Texas Instruments TMS320C6472 Bedienungsanleitung
TMS320C6472/TMS320TCI648x DSP
64-Bit Timer
User's Guide
Literature Number: SPRU818B
December 2005–Revised September 2010
2SPRU818B–December 2005–Revised September 2010
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Preface ....................................................................................................................................... 5
1 Introduction to the Timer ...................................................................................................... 6
2 Timer Modes ....................................................................................................................... 8
2.1 64-Bit Timer Mode ....................................................................................................... 8
2.2 Dual 32-Bit Timer Modes ............................................................................................... 8
2.3 Counter and Period Registers Used in GP Timer Modes ........................................................ 12
3 Timer Operation ................................................................................................................ 13
3.1 Timer Mode Selection ................................................................................................. 13
3.2 Timer Enabling ......................................................................................................... 13
3.3 Timer Clock Source Selection ........................................................................................ 14
3.4 Timer Output Mode Selection ........................................................................................ 14
3.5 Timer Counting ......................................................................................................... 15
3.6 Timer Reset Sources .................................................................................................. 15
3.7 Timer Interrupt Rate ................................................................................................... 15
3.8 Timer Emulation Modes ............................................................................................... 16
3.9 Timer Operation Boundary Conditions .............................................................................. 16
3.10 Initializing the Timer ................................................................................................... 18
4 Watchdog Timer Mode ....................................................................................................... 19
4.1 Timer Output Signal and Timer Interrupt Signal in Watchdog Mode ............................................ 19
4.2 Watchdog Timer Mode Restrictions ................................................................................. 19
4.3 Watchdog Timer Mode Operation ................................................................................... 19
4.4 Watchdog Timer Register Write Protection ......................................................................... 22
5 Timer Registers ................................................................................................................. 23
5.1 Emulation Management and Clock Speed Register (EMUMGT_CLKSPD) .................................... 24
5.2 Timer Counter Registers (CNTHI and CNTLO) .................................................................... 25
5.3 Timer Period Registers (PRDHI and PRDLO) ..................................................................... 26
5.4 Timer Control Register (TCR) ........................................................................................ 27
5.5 Timer Global Control Register (TGCR) ............................................................................. 30
5.6 Watchdog Timer Control Register (WDTCR) ....................................................................... 31
Appendix A Revision History ...................................................................................................... 32
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List of Figures
1 Timer Block Diagram ....................................................................................................... 7
2 Generation of the Internal Timer Clock .................................................................................. 7
3 64-Bit Timer Mode Block Diagram........................................................................................ 8
4 Dual 32-Bit Timers Chained Mode Block Diagram ..................................................................... 9
5 Dual 32-Bit Timers Chained Mode Example........................................................................... 10
6 Dual 32-Bit Timers Unchained Mode Block Diagram................................................................. 10
7 Dual 32-Bit Timers Unchained Mode Example........................................................................ 11
8 Timer Clock Source Block Diagram..................................................................................... 14
9 32-Bit Timer Counter Overflow Example............................................................................... 17
10 Timer Initialization ......................................................................................................... 18
11 Timer in Watchdog Timer Mode......................................................................................... 20
12 Watchdog Timer Operation State Diagram ............................................................................ 21
13 Emulation Management and Clock Speed Register (EMUMGT_CLKSPD) ....................................... 24
14 64-Bit Timer Counter Register........................................................................................... 25
15 Timer Counter Registers (CNTHI and CNTLO) ....................................................................... 25
16 64-Bit Timer Period Register............................................................................................. 26
17 Timer Period Registers (PRDHI and PRDLO)......................................................................... 26
18 Timer Control Register (TCR)............................................................................................ 27
19 Timer Global Control Register (TGCR)................................................................................. 30
20 Watchdog Timer Control Register (WDTCR) .......................................................................... 31
List of Tables
1 Counter and Period Registers Used in GP Timer Modes............................................................ 12
2 Timer Mode Selection..................................................................................................... 13
3 Timer Enabling............................................................................................................. 13
4 Timer Clock Source Selection ........................................................................................... 14
5 Timer Emulation Modes Selection ...................................................................................... 16
6 Timer Operation When Timer Count = 0 and Timer Period = 0..................................................... 16
7 Reading Counter Registers .............................................................................................. 17
8 Timer Registers............................................................................................................ 23
9 Emulation Management and Clock Speed Register (EMUMGT_CLKSPD) Field Descriptions................. 24
10 Timer Counter Registers (CNTHI and CNTLO) Field Descriptions................................................. 25
11 Timer Period Registers (PRDHI and PRDLO) Field Descriptions................................................... 26
12 Timer Control Register (TCR) Field Descriptions ..................................................................... 27
13 Timer Global Control Register (TGCR) Field Descriptions........................................................... 30
14 Watchdog Timer Control Register (WDTCR) Field Descriptions.................................................... 31
15 TCI648x/C6472 Timer Revision History................................................................................ 32
4List of Figures SPRU818B–December 2005–Revised September 2010
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Preface
SPRU818B–December 2005–Revised September 2010
Read This First
About This Manual
This document provides an overview of the 64-bit timer in the TMS320TCI648x/TMS320C6472 DSP. The
timer can be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a
watchdog timer. When configured as dual 32-bit timers, each half can operate in conjunction (chain mode)
or independently (unchained mode) of each other.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the C6000™ devices and related support tools. Copies of these
documents are available on the Internet. Tip: Enter the literature number in the search box provided at
www.ti.com.
SPRU189 —TMS320C6000 DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C6000 digital signal processors
(DSPs).
SPRU198 —TMS320C6000 Programmer's Guide. Describes ways to optimize C and assembly code for
the TMS320C6000™ DSPs and includes application program examples.
SPRU301 —TMS320C6000 Code Composer Studio Tutorial. Introduces the Code Composer Studio™
integrated development environment and software tools.
SPRU321 —Code Composer Studio Application Programming Interface Reference Guide.
Describes the Code Composer Studio™ application programming interface (API), which allows you
to program custom plug-ins for Code Composer.
SPRU871 —TMS320C64x+ Megamodule Reference Guide. Describes the TMS320C64x+ digital signal
processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
C6000, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
5
SPRU818B–December 2005–Revised September 2010 Preface
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User's Guide
SPRU818B–December 2005–Revised September 2010
C6472/TCI648x 64-Bit Timer
1 Introduction to the Timer
The timer can be configured in one of three modes using the timer mode (TIMMODE) bits in the timer
global control register (TGCR): a 64-bit general-purpose (GP) timer, dual 32-bit timers (TIMLO and
TIMHI), or a watchdog timer. When configured as dual 32-bit timers, each half can operate dependently
(chain mode) or independently (unchained mode) of each other.
At reset, the timer is configured as a 64-bit GP timer. The watchdog timer function can be enabled if
desired, via the TIMMODE bits in timer global control register (TGCR) and WDEN bit in the watchdog
timer control register (WDTCR). Once the timer is configured as a watchdog timer, it cannot be
re-configured as a regular timer until a device reset occurs.
The timer has two input pins for C6472/TCI6486 devices (TINPL and TINPH), one input pin for TCI6482,
TCI6484, TCI6487/88 devices (TINPL), and one output pin (TOUTL). The timer control register (TCR)
controls the function of the input and output pin.
Figure 1 shows a high-level block diagram of the timer circuitry.
6C6472/TCI648x 64-Bit Timer SPRU818B–December 2005–Revised September 2010
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INVINP
INVOUTP
TSTAT
CLKSRC
ENAMODE
Configuration
bus
Equal comparator
Count
enable
Timer period
register
Timer counter
register
CP
PWID (CP = 0)
Pulse generator
Internal clock
Gated
internal clock
TDDRHI bits
PSCHI bits
TINPL
TINPH (C6472/TCI6486 only)
TOUTL
External clock
Input clock
TIEN
0
1
0 1
TIMxxRS
Timer output
Interrupt to CPU
Event to EDMA controller
DSP
PLL1
controller
DSP input clock Internal timer clock
Timer
Timer/prescaler
counter
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Introduction to the Timer
Figure 1. Timer Block Diagram
The timer can be driven by an external clock at the timer input pin (TINPL) or by the divide-down clock
rate of the internal clock, as shown in Figure 2. For C6472/TCI6486 devices, TINPH can be used to drive
the higher 32-bit timer, TIMHI, in unchained mode. The internal clock is generated by the PLL1 controller
and is a divided-down version of the CPU clock. For more information, see the device-specific data
manual.
Figure 2. Generation of the Internal Timer Clock
7
SPRU818B–December 2005–Revised September 2010 C6472/TCI648x 64-Bit Timer
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CNTHI
Internal
clock
External clock
via TINPL
64-bit timer counter Timer period
PRDHI
Input clock
CLKSRC
Gated internal clock
CP_LO
PWID_LO (CP_LO = 0)
Pulse generator
Timer interrupt (TINTLO) to CPU
Timer event (TEVTLO) to EDMA controller
INVOUTP_LO
TSTAT_LO bit in TCR
Output via TOUTL
Equality comparator
CNTLO
PRDLO
Timer Modes
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2 Timer Modes
2.1 64-Bit Timer Mode
The timer can be configured as a 64-bit general-purpose (GP) timer, using the TIMMODE bits in TGCR
register. At reset, the timer is in 64-bit GP timer mode.
In this mode, the timer operates as a 64-bit up-counter, as shown in Figure 3. The counter registers
(CNTLO, CNTHI) and the period registers (PRDLO, PRDHI) form a 64-bit timer counter register and a
64-bit timer period register, respectively. When the timer is enabled (see Section 3.3), the timer counter
starts incrementing by 1 at every timer input clock cycle. When the timer counter matches the timer period,
it generates a maskable timer interrupt (TINTLO), a timer event (TEVTLO), and an output signal on the
timer output pin, TOUTL. When in pulse mode (CP_LO = 0), the timer output pin (TOUTL) asserts a pulse
that is 1, 2, 3, or 4 timer clock cycles wide, depending on the setting of the pulse width (PWID_LO) bits in
timer control register TCR. When the timer is configured in continuous mode, the timer counter is reset to
0 on the cycle after the timer counter reaches the timer period. The timer can be stopped, restarted, reset,
or disabled using the bits of the timer control register.
Figure 3. 64-Bit Timer Mode Block Diagram
2.2 Dual 32-Bit Timer Modes
The timer can be broken down into two 32-bit timers, using the TIMMODE bits in TGCR. In this mode, the
two 32-bit timers can be operated in conjunction with each other (chained mode) or independently
(unchained mode).
8C6472/TCI648x 64-Bit Timer SPRU818B–December 2005–Revised September 2010
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CNTHI
Internal
clock
External clock
via TINPL
32-bit prescale counter Prescale period
Equality comparator
PRDHI
Input clock
32-bit prescaler
(TIMHI)
32-bit timer
(TIMLO)
CP_LO
PWID_LO (CP_LO = 0)
Pulse generator
CLKSRC
Gated internal clock
Timer interrupt (TINTLO) to CPU
Timer event (TEVTLO) to EDMA controller
INVOUTP_LO
TSTAT bit in TCR
Output via TOUTL
CNTLO
32-bit timer counter Timer period
Equality comparator
PRDLO
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Timer Modes
2.2.1 Chained Mode
In the chained mode, shown in Figure 4, one 32-bit timer (TIMHI) is used as a 32-bit prescaler to a second
timer (TIMLO).
The 32-bit prescaler (TIMHI) uses the counter register (CNTHI) and the period register (PRDHI) to form a
32-bit prescale counter register and a 32-bit prescale period register, respectively. When the timer is
enabled, the prescale counter starts incrementing by 1 at every timer input clock cycle. One cycle after the
prescale counter matches the prescale period, a clock signal is generated and the prescale counter
register is reset to 0 (see the example in Figure 5).
The other 32-bit timer (TIMLO) uses the counter register (CNTLO) and the period register (PRDLO) to
form a 32-bit timer counter register and a 32-bit timer period register, respectively. This timer is clocked by
the output clock from the prescaler (see the example in Figure 5). The timer counter increments by 1 at
every prescaler output clock cycle. When the timer counter matches the timer period, a maskable timer
interrupt (TINTLO), a timer EDMA event (TEVTLO), and an output signal are generated. When in pulse
mode (CP_LO = 0), the timer output (TOUTL) asserts a pulse that is 1, 2, 3, or 4 timer clock cycles wide,
depending on the setting of the pulse width (PWID) bits in the timer control register (TCR). When the timer
is configured in continuous mode, the timer counter is reset to 0 on the cycle after the timer counter
reaches the timer period. The timer can be stopped, restarted, reset, or disabled using the bits of the timer
control register. The timer control register (TCR) does not control the TIMHI in this mode.
Figure 4. Dual 32-Bit Timers Chained Mode Block Diagram
9
SPRU818B–December 2005–Revised September 2010 C6472/TCI648x 64-Bit Timer
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200 201 202 0 1 2
Prescale counter
(CNTHI)
T
(CNTLO)
imer counter 3 4
32-bit prescaler settings: count = CNTHI = 200; period = PRDHI = 202
32-bit timer settings: count = CNTLO = 3; period = PRDLO= 4
Prescale counter reset
Timer counter incremented
Internal
clock
Input clock
TSTAT bit in TCR
CP_LO
PWID_LO
(CP_LO = 0)
32-bit timer with 4-bit prescaler
(TIMHI)
32-bit timer
(TIMLO)
Timer interrupt
(TINTHI) to CPU
Timer event (TEVTHI)
to EDMA controller
Internal
clock
External clock
via TINPL
Input clock
CP_HI
PWID_HI (CP_HI = 0)
Pulse generator
CLKSRC
Gated internal clock
Timer interrupt (TINTLO) to CPU
Timer event (TEVTLO) to EDMA controller
INVOUTP_LO
TSTAT bit in TCR
Output via TOUTL
CNTLO
32-bit timer counter Timer period
Equality comparator
PRDLO
Pulse generator
CNTHI
32-bit timer counter Timer period
Equality comparator
PRDHI
TDDRHI
4-bit prescale counter Prescale period
Equality comparator
PSCHI
Timer Modes
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Figure 5. Dual 32-Bit Timers Chained Mode Example
2.2.2 Unchained Mode
In the unchained mode, shown in Figure 6, the timer can operate as two independent 32-bit timers. One
32-bit timer (TIMHI) can be configured as a 32-bit timer being clocked by a 4-bit prescaler. The other
(TIMLO) can be used as a 32-bit timer.
Figure 6. Dual 32-Bit Timers Unchained Mode Block Diagram
10 C6472/TCI648x 64-Bit Timer SPRU818B–December 2005–Revised September 2010
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