Transmeta Crusoe TM5500 Leitfaden

TM5500/TM5800

System Design Guide

July 17, 2002

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Transmeta Corporation

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July 17, 2002

TM5500/TM5800 System Design Guide

Crusoe™ Processor Model TM5500/TM5800

System Design Guide

Revision 1.3

Revision History:

1.0 July 2, 2001 - first release

1.1 December 6, 2001 - updated schematics, reorganized and added new information, misc corrections

1.2 June 17, 2002 - changed DDR interface spec to one bank only, removed “Preliminary” mark

1.3 July 17, 2002 - updated MAX1718 core power supply example, removed ISL6211 and FAN5250 examples

July 17, 2002

Table of Contents

List of Tables ..........................................................................................................................................5

List of Figures .........................................................................................................................................7

Chapter 1 Introduction and Naming Conventions ................................................................................................9

1.1 Overview.....................................................................................................................................9

1.2 Reference Documents ..............................................................................................................10

1.3 Naming Conventions.................................................................................................................10

1.3.1 Power Management Mode Terms ..............................................................................11

1.3.2 Power Network Names...............................................................................................12

1.3.3 Signal Names .............................................................................................................12

Chapter 2 Example System Block Diagram and Schematics ............................................................................13

2.1 System Block Diagram..............................................................................................................13

2.2 Processor Schematics ..............................................................................................................15

Chapter 3 Processor Power Supplies and Power Management ........................................................................21

3.1 Power Supplies.........................................................................................................................21

3.1.1 Core Power Supply Requirements ............................................................................22

3.1.2 VRM Core Power Supply Example.............................................................................25

3.1.3 PLL Power Supply .....................................................................................................30

3.1.4 I/O Power Supplies.....................................................................................................33

3.1.5 Decoupling Capacitors................................................................................................34

3.2 Power Supply Sequencing .......................................................................................................35

3.2.1 Power Sequencing Requirements ..............................................................................35

3.2.2 Power Sequencing Circuit Examples..........................................................................36

3.3 Power Supply Voltage Supervisor.............................................................................................38

3.4 POWERGOOD Block Diagram Example..................................................................................40

3.5 State Transition Timing Requirements......................................................................................42

Chapter 4 DDR Memory Design ............................................................................................................................51

4.1 DDR Memory Interface .............................................................................................................51

4.2 Clock Enable Isolation...............................................................................................................52

4.3 Signal Termination....................................................................................................................52

4.4 DDR Reference Voltage............................................................................................................53

4.4.1 DDR Reference Voltage Noise Filter Circuit...............................................................53

4.5 DDR Memory Interface Design Guidelines ...............................................................................54

4.6 PCB Placement and Routing Example .....................................................................................55

4.7 DDR SDRAM Schematics.........................................................................................................59

Chapter 5 SDR Memory Design ............................................................................................................................65

5.1 SDR Memory Interface..............................................................................................................65

July 17, 2002

Table of Contents

5.2 SDR Memory Interface Design Guidelines................................................................................66

5.2.1 Bank Selection............................................................................................................66

5.2.2 Clock Enable Isolation During Power-down States.....................................................67

5.2.3 Signal Termination......................................................................................................67

5.2.4 Miscellaneous Notes...................................................................................................67

5.3 SDR SDRAM Layout Notes.......................................................................................................67

5.3.1 SDR SDRAM Memory Interface Timing......................................................................67

5.3.2 Example Design Strategy............................................................................................68

5.3.3 Write Timing ...............................................................................................................69

5.3.4 Read Timing................................................................................................................70

5.3.5 Uncertainty in the Feedback Calculation.....................................................................71

5.3.6 Using Soldered-down Memory....................................................................................71

5.3.7 Recommended Design Procedure..............................................................................76

5.3.8 Design Example..........................................................................................................77

5.4 SDR SDRAM Schematics .........................................................................................................77

Chapter 6 System Design Considerations ...........................................................................................................83

6.1 Clocking ....................................................................................................................................83

6.2 System Reset ............................................................................................................................86

6.3 Signal Pull-ups and Pull-downs.................................................................................................87

6.4 Mode-bit ROM ..........................................................................................................................89

6.5 Code Morphing Software ROM .................................................................................................91

6.5.1 Serial Flash ROM Interface.........................................................................................91

6.5.2 Serial Flash ROM Write Protection Circuit..................................................................93

6.5.3 Combined BIOS/CMS Parallel ROM Interface............................................................96

6.6 Southbridge ...............................................................................................................................98

6.6.1 Qualified Southbridge Devices....................................................................................98

6.6.2 Using CLKRUN...........................................................................................................98

6.6.3 Southbridge Schematics .............................................................................................98

6.7 Thermal Design .......................................................................................................................103

6.8 Thermal Diode and Thermal Sensor ......................................................................................103

6.8.1 Thermal Sensor Circuit .............................................................................................103

6.8.2 Thermal Sensor Issues .............................................................................................104

6.8.3 Thermal Sensor Layout.............................................................................................104

6.8.4 Thermal Sensor Example Schematic........................................................................105

6.9 TDM Debug Interface Connection...........................................................................................107

Chapter 7 PCB Layout Guidelines ......................................................................................................................111

7.1 PCB Design Layout.................................................................................................................111

7.2 Example PCB Fabrication Notes.............................................................................................112

7.3 Board Design Guidelines.........................................................................................................113

7.3.1 Printed Circuit Board Stackup ..................................................................................113

7.3.2 Allegro Standard Spacing Constraints .....................................................................113

7.3.3 Allegro Extended Spacing Constraints .....................................................................114

7.3.4 Allegro Extended Physical (Lines/Vias) Constraints ................................................115

7.3.5 Allegro Extended Electrical (Lines/Vias) Constraints ...............................................115

7.4 Footprint and Pin Escape Diagram .........................................................................................116

Appendix A System Design Checklists .................................................................................................................117

Appendix B Serial Write-protection PLD Data .......................................................................................................123

Index .....................................................................................................................................................129

July 17, 2002

List of Tables

Table 1: Supported ACPI Processor States ......................................................................11

Table 2: Supported ACPI System States...........................................................................11

Table 3: Power Net Naming Conventions..........................................................................12

Table 4: Signal Naming Conventions ................................................................................12

Table 5: Core Power Supply Requirements for TM5500/TM5800 Processors..................22

Table 6: Default Power-on Start Voltage VRDA (VID) Output Codes................................23

Table 7: VID/VRDA Values and Output Voltages for MAX1718 VRM...............................24

Table 8: MAX1718 Core Power Supply Output Control Selector ......................................25

Table 9: MAX1718 DSX Voltage Configuration.................................................................26

Table 10: Power Supply Sequencing Timing Specifications................................................35

Table 11: DDR SDRAM Memory Configurations.................................................................51

Table 12: SDR SDRAM Memory Configurations.................................................................65

Table 13: SDR SDRAM Interface Device Specifications.....................................................68

Table 14: Write Timing Compensation ................................................................................69

Table 15: Signal Pull-up/Pull-down Requirements ..............................................................87

Table 16: PLD Pinout...........................................................................................................94

Table 17: Recommended Eight Layer PCB Stackup.........................................................113

Table 18: Standard Spacing/Line/Via Constraints ............................................................113

Table 19: Extended Global Spacing/Line/Via Constraints ................................................114

Table 20: Extended Physical Constraints .........................................................................115

Table 21: Extended Electrical Constraints ........................................................................115

July 17, 2002

List of Tables

July 17, 2002

List of Figures

Figure 1: Example Schematic Naming System...................................................................11

Figure 2: Example System Block Diagram .........................................................................13

Figure 3: PLL / Processor Core Voltage Tracking Requirement.........................................30

Figure 4: Power Supply Sequencing...................................................................................35

Figure 5: Recommended DDR Reference Voltage Circuit with Ferrite Bead Noise Filter ..53

Figure 6: Recommended 4-Device DDR Memory Chip Placement....................................55

Figure 7: Recommended 4-Device DDR Memory Signal Routing - Top Layer...................56

Figure 8: Recommended 4-Device DDR Memory Signal Routing - Internal Layer.............57

Figure 9: Recommended 4-Device DDR Memory Signal Routing - Bottom Layer..............58

Figure 10: Physical SDRAM Configurations .........................................................................68

Figure 11: Read Timing Compensation ................................................................................70

Figure 12: Adjustment of CLKIN Delay.................................................................................71

Figure 13: Optimum Placement and Routing........................................................................72

Figure 14: Sub-optimal Placement........................................................................................72

Figure 15: Data Structure Diagram.......................................................................................73

Figure 16: Address Line Structure Diagram..........................................................................74

Figure 17: Clock Line Structure Diagram..............................................................................74

Figure 18: Data Mask Structure Diagram .............................................................................75

Figure 19: Clock Enable Structure Diagram .........................................................................75

Figure 20: System Reset Diagram........................................................................................86

Figure 21: Schematic Diagram of Serial Flash Write-protection PLD in System ..................95

Figure 22: Recommended CLKRUN Circuit .........................................................................98

Figure 23: Transmeta Debug Connector (TDCA)...............................................................108

Figure 24: Mechanical Footprint .........................................................................................116

Figure 25: Write Protection TSSOP-24 JEDEC Fuse Map.................................................124

Figure 26: Write Protection TSSOP-24 CUPL Source Code..............................................125

July 17, 2002

List of Figures

July 17, 2002

Chapter 1

Introduction and Naming

Conventions

1.1 Overview

This design guide is organized into the following sections:

•Introduction and Naming Conventions (this chapter) introduces the conventions used in this document,

including possible differences between hardware names for power supplies, pins, etc. and the reference

schematics used throughout the document.

• Chapter 2, Example System Block Diagram and Schematics presents the Crusoe TM5500/TM5800

processor in the context of a block diagram that shows necessary components and their connections.

The reference schematic for the processor itself is also provided.

• Chapter 3, Processor Power Supplies and Power Management describes the power supply network in

detail.

• Chapter 4, DDR Memory Design provides design guidelines and layout requirements for incorporating

DDR SDRAM memory into a design.

• Chapter 5, SDR Memory Design provides design guidelines and layout requirements for incorporating

SDR SDRAM memory into a design.

• Chapter 6, System Design Considerations describes a variety of design issues, including clocking, reset,

ROM interfaces, signal pull-up/pull-down requirements, thermal sensor, and southbridge interfaces.

• Chapter 7, PCB Layout Guidelines discusses physical issues related to memory and component

interfaces, power supplies, signal integrity, mounting and spacing constraints, tolerances and fabrication

guidelines, and footprint and pin escape diagrams.

• Appendix A, System Design Checklists includes cross-referenced checklists to follow while designing a

system.

• Appendix B, Serial Write-protection PLD Data includes the JEDEC fuse map and CUPL source code for

the write-protection PLD required for serial-ROM Code Morphing software placement. This issue is

described in Serial Flash ROM Write Protection Circuit on page 93 in Chapter 6, System Design

Considerations.

•AnIndex is also included.

July 17, 2002

Introduction and Naming Conventions

1.2 Reference Documents

The following documents are available from Transmeta for use in conjunction with this design guide. Some of

these documents are extensively referenced in the design guide, and should be consulted as specified in the

text.

• TM5500/TM5800 Data Book

• TM5500/TM5800 Package Specifications and Manufacturing Guide

•TM5500/TM5800 Thermal Design Guide

•TM5500/TM5800 Development and Manufacturing Guide

•TM5500/TM5800 BIOS Programmer’s Guide

•TM5500/TM5800 IBIS Models

•TM5500/TM5800 BSDL file

• TM5500/TM5800 Code Morphing Software Release Notes

• TM5500/TM5800 Technical Bulletins and Errata documents

1.3 Naming Conventions

Power supply and signal names used in the Data Book and other hardware-specific materials can be different

from those used on the reference schematics. This section shows the terms used in the System Design

Guide and the reference schematics, and correlates them with the hardware-specific names used elsewhere.

In general, the hardware symbols in the schematics show the hardware names for each item (signal or power

line). The alphanumeric marker at the connection between symbol and line is the ball number, described in

detail in the Data Book. The line itself shows the schematic net name, i.e. the name that is used throughout

this document to refer to that net/signal/line.

Note

The block diagram and reference schematics included in this book offer general guidelines for integrating

TM5500/TM5800 processors into product designs. For detailed processor-specific information, consult the

reference documents listed below.

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