VIA Technologies QSM-8Q60 Leitfaden

1.01-09022020-175700

DESIGN GUIDE

Carrier Board

for VIA QSM-8Q60 Qseven™ ARM module

No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language,

in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written

permission of VIA Technologies, Incorporated.

Trademarks

All trademarks are the property of their respective holders.

Disclaimer

No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies makes no

warranties, implied or otherwise, in regard to this document and to the products described in this document. The information

provided in this document is believed to be accurate and reliable as of the publication date of this document. However, VIA

Technologies assumes no responsibility for the use or misuse of the information (including use or connection of extra

device/equipment/add-on card) in this document and for any patent infringements that may arise from the use of this document. The

information and product specifications within this document are subject to change at any time, without notice and without obligation

to notify any person of such change.

VIA Technologies, Inc. reserves the right the make changes to the products described in this manual at any time without prior notice.

Regulatory Compliance

FCC-A Radio Frequency Interference Statement

This equipment has been tested and found to comply with the limits for a class A digital device, pursuant to part 15 of the FCC rules.

These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a

commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in

accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a

residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his

personal expense.

Notice 1

The changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to

operate the equipment.

Notice 2

Shielded interface cables and A.C. power cord, if any, must be used in order to comply with the emission limits.

Notice 3

The product described in this document is designed for general use, VIA Technologies assumes no responsibility for the conflicts or

damages arising from incompatibility of the product. Check compatibility issue with your local sales representatives before placing

an order.

Carrier Board Design Guide for VIA QSM-8Q60

iii

Revision History

Revision

Date

Description

1.00 03/07/2017 Initial release

1.01 09/02/2020 Updated VIA logo and copyright year

Carrier Board Design Guide for VIA QSM-8Q60

Table of Contents

1. Introduction ...................................................................................................................................1

1.1. Document Overview.........................................................................................................................................1

1.2. Acronyms and Definitions ...............................................................................................................................2

1.3. Illustrations and Schematics............................................................................................................................3

2. General Carrier Board Recommendations ...............................................................................4

2.1. PCB Stackup Example.......................................................................................................................................4

2.1.1. Microstrip Versus Stripline Designs .......................................................................................................4

2.2. General Layout and Routing Guidelines ......................................................................................................6

2.2.1. Routing Styles and Topology ..................................................................................................................6

2.2.2. General Trace Attribute Recommendations ........................................................................................7

2.2.3. General Clock Routing Considerations .................................................................................................7

3. Qseven Specification Overview.................................................................................................9

3.1. Qseven Module Placement.............................................................................................................................9

3.2. Qseven Mechanical Characteristics...............................................................................................................9

3.3. VIA QSM-8Q60 Module and Carrier Board Dimensions........................................................................... 10

3.4.MXM Connector ............................................................................................................................................. 11

3.4.1. MXM Connector Dimensions................................................................................................................ 11

3.4.2. MXM Connector Footprint .................................................................................................................... 12

3.4.3. VIA QSM-8Q60 Module and MXM Connector Footprint ............................................................. 12

3.5. MXM Connector Pinouts............................................................................................................................... 13

4. Layout and Routing Recommendations ..................................................................................17

4.1. PCI Express Interface ..................................................................................................................................... 17

4.1.1. MiniPCIe Slot............................................................................................................................................ 17

4.1.2. PCI Express Layout and Routing Recommendations ....................................................................... 19

4.1.3. PCI Express Reference Schematics ...................................................................................................... 20

4.2. Ethernet Interface ........................................................................................................................................... 21

4.2.1. Ethernet Interface Topology................................................................................................................. 22

4.2.2. Gigabit Ethernet Layout and Routing Recommendations............................................................... 23

4.2.3. Gigabit Ethernet Reference Schematics ............................................................................................. 24

4.3. USB Interface ................................................................................................................................................... 25

4.3.1. USB Layout and Routing Recommendations ..................................................................................... 25

4.3.2. USB Reference Schematics.................................................................................................................... 28

4.4. LVDS Interface................................................................................................................................................. 29

4.4.1. LVDS Layout and Routing Recommendations................................................................................... 30

4.4.2. LVDS Reference Schematics ................................................................................................................. 32

4.5. HDMI Interface ................................................................................................................................................ 33

4.5.1. HDMI Layout and Routing Recommendations.................................................................................. 34

4.5.2. HDMI Reference Schematics................................................................................................................. 35

4.6. Audio Interface ............................................................................................................................................... 36

4.6.1. Audio Layout and Routing Recommendations ................................................................................. 36

4.6.2. Audio Reference Schematics ................................................................................................................ 37

Carrier Board Design Guide for VIA QSM-8Q60

List of Figures

Figure 1: Conventions pertaining to schematics............................................................................................................3

Figure 2: Six-layer microstrip PCB stackup example....................................................................................................4

Figure 3: Six-layer stripline PCB stackup example .......................................................................................................4

Figure 4: Point-to-point and multi-drop examples ......................................................................................................6

Figure 5: Daisy-chain example ..........................................................................................................................................6

Figure 6: Alternate multi-drop example.........................................................................................................................6

Figure 7: Suggested clock trace spacing.........................................................................................................................7

Figure 8: Clock trace layout in relation to the ground plane ....................................................................................8

Figure 9: Series termination for multiple clock loads .................................................................................................8

Figure 10: Qseven module placement on carrier board PCB....................................................................................9

Figure 11: Carrier board with Qseven module installed ............................................................................................9

Figure 12: Qseven module and carrier board height distribution ............................................................................9

Figure 13: Dimensions of the VIA QSM-8Q60 module (top view) ....................................................................... 10

Figure 14: Dimensions of the carrier board (top view) ............................................................................................ 10

Figure 15: Dimensions of the MXM connector (top view) ...................................................................................... 11

Figure 16: Dimensions of the MXM connector (side view)..................................................................................... 11

Figure 17: Carrier board PCB footprint for the MXM connector............................................................................ 12

Figure 18: PCB footprint for Qseven module inserted in the MXM connector on the carrier board............ 12

Figure 19: MXM connector schematics ........................................................................................................................ 16

Figure 20: MiniPCIe card and slot diagram.................................................................................................................. 18

Figure 21: MiniPCI Express interface topology example ......................................................................................... 19

Figure 22: PCI Express trace spacing diagram ............................................................................................................ 19

Figure 23: MiniPCIe slot reference circuitry ................................................................................................................ 20

Figure 24: Gigabit Ethernet layout recommendations (integrated magnetic module) ..................................... 22

Figure 25: Gigabit Ethernet reference circuitry........................................................................................................... 24

Figure 26: USB differential signal layout recommendations ................................................................................... 25

Figure 27: USB differential signal routing example................................................................................................... 26

Figure 28: USB 2.0 trace spacing diagram ................................................................................................................... 26

Figure 29: USB host reference circuitry........................................................................................................................ 28

Figure 30: USB client reference circuitry...................................................................................................................... 28

Figure 31: LVDS panel interface implementation ...................................................................................................... 30

Figure 32: LVDS connector example ............................................................................................................................ 32

Figure 33: LVDS panel power reference circuitry...................................................................................................... 32

Figure 34: LVDS backlight reference circuitry............................................................................................................. 32

Figure 35: HDMI interface connector diagram ........................................................................................................... 33

Figure 36: HDMI interface reference circuitry............................................................................................................. 35

Figure 37: Onboard I2S audio codec implementation example ............................................................................ 36

Figure 38: I2S Audio Codec implementation example ............................................................................................. 37

Carrier Board Design Guide for VIA QSM-8Q60

List of Tables

Table 1: Acronyms and definitions ..................................................................................................................................2

Table 2: General six-layer microstrip PCB stackup ......................................................................................................5

Table 3: PCB stack-up detail .............................................................................................................................................5

Table 4: Recommended trace width and spacing........................................................................................................7

Table 5: MXM connector sample.................................................................................................................................. 11

Table 6: MXM connector pinout ................................................................................................................................... 15

Table 7: PCI Express signal group and definition...................................................................................................... 17

Table 8: MiniPCIe slot pinout definition ...................................................................................................................... 18

Table 9: PCI Express interface routing guidelines ..................................................................................................... 20

Table 10: PCI Express interface layout guidelines .................................................................................................... 20

Table 11: PCI Express interface trace properties....................................................................................................... 20

Table 12: Ethernet signal definition.............................................................................................................................. 21

Table 13: Gigabit Ethernet interface routing guidelines .......................................................................................... 23

Table 14: Gigabit Ethernet interface layout guidelines............................................................................................ 23

Table 15: Gigabit Ethernet interface trace properties .............................................................................................. 24

Table 16: USB signal definition...................................................................................................................................... 25

Table 17: USB interface routing guidelines................................................................................................................. 26

Table 18: USB interface layout guidelines .................................................................................................................. 27

Table 19: USB interface trace properties..................................................................................................................... 27

Table 20: LVDS signal definition ................................................................................................................................... 29

Table 21: LVDS interface routing guidelines .............................................................................................................. 30

Table 22: LVDS interface layout guidelines................................................................................................................ 31

Table 23: LVDS interface trace properties .................................................................................................................. 31

Table 24: HDMI interface signal definition ................................................................................................................. 33

Table 25: HDMI interface routing guidelines ............................................................................................................. 34

Table 26: HDMI interface layout guidelines ............................................................................................................... 34

Table 27: HDMI interface trace properties ................................................................................................................. 34

Table 28: Audio interface signal definition................................................................................................................. 36

Table 29: Audio interface routing guidelines............................................................................................................. 36

Table 30: Audio interface layout guidelines .............................................................................................................. 37

Table 31: Audio interface trace properties................................................................................................................. 37

Carrier Board Design Guide for VIA QSM-8Q60

1. Introduction

This document provides design guidelines to the developers of a custom Qseven compliant carrier board

that supports the features of VIA QSM-8Q60™module. This document includes the layout and routing

guidelines for general board designs and major underlying interfaces such as PCI Express, Gigabit Ethernet,

USB, LVDS, HDMI and Audio. In addition, the document includes the mechanical information of the

ruggedized MXM connector that provides high speed interfaces between the carrier board and the

module.

Please note that this document is considered to be a reference guide only. This document is not intended

to be a specification. All information and examples listed below are considered to accurate as of the

publication date; however developers must be aware that this document is only a referencing guide.

1.1. Document Overview

A brief description of each chapter is given below.

Chapter 1: Introduction

Briefly introduces the structure of the design guide document.

Chapter 2: General Carrier Board Recommendations

General design schemes and recommended layout rules are shown in this chapter.

Chapter 3: Qseven Specification Overview

Detailed information about the MXM connector placement and dimensions are described.

Chapter 4: Layout and Routing Recommendations

Detailed layout and routing guidelines for each major interface are described.

Appendix A: Carrier Board Reference Schematics

Reference schematics of COMEDB2 evaluation carrier board.

Carrier Board Design Guide for VIA QSM-8Q60

1.2. Acronyms and Definitions

Term

Description

ASIC

Application-Specific Integrated Circuit

EMI Electromagnetic Interference

GBE Gigabit Ethernet

HDMI

High-Definition Multimedia Interface

IC Integrated Circuit

IEEE Institute of Electrical and Electronics Engineers

Input/Output

Integrated Interchip Sound / Inter-IC Sound

LAN Local Area Network

LCD Liquid Crystal Display

LVDS

Low-Voltage Differential Signaling

MiniPCIe Mini PCI Express

MXM Mobile PCI Express Module

Not Connected / No Connection

OTG On-The-Go

PCB Printed Circuit Board

PCIe

Peripheral Component Interconnect Express

PCIe x1

PCI Express one lane

RJ-45 Registered Jack-45

USB

Universal Serial Bus

Table 1: Acronyms and definitions

Carrier Board Design Guide for VIA QSM-8Q60

1.3. Illustrations and Schematics

Illustrations and schematics depicted in this document may show the directional flow of signals.

Directional flow is indicated by the pointed ends of the arrow shapes. See Figure 1.

input signal flow output signal flow

bidirectional signal flow

Figure 1: Conventions pertaining to schematics

Carrier Board Design Guide for VIA QSM-8Q60

2. General Carrier Board Recommendations

This section contains general guidelines for the PCB stackup and the layout of traces. General guidelines

for routing style, topology, and trace attribute recommendations are also discussed.

2.1. PCB Stackup Example

Figure 2 illustrates an example of a PCB with a six-layer stackup. The stackup consists of three signal layers

and three reference (power and ground) layers. The three signal layers are referred to as the component

layer, inner layer and solder layer. The example below also shows the PCB stackup in a microstrip design.

Microstrip stackup design

Solder layer

Ground layer

Power layer

Inner layer

Ground layer

Component layer

Reference layer

Signal layers

Figure 2: Six-layer microstrip PCB stackup example

2.1.1. Microstrip Versus Stripline Designs

Carrier board designers can choose between two basic categories of PCB design: microstrip and stripline.

Microstrip designs have the outer signal layers exposed. Stripline designs have the outermost signal layers

shielded by reference layers.

Stripline stackup design

Ground layer

Solder layer

Power layer

Inner layer

Component layer

Ground layer

Reference layer

Signal layers

Figure 3: Six-layer stripline PCB stackup example

The choice of microstrip or stripline design depends on the application for which the carrier board is

being designed. If the carrier board is being designed for locations where sensitivity to EMI is an issue, a

stripline design is recommended for reducing EMI and noise coupling. For applications where the

tolerance for EMI levels is greater, a microstrip design is recommended to reduce costs. Due to the

inherent nature of stripline PCB stacks, broad-side coupling is possible.

Andere Handbücher für QSM-8Q60

Inhaltsverzeichnis

Andere VIA Technologies Trägerplatine Handbücher

VIA Technologies

VIA Technologies SOM-9X50-STK Bedienungsanleitung

Beliebte Trägerplatine Handbücher anderer Marken

CTJ

CTJ TX2 Bedienungsanleitung

Amfeltec

Amfeltec AngelShark Series Bedienungsanleitung

Advantech

Advantech CPC-2420 Installations- und Betriebshandbuch

Bob's Space Racers

Bob's Space Racers BSR-3000 Bedienungsanleitung

RTimes

RTimes Z509 Bedienungsanleitung

mikroElektronika

mikroElektronika Clicker 2 Bedienungsanleitung

Connect Tech

Connect Tech Sprocket Carrier Bedienungsanleitung

ETAS

ETAS ES5372.1-B Bedienungsanleitung

TQ-Systems

TQ-Systems MBa7x Bedienungsanleitung

Arbor Technology

Arbor Technology PBE-1101 Bedienungsanleitung

Aetina

Aetina AN310 Bedienungsanleitung

RTimes

RTimes Z603L/LE Bedienungsanleitung

Hemisphere GPS

Hemisphere GPS SBX-4 Montageanleitung

REDEKOP

REDEKOP Actuated Tailboard Bedienungsanleitung

XJTAG

XJTAG SPEA 3030 Bedienungsanleitung

Exor

Exor GigaSOM gS01 Bedienungsanleitung

Aaeon

Aaeon ECB-920A-A11 Bedienungsanleitung

ESD

ESD PCIe-XPIMC-Carrier Bedienungsanleitung