Vivid CLT-302R Bedienungsanleitung
CLT-302R & CLT-302L CAMERA LINK
TRANSLATOR
User’s Manual
Document # 201034, Rev 0.2, 7/15/2011
Vivid Engineering
418 Boston Turnpike #104 • Shrewsbury, MA 01545
Phone 508.842.0165 • Fax 508.842.8930
Table of Contents
1. Introduction 1
1.1. Overview 1
1.2. Features 3
1.3. Functional Description 4
1.3.1. Mode Switch Settings 9
1.4. Typical Application 10
1.5. Specifications 12
2. Interface 13
2.1. Front Panel Connections 13
2.1.1. Camera Connector Signals 14
2.1.2. Camera Cable Shielding and Grounding 14
2.1.3. Camera Cable Recommended Connectors 14
2.2. Rear Panel 51
2.2.1. Video Connector Signals 52
3. Mechanical 54
3.1. Dimensions 54
3.2. External Power Supply 55
4. Revision History 56
1
1. Introduction
1.1. Overview
The CLT-302R and CLT-302L Camera Link 1Translators enable the use of traditional
RS-422 and LVDS digital cameras with Camera Link frame grabbers. The “R” and “L”
versions support parallel RS-422 and LVDS digital camera data, respectively. The CLT-
302’s are extremely flexible and can convert a wide range of cameras from parallel digital
output to Camera Link base configuration with up-to 24-bit data.
Cameras with pixel clock rates as low as 2.5 MHz and as high as 85 MHz are supported.
Features include RS-232 communication support, a camera signal detect indicator, and
isolated DC power input.
The CLT-302’s are housed in sturdy, compact aluminum enclosures. A locking power
supply plug is optional.
1The Camera Link interface standard enables the interoperability of cameras and frame grabbers,
regardless of vendor. The Automated Imaging Association (AIA) sponsors the Camera Link
program including the oversight Camera Link Committee, the self-certification program, and the
product registry. The Camera Link specification may be downloaded from the AIA website, found
at www.machinevisiononline.org
2
V
ivid
E
ngineering
Camera Link Translator CLT-302R
RS-422 CAMERAPOWER LINK
V
ivid
E
ngineering
Camera Link Translator CLT-302L
LVDS CAMERAPOWER LINK
3
1.2. Features
•Enable use of RS-422 and LVDS cameras with Camera Link frame grabbers
•Also useful for converting parallel video from FPGA and imaging development
boards
•Camera Link “base” configuration interface, supports up-to 24-bit data
•“R” version supports RS-422 cameras
•“L” version supports LVDS cameras
•2.5 MHz to 85 MHz camera pixel clock range for “L” version
•2.5 MHz to 32 MHz camera pixel clock range for “R” version
•RS-232 camera communication support
•Selectable camera clock and timing signal polarities
•Link indicator identifies an active camera connection
•Isolated DC power input
•Minimal data pass-through latency
•Flow-through connector placement
•Sturdy, compact aluminum enclosure with mounting flange
•Multi-nation power supply included, locking power plug optional
•3-year warrantee
4
1.3. Functional Description
The CLT-302L & CLT-302R Camera Link Translators enable the use of traditional RS-
422 and LVDS digital cameras with Camera Link frame grabbers. Block diagrams of the
CLT-302R and CLT-302L are provided in Figures 1-1 and 1-2, respectively. The CLT-
302R is intended for use with RS-422 digital cameras and the CLT-302L for use with
LVDS (EIA-644) digital cameras.
The camera interface receives video data in parallel digital format using RS-422 or LVDS,
depending on CLT-302 version. The camera interface incorporates a 100-pin SCSI-style
connector.
The CLT-302 frame grabber interfaces incorporates the connector, signals, pinout, and
chipset in compliance with the Camera Link specification. The CLT-302 incorporates the
“base” configuration signal set, consisting of video data, camera control, and serial
communications.
RS-422
Receivers
RS-422
Receivers
RS-422
Receivers
Channel
Link
Transmitter
LVDS
Receiver
RS-422
Transmitter
RS-422 Rcvr
To RS-422 Camera
Video
Data
Camera
Control
Serial
Comm
(RS-422)
RS-422 Xmtr
Video
Data
Camera
Control
Serial
Comm
Link
To Camera Link Frame Grabber
CLT-302R Camera Link Translator
Polarity
Select
Clock
Multiplier
Pixel Data
Frame Valid,
Line Valid
Edge
Select
Clock
Mode Select Switch
LVDS Xmtr
LVDS RcvrRS-232 Rcvr
RS-232 Xmtr
Mux
Serial
Comm
(RS-232)
Link
Detect
comm select
Figure 1-1: CLT-302R Block Diagram
5
RS-422
Receivers
RS-422
Receivers
LVDS
Receivers
Channel
Link
Transmitter
LVDS
Receiver
LVDS
Transmitter
LVDS Rcvr
To LVDS Camera
Video
Data
Camera
Control
Serial
Comm
(LVDS)
LVDS Xmtr
Video
Data
Camera
Control
Serial
Comm
Link
To Camera Link Frame Grabber
CLT-302L Camera Link Translator
Polarity
Select
Clock
Multiplier
Pixel Data
Frame Valid,
Line Valid
Edge
Select
Clock
Mode Select Switch
LVDS Xmtr
LVDS RcvrRS-232 Rcvr
RS-232 Xmtr
Mux
Serial
Comm
(RS-232)
Link
Detect
comm select
Figure 1-2: CLT-302L Block Diagram
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The CLT-302 receives parallel digital camera data on the 100-pin camera connector and
maps the pixel data into the corresponding Camera Link “base” configuration format. The
CLT supports single-channel (monochrome) cameras with 8/10/12/14/16-bit pixels, dual-
channel 8/10/12-bit cameras, and 8-bit color cameras.
The latency (i.e. delay) of the video, control, and communication signals passing through
the CLT-302 is minimal. This is an important criteria in some time-critical application.
The delay for the camera video through the CLT-302 is only a few pixel clock periods.
See Table 1.1 for CLT-302 latency specifications.
Camera timing signal characteristics are selected using the rear-panel mode switch. One
switch position is used to select the polarity of the line valid signal, and a second switch
position is used to select the polarity of the frame valid signal. In most cases, a “high”
state on the line enable and frame enable signals is used to envelope valid lines and
frames of video data, respectively. The settings enable the user to select either active-high
or active-low polarities for each timing signal. Note that the frame enable signal is not
used in line scan applications. Switch settings are defined in Section 1.3.1.
Camera Link incorporates a data valid signal which is used to qualify the video data. This
signal is generated by the CLT-302 and sent to the Camera Link frame grabber. Most
LVDS and RS-422 digital cameras do not incorporate a data valid type signal. The CLT-
302 incorporates a provision for the rare cases in which a data valid is provided by the
camera. When the data valid pass-through dip switch position is raised, the CLT-302
passes the data valid signal from the camera to the frame grabber. The Camera Link data
valid input is active-high, qualifying the incoming video data when the signal is high. A
second dipswitch position, data valid polarity, supports either active-high or active-low
data valid signals from the camera. When the data valid pass-through dipswitch is in the
normal (low) position, the CLT-302 maintains the data valid signal sent to the frame
grabber in the high position. The only exception is when the clock multiplier is being used
which is discussed next.
Camera pixel clock characteristics are selected using the rear-panel mode switch. One
switch position is used to select which pixel clock edge, rising or falling, is used to sample
the data and timing signals received from the camera. Two additional switch positions are
used to enable the CLT-302 clock multiplier circuit. The clock multiplier supports the use
of camera with pixel clock frequency below the Camera Link 20MHz minimum by
“multiplying” the camera clock frequency before it is sent to the Camera Link frame
grabber.. For cameras with pixel clocks in the 10-19.99 MHz range, the clock multiplier is
used to 2x (i.e. double) the clock frequency. For cameras with pixel clocks in the 5-9.99
MHz range, the clock multiplier is used to 4x (i.e. quadruple) the clock frequency. For
cameras with pixel clocks in the 2.5-4.99 MHz range, the clock multiplier is used to 8x the
clock frequency.
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The result of using the clock multiplier is a 2x/4x/8x oversampling of camera data and
timing signals sent to the Camera Link frame grabber. When in 2x/4x/8x mode, the CLT-
302L & CLT-302R toggles the “data valid” signal defined in the Camera Link
Specification accordingly. If the frame grabber supports the data valid signal, the
oversampling affect is removed automatically. Otherwise, the oversampling is easily
removed in the frame grabber by adjusting the line timing (multiply by 2/4/8) and
decimating (divide by 2/4/8) the pixels in the “X” dimension. Two switch positions are
used to select camera clock characteristics. Switch settings are defined in Section 1.3.1.
The CLT-302 receives four LVDS camera control signals from the Camera Link frame
grabber and retransmits all four signals to the camera using LVDS or RS-422 signaling,
depending on CLT-302 version. These signals are often used to externally synchronize
the camera (i.e. EXSYNC). The camera may or may not require any or all of these
signals.
The CLT-302 routes the serial communication signals between the LVDS/RS-422 digital
camera and the Camera Link frame grabber. This supports host computer access to mode
control and status registers in the camera via the serial port included in the Camera Link
frame grabber. The camera may or may not incorporate a serial port. The CLT-302
supports differential signaling (LVDS or RS-422, depending on CLT-302 version) for the
camera serial port as well as RS-232 single-ended signaling which is used with some
LVDS/RS-422 cameras. A rear-panel dipswitch is used to select the camera serial port
signaling standard (RS-422/LVDS or RS-232). Note that the LVDS/RS-422 and RS-232
serial ports use different pins on the 100-pin camera connector. The camera cable must be
correctly wired for the desired serial port signaling standard.
The CLT-302L & CLT-302R frame grabber interface incorporates LVDS devices for the
serial communication signals (per Camera Link). The camera interface serial signals are
implemented using LVDS or RS-422 devices, depending on CLT-302 version.
The CLT-302 detects the presence of an active Camera Link camera. When an active (i.e.
powered) camera is detected, the front-panel “link” indicator illuminates. The front panel
also includes a power indicator to show that the CLT-302 is powered.
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