Xilinx ChipScope Pro Bedienungsanleitung

User Guide []

UG029 (v14.3) October 16, 2012 []

ChipScope Pro

Software and Cores

User Guide

UG029 (v14.3) October 16, 2012

This document applies to the following software versions: ISE Design Suite 14.3 through 14.6This document applies to the following software versions: ISE Design Suite 14.3 through 14.6This document applies to the following software versions: ISE Design Suite 14.3 through 14.6This document applies to the following software versions: ISE Design Suite 14.3 through 14.6

ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012

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Revision History

The following table shows the revision history for this document.

Date Version Revision

4/24/2012 14.1 Updated for 14.1 release. Updates for KC705 board.

7/25/2012 14.2 Updated for 14.2 release. Various corrections plus support for RX Margin Analysis panel.

10/16/2012 14.3 Updated for 14.3 release. Support for IBERT 7 Series GTP and GTZ devices.

ChipScope Pro Software and Cores User Guide www.xilinx.com 3

UG029 (v14.3) October 16, 2012

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: Introduction

ChipScope Pro Tools Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

ChipScope Pro Tools Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Using ChipScope Pro Cores in the PlanAhead Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ChipScope Pro Cores Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Software Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Chapter 2: Using the Core Generator Tools

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Using the Xilinx CORE Generator Tool with ChipScope Pro Cores . . . . . . . . . . . 31

Chapter 3: Using the ChipScope Pro Core Inserter

ChipScope Pro Core Inserter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Using the ChipScope Pro Core Inserter with the PlanAhead Tool . . . . . . . . . . . . 33

Using the ChipScope Pro Core Inserter with ISE Project Navigator . . . . . . . . . . . 33

Using the ChipScope Pro Core Inserter with Command Line Implementation 35

ChipScope Pro Core Inserter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Chapter 4: Using the ChipScope Pro Analyzer

ChipScope Pro Analyzer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

ChipScope Pro Analyzer Server Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

ChipScope Pro Analyzer Client Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

ChipScope Pro Analyzer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

ChipScope Pro ILA Waveform Toolbar Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

ChipScope Pro Analyzer Command Line Options. . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Chapter 5: ChipScope Engine Tcl Interface

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

CSE/Tcl Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

CseJtag Tcl Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CseFpga Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

CseCore Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

CseVIO Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

CSE/Tcl Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Appendix A: ChipScope Pro Tools Troubleshooting Guide

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

ChipScope Pro Tools Installation Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . 208

Xilinx JTAG Programming Cable Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . 209

ChipScope Pro Software and Cores User Guide www.xilinx.com 4

UG029 (v14.3) October 16, 2012

ChipScope Pro Analyzer Core Troubleshooting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Gathering Information for Xilinx Technical Support . . . . . . . . . . . . . . . . . . . . . . . . 223

Appendix B: References

ChipScope Pro Software and Cores User Guide www.xilinx.com 5

UG029 (v14.3) October 16, 2012

Chapter 1

Introduction

ChipScope Pro Tools Overview

As the density of FPGA devices increases, so does the impracticality of attaching test

equipment probes to these devices under test. The ChipScope™ Pro tools integrate key

logic analyzer and other test and measurement hardware components with the target

design inside the supported Xilinx® FPGA devices listed in the ISE® Design Suite Product

Table [See Reference 16, p. 225]. The tools communicate with these components and

provide the designer with a robust logic analyzer solution.

The ChipScope Pro Serial I/O Toolkit provides features and capabilities specific to the

exploration and debug of designs that use the high-speed serial transceiver I/O capability

of FPGAs. The IBERT (internal bit error ratio tester) core and related software provides

access to the high-speed serial transceivers and perform bit error ratio analysis on channels

composed of these transceivers. In this document, the transceivers are called MGTs (multi-

gigabit transceivers). The IBERT core supports the high-speed serial transceivers found in

the Xilinx Virtex®-7, Kintex™-7, Virtex-6, Spartan®-6, and Virtex-5 FPGA devices listed in

the ISE Design Suite Product Table [See Reference 16, p. 225].

ChipScope Pro Tools Description

The following table gives a brief description of the various ChipScope Pro tools and cores.

Table 1-1: ChipScope Pro Tools Description

Tool Description

Xilinx CORE

Generator™ tool

Provides core generation capability for the ICON (integrated

controller), ILA (integrated logic analyzer), VIO, (virtual

input/output), and ATC2 (Agilent trace core) cores targeting all

supported FPGA device families. Also provides core generation

capability for the IBERT v2.0 core targeting the Virtex-7, Kintex-7,

Virtex-6, Spartan-6, and Virtex-5 FPGA families. The Xilinx CORE

Generator tool is part of the Xilinx ISE Design Suite tool installation.

IBERT Core

Generator

Provides full design generation capability for the IBERT v1.0 core

targeting the Virtex-5 devices. You select the MGTs and parameters

governing the design, and the CORE Generator tool uses the ISE

design suite to produce a configuration file.

Core Inserter Automatically inserts the ICON, ILA, and ATC2 cores into your

synthesized design.

6www.xilinx.com ChipScope Pro Software and Cores User Guide

UG029 (v14.3) October 16, 2012

Chapter 1: Introduction

This figure shows a block diagram of a system containing debug cores added using the

ChipScope Pro tools. You can place the ICON, ILA, VIO, and ATC2 cores (collectively

called the ChipScope Pro cores) into your design by generating the cores with the CORE

Generator tool and instantiating them into the HDL source code. You can also insert the

ICON, ILA, and ATC2 cores directly into the synthesized design netlist using the

ChipScope Pro Core Inserter or PlanAhead tools. You then place and route your design

using the ISE implementation tools. Next, download the bitstream into the device under

test and analyze the design with the ChipScope Pro Analyzer tool.

PlanAhead™ Design

Analysis Tool

Automatically inserts the ICON and ILA cores into the design

netlist. For more information on this feature, go to PlanAhead

Design Analysis Tool [See Reference 17, p. 225].

ChipScope Pro

Analyzer Tool

Provides in-system device configuration, as well as trigger setup,

trace display, control, and status for the ICON, ILA,VIO, and IBERT

cores.

ChipScope Engine Tcl

(CSE/Tcl) Scripting

Interface

The scriptable CSE/Tcl command interface makes it possible to

interact with devices in a JTAG (Joint Test Action Group, IEEE

standard) chain from a Tcl shell

(1).

Notes:

1. Tcl stands for Tool Command Language. The CSE/Tcl interface requires the Tcl shell program (called

xtclsh) that is included in the ChipScope Pro and ISE tool installations or in the ActiveTcl 8.4 shell

available from ActiveState [See Reference 24, p. 226].

X-Ref Target - Figure 1-1

Figure 1-1: ChipScope Pro System Block Diagram

Table 1-1: ChipScope Pro Tools Description (Cont’d)

Tool Description

Board-Under-Test

Host Computer with

ChipScope Pro Software

JTAG

Connections

cs_pro_sys_blk_diag

ChipScope

Pro

Target Device Under Test

User

Function

User

Function

User

Function

ILA Pro

ICON Pro

ILA Pro

Parallel

Cable

ChipScope Pro Software and Cores User Guide www.xilinx.com 7

UG029 (v14.3) October 16, 2012

ChipScope Pro Tools Description

ChipScope Pro Analyzer tool supports the following download cables for communication

between your computer and the devices in the JTAG boundary scan chain:

•Platform Cable USB

•Parallel Cable IV

•Digilent USB-to-JTAG cables

•ByteTools Catapult EJ-1 Ethernet-to-JTAG cable

The ChipScope Pro Analyzer tool and cores contain many features that you can use to

verify your logic (Table 1-2). User-selectable data channels range from 1 to 4,096 and the

sample buffer sizes range from 256 to 131,072 samples. You can change the triggers in real

time without affecting your logic. ChipScope Pro Analyzer tool leads you through the

process of modifying triggers and analyzing the captured data.

Table 1-2: ChipScope Pro Logic Debug Features and Benefits

Feature Benefit

1 to 4,096 user-selectable data channels Accurately captures wide data bus

functionality.

User-selectable sample buffers ranging in

size from 256 to 131,072 samples

Large sample size increases accuracy and

probability of capturing infrequent events.

Up to 16 separate trigger ports, each with a

user-selectable width of 1 to 256 channels (for

a total of up to 4096 trigger channels)

Multiple separate trigger ports increase the

flexibility of event detection and reduce the

need for sample storage.

Up to 16 separate match units per trigger

port (up to 16 total match units) for a total of

16 different comparisons per trigger

condition

Multiple match units per trigger ports

increase the flexibility of event detection

while conserving valuable resources.

All data and trigger operations are

synchronous to your clock at rates up to 500

MHz

Capable of high-speed trigger event

detection and data capture.

Trigger conditions implement either a

boolean equation or a trigger sequence of up

to 16 match functions

Can combine up to 16 trigger port match

functions using a boolean equation or a

16-level trigger sequencer.

Data storage qualification condition

implements a boolean equation of up to 16

match functions

Can combine up to 16 trigger port match

functions using a boolean equation to

determine which data samples are captured

and stored in on-chip memory.

Trigger and storage qualification conditions

are in-system changeable without affecting

the user logic

No need to single step or stop a design for

logic analysis.

Easy-to-use graphical interface Guides you through selecting the correct

options.

8www.xilinx.com ChipScope Pro Software and Cores User Guide

UG029 (v14.3) October 16, 2012

Chapter 1: Introduction

Design Flow

The tools design flow (Figure 1-2) merges easily with any standard FPGA design flow that

uses a standard HDL synthesis tool and the ISE implementation tools.

Using ChipScope Pro Cores in the PlanAhead Tool

You can add the ChipScope Pro cores to your design using the PlanAhead tool using one of

two methods:

•HDL instantiation

•Netlist insertion

Up to 15 independent ILA, VIO, or ATC2

cores per device

Can segment logic and test smaller sections

of a large design for greater accuracy.

Multiple trigger settings

Records duration and number of events

along with matches and ranges for greater

accuracy and flexibility.

Downloadable from the Xilinx Web site Tools are easily accessible from the

ChipScope Suite [See Reference 18, p. 225].

Table 1-2: ChipScope Pro Logic Debug Features and Benefits (Cont’d)

Feature Benefit

X-Ref Target - Figure 1-2

Figure 1-2: ChipScope Pro Tools Design Flow

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ChipScope Pro Software and Cores User Guide www.xilinx.com 9

UG029 (v14.3) October 16, 2012

Using ChipScope Pro Cores in the PlanAhead Tool

The HDL instantiation method is a two-step process that involves:

1. Using the IP Catalog in the PlanAhead tool to select, customize, and generate the

desired ChipScope Pro debug core.

2. Using the HDL Editor in the PlanAhead tool to manually instantiate the IP component

instance into your HDL source.

The HDL instantiation method is a good approach for users who want full control of all IP

core parameters and connections to signals in their HDL design. The downside of HDL

instantiation is that it requires the user to modify their source code. It can also be difficult

to debug a design that is made up of multiple levels of hierarchy because signals of interest

need to be brought to the debug core instance.

The Netlist insertion method is also a two step process that involves:

1. Selecting signals or nets in your design that are interesting for debugging purposes.

2. Specifying how you want these signals to be attached to debug IP cores.

The PlanAhead tool takes care of generating the debug IP core, inserting it into the design

netlist, and connecting it to the nets of interest. A potential drawback to the netlist insertion

method is that the HDL signals you want to debug could be optimized away or obfuscated

during synthesis process. Most signals that are interesting for debug (such as outputs of

registers, block RAM, etc.) are not adversely affected by the synthesis process. However,

one way to ensure signals are preserved for debugging later in the flow is to attach the

MARK_DEBUG attribute or property to signals in your design source (either your HDL or

constraints files). For details about the MARK_DEBUG attribute and other constraints,

refer to the ISE Constraints Guide [See Reference 14, p. 225].

The MARK_DEBUG property has the following benefits:

•Allows targeted debugging of signals in your design source without the overhead of

HDL instantiation method

•Ensures signals to be debugged are preserved in the synthesized netlist

•Is compatible with Xilinx Synthesis Technology (XST) and third party FPGA synthesis

tools such as Synopsys, Synplify Pro, and Mentor Graphics Precision.

For more details on the ChipScope debugging capabilities of the PlanAhead tool, refer to

the PlanAhead User Guide [See Reference 17, p. 225].

Using ChipScope Pro Cores in Embedded Processor and DSP Tool Flows

The cores (ICON, ILA, IBA, VIO, and ATC2) can also be used in the EDK and System

Generator for DSP tool flows for embedded processor and DSP designs, respectively. For

information on how to use the ChipScope Pro cores, see the EDK Platform Studio [See

Reference 15, p. 225] and System Generator for DSP [See Reference 19, p. 225]

documentation.

10 www.xilinx.com ChipScope Pro Software and Cores User Guide

UG029 (v14.3) October 16, 2012

Chapter 1: Introduction

ChipScope Pro Cores Description

ICON Core

All the cores use the JTAG boundary scan port to communicate to the host computer via a

JTAG download cable. The ICON core provides a communications path between the JTAG

boundary scan port of the target FPGA and up to 15 ILA, VIO, and/or ATC2 cores (as

shown in Figure 1-1, page 6).

For devices of the Spartan-3, Spartan-3E, Spartan-3A, and Spartan-3A DSP families, the

ICON core uses either the USER1 or USER2 JTAG boundary scan instructions for

communication via the BSCAN primitive. The unused USER1 or USER2 scan chain of the

BSCAN primitive can also be exported for use in your application, if needed.

For all other supported devices, the ICON core uses any one of the USER1, USER2, USER3

or USER4 scan chains available via the BSCAN primitives. It is not necessary to export

unused USER scan chains because each BSCAN primitive implements a single scan chain.

ILA Core

The ILA core is a customizable logic analyzer core that can be used to monitor any internal

signal of your design. Because the ILA core is synchronous to the design being monitored,

all design clock constraints that are applied to your design are also applied to the

components inside the ILA core. The ILA core consists of three major components:

•Trigger input and output logic:

−Trigger input logic detects elaborate trigger events.

−Trigger output logic triggers external test equipment and other logic.

•Data capture logic:

−ILA cores capture and store trace data information using on-chip block RAM

resources.

•Control and status logic:

−Manages the operation of the ILA core.

ILA Trigger Input Logic

The triggering capabilities of the ILA core include many features that are necessary for

detecting elaborate trigger events. These features are described in Table 1-3.

Table 1-3: Trigger Features of the ILA Core

Feature Description

Wide Trigger Ports Each trigger port can be 1 to 256 bits wide.

Multiple Trigger Ports

Each ILA core can have up to 16 trigger ports. The ability to

support multiple trigger ports is necessary in complex systems

where different types of signals or buses must be monitored

using separate match units.

Multiple Match Units per

Trigger Port

Each trigger port can be connected to up to 16 match units. This

feature enables multiple comparisons to be performed on the

trigger port signals.

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