Xilinx Pico Blaze Frequency Generator Bedienungsanleitung

Frequency Generator

for

Spartan-3E Starter Kit

Ken Chapman

Xilinx Ltd

July 2006

Rev.1

With special thanks to

Peter Alfke and Alireza Kaviani.

Frequency Generator for the Spartan-3E Starter Kit 2

Limited Warranty and Disclaimer. These designs are provided to you “as is”. Xilinx and its licensors make and you receive no

warranties or conditions, express, implied, statutory or otherwise, and Xilinx specifically disclaims any implied warranties of

merchantability, non-infringement, or fitness for a particular purpose. Xilinx does not warrant that the functions contained in these

designs will meet your requirements, or that the operation of these designs will be uninterrupted or error free, or that defects in

the Designs will be corrected. Furthermore, Xilinx does not warrant or make any representations regarding use or the results of

the use of the designs in terms of correctness, accuracy, reliability, or otherwise.

Limitation of Liability. In no event will Xilinx or its licensors be liable for any loss of data, lost profits, cost or procurement of

substitute goods or services, or for any special, incidental, consequential, or indirect damages arising from the use or operation

of the designs or accompanying documentation, however caused and on any theory of liability. This limitation will apply even if

Xilinx has been advised of the possibility of such damage. This limitation shall apply not-withstanding the failure of the essential

purpose of any limited remedies herein.

This design module is not supported by general Xilinx Technical support as an official Xilinx Product.

Please refer any issues initially to the provider of the module.

Any problems or items felt of value in the continued improvement of KCPSM3 or this reference design would be gratefully

received by the author.

Ken Chapman

Senior Staff Engineer – Spartan Applications Specialist

email: chapman@xilinx.com

Limitations

The author would also be pleased to hear from anyone using KCPSM3 with information about your application and PicoBlaze

has been useful.

Frequency Generator for the Spartan-3E Starter Kit 3

Design Overview

This design converts the Spartan-3E Starter Kit into a reasonably accurate frequency generator covering the nominal range 1Hz to 100MHz. The design

allows you to attempt generation of higher frequencies to allow you to experiment with the maximum performance of the Spartan device on your board. The

rotary control is used to edit the frequency displayed on the upper line of the LCD display and the corresponding frequency will then be output on the SMA

connector (J17) as well as the stake pin J4-IO12. Internally to the device the frequency range is twice that provided externally (nominally up to 200MHz).

As well as providing the basic instructions to use the frequency counter, this document provides details of the Direct Digital Synthesis (DDS) techniques used

in the design such that the can be transplanted into your own designs. PicoBlaze is used to provide the human interface and perform so high precision

calculations which are passed to a simple but high performance (200MHz) frequency synthesizer formed from pure hardware and two Digital Clock Managers

(DCMs). The lower line of the LCD display provides the information passed from PicoBlaze to the hardware which means that you can use this design with

your board to determine the exact values required to implement a fixed frequency synthesizer without requiring PicoBlaze, the knob and LCD display. On this

board the technique provides a convenient alternative to fitting a special oscillator in the IC16 socket and it may proves a cost effective solution for many real

product applications too.

As well as the source design files, a compiled

configuration bit file is provided which you can

immediately download into the Spartan

XC3S500E device on your board. To make this

task really easy the first time, unzip all the files

provided into a directory and then….

double click on

‘install_frequency_generator.bat’.

Assuming you have the Xilinx software installed,

your board connected with the USB cable and

the board powered (don’t forget the switch),

then this should open a DOS window and run

iMPACT in batch mode to configure the

Spartan-3E with the design.

Load it now – it only takes 30 seconds!

It is recommended that you try this to become

familiar with what the design does (operating

instructions on the next page).

Output Frequency provided on

SMA socket

Frequency display

(top line)

50MHz Reference

Crystal Oscillator

LEDs indicate

frequency

editing mode

Spartan XC3S500E

Press and rotate knob

to set frequency

DDS control values

(bottom line)

J4-IO9

Phase

Accumulator

Test Point

J4-IO12

Copy of Output

Frequency

Frequency Generator for the Spartan-3E Starter Kit 4

Operating Instructions

Output frequency provided on SMA connector (J17)

and J4_IO12.

In this mode rotating the knob to the left or right will cause the display

cursor to move in the corresponding direction on the upper line of the

display. Use this mode to position the cursor below the digit you wish to

adjust and then press and release the knob to change mode. The

cursor automatically skips past the decimal point and space separator

and hits ‘end stops’ if you over rotate the knob.

= Edit cursor position mode

LEDs indicate the editing mode.

The cursor is the small

black line under the digit

in the top line.

= Edit digit value mode

Press and release knob to toggle between frequency editing modes

Edit cursor position mode

In this mode rotating the knob to the left or right will decrement or increment the value of the digit located at the cursor position. The controller will

automatically borrow from, or carry to, the more significant digits to the left of the digit being adjusted. Every adjustment will immediately result in the

corresponding frequency change at the output which is also reflected by the changes to the computed DDS control values on the lower line of the display.

Press and release the knob to revert to cursor position mode when complete.

Edit digit value mode

The cursor can be moved into the

10MHz and 100MHz digit positions but

these positions are blanked when zero.

Frequency Generator for the Spartan-3E Starter Kit 5

PicoBlaze Design Size

The images and statistics on this page show that the design occupies just 172 slices, 1 BRAM and 2 DCMs. This is only 3.7% of the slices available in an

XC3S500E device. More significantly, this slice count can be reduced to less than 32 when implementing a fixed frequency version.

Number of occupied Slices: 172 out of 4,656 3%

Number of Block RAMs: 1 out of 20 5%

DCMs: 2 out of 4 50%

Total equivalent gate count for design: 91,537

PicoBlaze makes extensive use of the distributed memory features of the

Spartan-3E device leading to very high design efficiency. If this design

was replicated to fill the XC3S500E device, it would represent the

equivalent of over 1.5 million gates. Not bad for a device even marketing

claims to be 500 thousand gates 

MAP report

FPGA Editor view Floorplanner view

XC3S500E

Frequency Generator for the Spartan-3E Starter Kit 6

Design Files

The source files provided for the reference design are…..

frequency_generator.vhd

Top level file and main description of hardware.

Contains I/O required to disable StrataFLASH memory device on the board which may

otherwise interfere with the LCD display.

PicoBlaze program source assembler code

kcpsm3.vhd PicoBlaze processor for Spartan-3E devices.

fg_ctrl.vhd

frequency_generator.ucf I/O constraints file for Spartan-3E Starter Kit

Timing specifications for 50MHz PicoBlaze controller 200MHz DDS circuits.

Location constraint for DCM used for Jitter reduction.

fg_ctrl.psm

Assembled program for PicoBlaze (stored in a Block memory)

Note: The file shown in green is not included with the reference design as it is provided with PicoBlaze download. Please visit the PicoBlaze Web site

for your free copy of PicoBlaze, assembler, JTAG_loader and documentation.

www.xilinx.com/picoblaze

Hint – The JTAG_Loader utility supplied with PicoBlaze has been included in this design. This enables the new programs to be written for PicoBlaze

using the configuration file provided.

This design contains an otherwise undocumented and unspecified mode of

operation for a DCM. Before this design can be processed a special BITGEN option

needs to be set. Please read the notes provided on page 13 as well as those

contained in ‘frequency_generator.vhd'for details of this special requirement.

Hint – You do not need PicoBlaze if you use this design as the basis for implementing a fixed frequency module. However, I’m sure you will want

PicoBlaze for other parts of your design now that you have seen what it is capable of doing .

Frequency Generator for the Spartan-3E Starter Kit 7

Direct Digital Synthesis (DDS) Circuit Diagram

32-Bit

Counter

CLKIN

50MHz

clk

BUFG

phase_acc_dcm

DCM

The first DCM is used to multiply the 50MHz clock by a

factor or 4 and form a 200MHz clock. This gives the

phase accumulator a timing resolution of 5ns.

CLKFX

CLKFX_MULTIPLY=4

CLKFX_DIVIDE=1

clk_200mhz dds_clk

BUFG

200MHz

dds_control_word[31:0]

phase_accumulator[31:0]

phase_acc

The phase accumulator is a standard 32-bit accumulator operating at 200MHz. This accumulator is

really the heart of the DDS as it is the most significant bit of the accumulator that produces the

variable frequency being synthesized. The remaining circuits only multiply, divide and clean this

synthesized frequency or are involved with selecting and generating the DDS control words.

The frequency of the most significant bit is defined by the 32-bit value applied to the input of the

accumulator. This value is shown as ‘N’ on the LCD display and is applied to the bus

‘dds_control_word’ in the circuit. The value of N is computed in such a way that the synthesized

frequency is nominally in the range 6.25MHz to 12.5MHz so that it is always a suitable

input to the second DCM.

[31]

N × 200MHz

FMSB =232

In this example N=204010946 decimal so the output from the phase accumulator

is ~9.5MHz (a period of approximately 105ns). That means that the accumulator

synthesizes one output cycle for approximately 21 cycles of the 200MHz clock

from which the accumulator runs.

CLKIN

BUFG

frequency_aligned_dcm

DCM

CLKFX

CLKFX_MULTIPLY=256

CLKFX_DIVIDE=16

dcm_clean_clk

synth_clk

The second DCM is used in a ‘frequency aligned mode’. At the time of writing this

reference design, this mode is not an officially documented or supported feature.

However, it is hoped that this reference design will enable you to see this mode in action

and evaluate it for yourself. In this mode, the DCM not only multiplies the input clock, but

also has the effect of reducing cycle to cycle jitter. This is because the normal phase

alignment mode of the DCM has been disabled and the DCM is tracking the average of

the input frequency instead.

×4

×16

10 or 11

cycles 10 or 11

cycles

In the example, the input to the DCM will have 5ns

of cycle to cycle jitter as the square wave is formed

from 21 cycles of 200MHz. The DCM will generate

~153MHz square wave with <300ps of jitter.

frequency_divider[31:0]

freq_scaling 0

io9

io12

sma_out

dds_scaling_word

A simple binary counter is used

to divide the low jitter clock by

powers of 2 and a multiplexer

selects the appropriate course

division factor.

N × 200MHz × 16

FO=2(D+1) × 232

In the example, D=4 so the

~153MHz from the DCM is

divided by 2(4+1)=32

FO=4.7499999869MHz

Frequency Generator for the Spartan-3E Starter Kit 8

PicoBlaze Circuit Diagram

strataflash_oe

strataflash_ce

strataflash_we

Vcc

* StrataFLASH memory

must be disabled to

prevent interference with

the LCD display.

interrupt_control

‘JTAG_loader’ allows rapid

PicoBlaze code development.

port_id

kcpsm3 processor

instruction

write_strobe

clk

out_port

read_strobe

address

reset

interrupt_ackinterrupt

in_port

instruction

address

fg_ctrl

program_rom

instruction

address

clk

port_id

write_strobe

out_port

read_strobe

interrupt_ack

interrupt

in_port

JTAG

proc_reset

clk

kcpsm3_reset

input_ports

led(6)

led(5)

led(4)

led(3)

led(2)

led(1)

led(0)

led(7)

output_ports

rotary_a

rotary_press

rotary_b

lcd_rs

lcd_e

lcd_rw

lcd(7)

lcd(6)

lcd(5)

lcd(4)

lcd(7)

lcd(6)

lcd(5)

lcd(4)

bidirectional

LCD data

rotary_press_in

See reference

design called

‘Rotary Encoder

Interface for

Spartan-3E Starter

Kit’ for details of

this section.

rotary_event

rotary_left

rotary_filter & direction

clk

50MHz clock to all items on this page

dds_scaling_word

dds_control_word

[7:0]

[15:8]

[23:16]

[31:24]

[4:0]

PicoBlaze provides the user interface and performs

the calculations required to generate the 32-bit DDS

control word ‘N’ and 5-bit DDS scaling word ‘D’.

Hint – The ‘fg_ctrl.psm’ file contains significant

comments to explain the operations and calculations

that the PicoBlaze program is performing to

generate ‘N’ and ‘D’ from the BCD value displayed

on the LCD.

Frequency Generator for the Spartan-3E Starter Kit 9

Phase Accumulator Waveforms

The following waveforms were obtained by monitoring the output of the phase accumulator presented on stake pin ‘J4-IO9’. In each case the digital storage

oscilloscope was set to infinite persistence in order capture any fluctuations over time and therefore observe the ‘envelope’ of operation.

This waveform shows a pretty clean 12.5MHz square wave. The reason the waveform is so

clean is because 12.5MHz is a perfect division of the 200MHz clock used by the phase

accumulator and it means that the synthesized waveform is always formed of 16 clock periods

of the 200mHz clock with 8 Low and 8 High.

Note that to force this frequency at the phase accumulator I actually dialled in a frequency of

100MHz on to the LCD display such that N=10000000 hex.

12.5MHz

8 cycles

@ 200MHz

8 cycles

@ 200MHz

This waveform shows what happens when you try to synthesize a 12.4125MHz clock using the

phase accumulator. There is clearly 5ns of cycle to cycle jitter in this situation because each

output cycle really should be formed of ~16.113 periods of the 200MHz clock which is

impossible. Therefore what the phase accumulator is doing is to provide the correct average

frequency by making some cycles of 16 periods and then make approximately 1 in every 9

cycles have 17 periods; a mix of 12.5MHz and 11.767MHz waveforms.

Note that to force this frequency at the phase accumulator I actually dialled in a frequency of

99.3MHz on to the LCD display such that N=0FE353F7 hex

16 cycles

@ 200MHz

17 cycles

@ 200MHz

16 cycles

@ 200MHz

5ns of cycle to cycle jitter is often acceptable when synthesizing lower frequencies especially if the waveform is only used as a digital clock for control and

timing of slower events. However, for higher frequencies such jitter becomes acceptable (i.e. at 100MHz the cycle period is only 10ns).

Frequency Generator for the Spartan-3E Starter Kit 10

Phase Accumulator Spectrum

An alternative way to observe the quality of the waveforms synthesised by the phase accumulator is to look at the frequency spectrum. I was lucky enough

to have a 2048-point FFT feature on my oscilloscope which allows some simple observations to be made. Once again I have set the display to infinite

persistence in order capture the spectrum over a long period of time (>15 seconds). I suggest that you do not look for exact values, but compare the plots

which have been captured using the same scales in each case. On the left are plots that show the spectrum up to 50MHz and on the right the plots show

are zoomed in to show ±5MHz centred on 12.5MHz.

As we know the 12.5MHz signal is

nominally clean in terms of the synthesis

process and this is reflected by a distinct

12.5MHz component which is >45dB above

the noise floor. The zoomed plot shows how

the fundamental covers only a narrow

bandwidth keeping in mind that the

resolution of the FFT is only ~50KHz.

Note the third harmonic of a square wave is

also very distinct at 37.5MHz and is even

close to being the theoretical 9.54dB down

from the fundamental (1/3 amplitude).

12.5MHz

Fundamental

5MHz/division

10dB/division 1MHz/division

10dB/division

3rd

Harmonic 12.5MHz

Fundamental

12.4125MHz

Fundamental 12.4125MHz

Fundamental

When we move to the less than perfect

12.4125MHz waveform the effects of that

5ns of cycle jitter and jumping between

12.5MHz and 11.76MHz waveforms is

obviously having an impact on the

spectrum. Although the fundamental

frequency component is good, if a little

wider in bandwidth, there are significant

modulation effects leading to a family of

spectral components and raised noise floor.

Hint – 12.5MHz-11.76MHz = 0.74MHz

12.4125±0.74MHz

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