Xilinx MIcroBlaze Development Spartan-3E 1600E Kit Bedienungsanleitung

MicroBlaze Development

Kit Spartan-3E 1600E

Edition User Guide

UG257 (v1.1) December 5, 2007

MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide 9

UG257 (v1.1) December 5, 2007 www.xilinx.com

Chapter 1

Introduction and Overview

Thank you for purchasing the Xilinx MicroBlaze™ Development Kit Spartan™-3E 1600E

Edition. You will find it useful in developing your Spartan-3E FPGA application.

Choose the Starter Kit Board for Your Needs

Depending on specific requirements, choose the Xilinx development board that best suits

your needs.

Spartan-3E FPGA Features and Embedded Processing Functions

The MicroBlaze Development Kit board highlights the unique features of the Spartan-3E

FPGA family and provides a convenient development board for embedded processing

applications. The board highlights these features:

•Spartan-3E specific features

♦Parallel NOR Flash configuration

♦MultiBoot FPGA configuration from Parallel NOR Flash PROM

♦SPI serial Flash configuration

•Embedded development

♦MicroBlaze 32-bit embedded RISC processor

♦PicoBlaze™ 8-bit embedded controller

♦DDR memory interfaces

♦10-100 Ethernet

♦UART

Learning Xilinx FPGA, CPLD, and ISE Development Software Basics

The MicroBlaze Development Kit board is more advanced and complex compared to other

Spartan development boards.

Advanced Spartan-3 Generation Development Boards

The MicroBlaze Development Kit board demonstrates the basic capabilities of the

MicroBlaze embedded processor and the Xilinx Embedded Development Kit (EDK). For

more advanced development on a board with additional peripherals and FPGA logic,

consider the V4 FX12 Board:

10 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide

www.xilinx.com UG257 (v1.1) December 5, 2007

Chapter 1: Introduction and Overview R

•http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DO-

ML403-EDK-ISE

Also consider the capable boards offered by Xilinx partners:

•http://www.xilinx.com/products/devboards/index.htm

Key Components and Features

The key features of the MicroBlaze Development Kit board are:

•Xilinx XC3S1600E Spartan-3E FPGA

♦Up to 250

♦user-I/O pins

♦320-pin FBGA package

♦Over 33,000 logic cells

•Two Xilinx 4 Mbit Platform Flash configuration PROM

•Xilinx 64-macrocell XC2C64A CoolRunner CPLD

•64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz

•16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)

♦FPGA configuration storage

♦MicroBlaze code storage/shadowing

•16 Mbits of SPI serial Flash (STMicro)

♦FPGA configuration storage

♦MicroBlaze code shadowing

•2 x 16 LCD display screen

•PS/2 mouse or keyboard port

•VGA display port

•10/100 Ethernet PHY (requires Ethernet MAC in FPGA)

•Two 9-pin RS-232 ports (DTE- and DCE-style)

•On-board USB-based FPGA/CPLD download/debug interface

•50 MHz and 66 MHz clock oscillators

•SHA-1 1-wire serial EEPROM for bitstream copy protection

•Hirose FX2 expansion connector with 40-user I/O

•Three Digilent 6-pin expansion connectors

•Four-output, SPI-based Digital-to-Analog Converter (DAC)

•Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain

pre-amplifier

•ChipScope™ SoftTouch debugging port

•Rotary-encoder with push-button shaft

•Eight discrete LEDs

•Four slide switches

•Four push-button switches

•SMA clock input

MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide 11

UG257 (v1.1) December 5, 2007 www.xilinx.com

Design Trade-Offs

•8-pin DIP socket for auxiliary clock oscillator

Design Trade-Offs

A few system-level design trade-offs were required in order to provide the MicroBlaze

Development Kit board with the most functionality.

Configuration Methods Galore!

A typical FPGA application uses a single non-volatile memory to store configuration

images. To demonstrate new Spartan-3E capabilities, the MicroBlaze Development Kit

board has three different configuration memory sources that all need to function well

together. The extra configuration functions make the starter kit board more complex than

typical Spartan-3E applications.

The starter kit board also includes an on-board USB-based JTAG programming interface.

The on-chip circuitry simplifies the device programming experience. In typical

applications, the JTAG programming hardware resides off-board or in a separate

programming module, such as the Xilinx Platform USB cable. This USB port is for

programming only and can not be used as an independent USB interface.

Voltages for all Applications

The MicroBlaze Development Kit board showcases a triple-output regulator developed by

Texas Instruments, the TPS75003 specifically to power Spartan-3 and Spartan-3E FPGAs.

This regulator is sufficient for most stand-alone FPGA applications. However, the starter

kit board includes DDR SDRAM, which requires its own high-current supply. Similarly,

the USB-based JTAG download solution requires a separate 1.8V supply.

Related Resources

•Xilinx MicroBlaze Soft Processor

http://www.xilinx.com/microblaze

•Xilinx PicoBlaze Soft Processor

http://www.xilinx.com/picoblaze

•Xilinx Embedded Development Kit

http://www.xilinx.com/ise/embedded_design_prod/platform_studio.htm

•Xilinx software tutorials

http://www.xilinx.com/support/techsup/tutorials/

•Texas Instruments TPS75003

http://focus.ti.com/docs/prod/folders/print/tps75003.html

MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide 13

UG257 (v1.1) December 5, 2007 www.xilinx.com

Chapter 2

Switches, Buttons, and Knob

Slide Switches

Locations and Labels

The MicroBlaze Development Kit board has four slide switches, as shown in Figure 2-1.

The slide switches are located in the lower right corner of the board and are labeled SW3

through SW0. Switch SW3 is the left-most switch, and SW0 is the right-most switch.

Operation

When in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic High.

When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic

Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active

debouncing circuitry, although such circuitry could easily be added to the FPGA design

programmed on the board.

UCF Location Constraints

Figure 2-2 provides the UCF constraints for the four slide switches, including the I/O pin

assignment and the I/O standard used. The PULLUP resistor is not required, but it defines

the input value when the switch is in the middle of a transition.

Figure 2-1: Four Slide Switches

Spartan-3E

Development Board

HIGH

LOW

UG257_02_01_061306

SW0

SW3

14 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide

www.xilinx.com UG257 (v1.1) December 5, 2007

Chapter 2: Switches, Buttons, and Knob R

Push-Button Switches

Locations and Labels

The MicroBlaze Development Kit board has four momentary-contact push-button

switches, shown in Figure 2-3. The push buttons are located in the lower left corner of the

board and are labeled BTN_NORTH, BTN_EAST, BTN_SOUTH, and BTN_WEST. The

FPGA pins that connect to the push buttons appear in parentheses in Figure 2-3 and the

associated UCF appears in Figure 2-5.

Operation

Pressing a push button connects the associated FPGA pin to 3.3V, as shown in Figure 2-4.

Use an internal pull-down resistor within the FPGA pin to generate a logic Low when the

button is not pressed. Figure 2-5 shows how to specify a pull-down resistor within the

UCF. There is no active debouncing circuitry on the push button.

Figure 2-2: UCF Constraints for Slide Switches

NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;

NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;

NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;

NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

UG257_02_060206

Figure 2-3: Four Push-Button Switches Surround Rotary Push-Button Switch

UG257_02_03_061306

Spartan-3E

Development Board

Rotary Push Button Switch

ROT_A:(K18) requiresan internal pull-up

ROT_B:(G18) requiresan internal pull-up

ROT_Center:(V16) requiresan internal pull-down

BTN_NORTH (V4)

BTN_WEST (D18)

BTN_SOUTH (K17)

BTN_EAST (H13)

Notes:

1. All BTN_* push-button inputsrequire an internal pull-down resistor.

2. BTN_SOUTH isalso used as asoft reset in some FPGA applications

MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide 15

UG257 (v1.1) December 5, 2007 www.xilinx.com

Rotary Push-Button Switch

In some applications, the BTN_SOUTH push-button switch is also a soft reset that

selectively resets functions within the FPGA.

UCF Location Constraints

Figure 2-5 provides the UCF constraints for the four push-button switches, including the

I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each

input.

Rotary Push-Button Switch

Locations and Labels

The rotary push-button switch is located in the center of the four individual push-button

switches, as shown in Figure 2-3. The switch produces three outputs. The two shaft

encoder outputs are ROT_A and ROT_B. The center push-button switch is ROT_CENTER.

Operation

The rotary push-button switch integrates two different functions. The switch shaft rotates

and outputs values whenever the shaft turns. The shaft can also be pressed, acting as a

push-button switch.

Push-Button Switch

Pressing the knob on the rotary/push-button switch connects the associated FPGA pin to

3.3V, as shown in Figure 2-6. Use an internal pull-down resistor within the FPGA pin to

generate a logic Low. Figure 2-9 shows how to specify a pull-down resistor within the UCF.

There is no active debouncing circuitry on the push button.

Figure 2-4: Push-Button Switches Require an Internal Pull-Down Resistor in FPGA

Input Pin

UG227_02_04_060206

BTN_* Signal

Push Button

3.3VFPGA I/O Pin

Figure 2-5: UCF Constraints for Push-Button Switches

NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;

NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;

NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;

NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;

UG257_02_05_060206

16 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide

www.xilinx.com UG257 (v1.1) December 5, 2007

Chapter 2: Switches, Buttons, and Knob R

Rotary Shaft Encoder

In principal, the rotary shaft encoder behaves much like a cam, connected to central shaft.

Rotating the shaft then operates two push-button switches, as shown in Figure 2-7.

Depending on which way the shaft is rotated, one of the switches opens before the other.

Likewise, as the rotation continues, one switch closes before the other. However, when the

shaft is stationary, also called the detent position, both switches are closed.

Closing a switch connects it to ground, generating a logic Low. When the switch is open, a

pull-up resistor within the FPGA pin pulls the signal to a logic High. The UCF constraints

in Figure 2-9 describe how to define the pull-up resistor.

The FPGA circuitry to decode the ‘A’ and ‘B’ inputs is simple, but must consider the

mechanical switching noise on the inputs, also called chatter. As shown in Figure 2-8, the

chatter can falsely indicate extra rotation events or even indicate rotations in the opposite

direction! See the Rotary Encoder Interface reference design in“Related Resources” for an

example.

Figure 2-6: Push-Button Switches Require Internal Pull-up Resistor in FPGA Input

UG257_02_06_060906

Rotary / Push Button

ROT_CENTER Signal

3.3VFPGA I/O Pin

Figure 2-7: Basic example of rotary shaft encoder circuitry

GND

Vcco

A=‘0’

B=‘1’

A pull-up resistor in each input pin

generates a‘1’for an open switch.

See the UCF file for details on

specifying the pull-up resistor.

FPGA

UG257_02_07_060206

Rotary Shaft

Encoder

MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide 17

UG257 (v1.1) December 5, 2007 www.xilinx.com

Discrete LEDs

UCF Location Constraints

Figure 2-9 provides the UCF constraints for the four push-button switches, including the

I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each

input.

Discrete LEDs

Locations and Labels

The MicroBlaze Development Kit board has eight individual surface-mount LEDs located

above the slide switches as shown in Figure 2-10. The LEDs are labeled LED7 through

LED0. LED7 is the left-most LED, LED0 the right-most LED.

Figure 2-8: Outputs from Rotary Shaft Encoder May Include Mechanical Chatter

Detent

UG257_02_08_060206

Rotating RIGHT

Switch closing chatter on ‘B’

injects false “clicks” to the LEFT

(’B’rising edge when ‘A’is Low)

Switch opening chatter on ‘A’

injects false “clicks” to the RIGHT

Rising edge on ‘A’

when ‘B’is Low indicates

RIGHT (clockwise) rotation

Figure 2-9: UCF Constraints for Rotary Push-Button Switch

NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;

NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;

NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;

UG257_03_060206

18 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide

www.xilinx.com UG257 (v1.1) December 5, 2007

Chapter 2: Switches, Buttons, and Knob R

Operation

Each LED has one side connected to ground and the other side connected to a pin on the

Spartan-3E device via a 390Ωcurrent limiting resistor. To light an individual LED, drive

the associated FPGA control signal High.

UCF Location Constraints

Figure 2-11 provides the UCF constraints for the four push-button switches, including the

I/O pin assignment, the I/O standard used, the output slew rate, and the output drive

current.

Related Resources

•Rotary Encoder Interface for Spartan-3E Starter Kit (Reference Design)

http://www.xilinx.com/s3estarter

http://www.xilinx.com/sp3e1600E

Figure 2-10: Eight Discrete LEDs

LED7

LED0

Spartan-3E

Development Board

UG257_02_10_061306

Figure 2-11: UCF Constraints for Eight Discrete LEDs

NET "LED<7>" LOC = "A8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<6>" LOC = "G9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<5>" LOC = "A7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<4>" LOC = "D13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<3>" LOC = "E6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<2>" LOC = "D6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<1>" LOC = "C3" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<0>" LOC = "D4” | IOSTANDARD = SSTL2_I ;

UG257_02_11_062106

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