Analog Devices ADuCM355 Kurzanleitung

4) 5V USB FROM 8-PIN JTAG CONNECTOR

MICRO USB CONNECTOR

J-TAG CONNECTOR

2) CONNECT 5V TO 2-PIN CONNECTOR

3) CONNECT 3.3V DIRECT TO DVDD OR AVDD

POWER OPTIONS:

USB TO UART

JLINK DEBUG

CONNECTOR

OPTIONAL PULL_UPS FOR SW LINES

OPTIONAL EXTERNAL 3V

SUPPLY CONNECTOR 1) VIA USB

OPTIONAL 5V CONNECTOR

1 2

<DESIGN_VIEW>

: n/a

Product(s): ADuCM355

HW TYPE : Customer Evaluation

1:1

02_045865

<PTD_ENGINEER>

ADP7158ACPZ-3.3-R7

560

SML-310MTT86

10UF

0.1UF

60OHM AT 100MEGHZ

0.1UF

1UF

BLM41A800SPB-1806

0.1UF

M20-9990245

2.2

60OHM AT 100MEGHZ2.2

FT232RQ

M20-9990245

0.1UF 0.1UF

25.195.0253.0

10UF

25.195.0253.0

0.1UF0.1UF

10UF

2520-6002-UB

0.1UF

10UF

0.1UF

100K

DNI

100K

TSW-101-07-G-D

0.1UF

BLM41A800SPB-1806

0.1UF

1UF

TSW-104-25-F-D-RA

10UF

47346-0001

AVDD

DVDD

JP36

DS1

R17

JP39

P14

R13

JP38

JP5 P3

C36

C35

JP41

JP40

JP37

JP42 JP43

JP44

JP34

JP32

JP46

JP45

JP35

R14

C57

P27

C38

C48

C49

C52

C53

C54

C55

C47

C41

JP6

C43

C44

C39

C40

C37

C42

C46

C45

5VUSB

USBD-

AVDD_PREFILTER

3V3VOUT

USBD+

USBD-

P0.10_SOUT

P0.11_SIN

3V3VOUT

DVDD_PREFILTER

AVDD_PREFILTER

DVDD

AVDD

P1.5_CS

DVDD

SWDIO

SWCLK

P0.10_SOUT

SWCLK

SWDIO

P0.11_SIN

/RESET

DVDD

5VUSB DVDD

P0.11_SINSWCLK

P0.10_SOUTSWDIO

5VUSB

5VUSB DVDD_PREFILTER

/RESET

USBD+

A C

21 21

21 87 65 43 21

PAD

1 19

2323

18 28

PAD

DGND

VCCVCCIO

CBUS4

CBUS3

CBUS2

CBUS1

CBUS0

RTS#

DTR#

TXD

OSCO

3V3OUT

NCEP AGNDGND

USBDP

USBDM

CTS#

DCD#

DSR#

RI#

RXD

OSCI

TEST

RESET#

AGND

DGND

AGND

DGND

AGND

DGND

VIN

VREG

REF

REF_SENSE

BYP

VOUT_SENSE

VOUT

DGND

GND

PINS

AGND

DGND

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR DRAWING NO.

SCALE

SIZE

REV

SHEET

APPROVED

DESCRIPTION

REVISIONS

OL G

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

ANV

OF ANALOG DEVICES.

SCHEMATIC

PTD ENGINEER

DESIGN VIEW

REV DATE

OPTIONAL UART PULL-UPS

OPTIONAL I2C PULL-UPS

OPTIONAL DIGITAL TEMP SENSOR

INPUT BUFFERS

ANALOG SIGNALS

EC SENSOR SHORTING FET

RESET BUTTON

WAKE-UP BUTTON

EC SENSOR CHANNEL 0

DIGITAL TEST PINS

0R RESEISTORS CLOSE TO DUT

EC SENSOR SHORTING FET

EXTERNAL CRYSTAL

EC SENSOR CHANNEL 1

BOOT MODE BUTTON

4-PIN DUAL SENSOR JMPRS

EXTERNAL RTIA

DECOUPLING CAPS

GPIO CONTROLLED LED

RCAL RESISTOR

OPTIONAL CONNECTOR TO A SENSOR

ADUCM355

2 2

<DESIGN_VIEW>

: n/a

Product(s): ADuCM355

HW TYPE : Customer Evaluation

1:1

02_045865

<PTD_ENGINEER>

31022-00-21-00-00-08-0

4.7UF

200

0.47UF

0.1UF

0.47UF

TSW-110-08-G-S

DNI

150K

DNI

560

LNJ926W8CRA

100K

32MEGHZ

ADT7420UCPZ-RL7

AD8671ARZ

TSW-120-07-S-S

B3S-1000

DNI

0.47UF

DNI

RED

DNI

RED

DNI

AD8671ARZ

RED

DNI DNI

RED

DNI

RED RED RED

DNI

RED

DNIDNI

RED

DNI

RED

DNI

RED

DNI

RED

DNI

31022-00-21-00-00-08-0

150K

0.1UF

CO-A4

DNI

B3S-1000

0.15UF 10K

220PF

0.1UF

7PF 7PF

TSW-101-07-G-D

0.47UF

4.7UF

B3S-1000

100K

DNI

0.1UF

.125

0.1UF

4.7UF

0.1UF

0.47UF

DNI

0.1UF

CO-A4

0.1UF

DNI

0.1UF

DNI

0.1UF

MMBFJ177

0.1UF

DNI

IPS1-109-01-L-D

100K

DNI

0.1UF

MMBFJ177

0.47UF

0.1UF

ADUCM355

C25

JP4

C_LPF1

C17

C21

RCAL

JP19

JP20

JP12

JP7

JP8

JP9

DS2 R10 JP33

TP11

TP13 TP14

TP12 A2

TP15 TP17

TP16

TP18

TP10

TP9TP7TP6

TP8

TP5

TP1

TP2

CTIA RTIA

R16

R15

JP28

JP27

JP26

JP25

JP24

JP23

JP22

JP21 JP10

TP3 JP14

JP13

JP18

JP17

JP16

JP11

JP15

TP4

C28 S1

C22

JP31

JP30

JP29

C23

P26

R11

C56

R12

C13

C_LPF0

C20

C19

C18

C34

C14

C32 C33

C30

C29

C26

C31C27

JP2

JP3

JP1

C10

C12

C11

C24

CH1

CH0

SE0

CE0

RE0

VBIAS0

RE1

SE1

VBIAS1

VZERO1

DVDD

VZERO0

AIN0

AIN3

AIN5

AIN6

CE1

CAP_POT0

CAP_POT1

XTALO

CE1

RE1

AIN6

AIN5

AIN3

AIN2

AIN1

AIN0

P2.4

AIN1

P0.10_SOUT

SCL_PULLEDUP

AIN2

AIN3

P0.5_SDA

P0.3_CS0

RE1RE0

AFEDIE_GPIO1

P0.11_SIN

P0.10_SOUT

P0.5_SDA

SE1

VBIAS1

VZERO1

DE0

AIN0

DE0

AIN3

VZERO0

VBIAS0

AVDD

DVDD

P0.1_MOSI0

RE1

DVDD

DE1

SE1

SDA_PULLEDUP

AFEDIE_GPIO0

P0.3_CS0

/RESET

P0.4_SCL

P2.4

XTALO

XTALI

AVDD

DVDD

P1.5_CS

P1.1

AIN2

DE1

SE0

DE0

P1.4_MISO1

P1.3_MOSI1

P1.2_SCLK1

P0.2_MISO0

P0.0_SCLK0

P0.1_MOSI0

P1.3_MOSI1

P0.10_SOUT

CAP_POT0

CE0

RE0

DE0

SE0

DE0

SE0

CE0

AIN1

AVDD

AIN6

AIN0

DE0 AIN0

SE1

DE1

RE0

AGND

AVDD

P1.0

DVDD

P1.1

RE0

AVDD

CAP_POT1

AVDD

CE1

DVDD

P1.4_MISO1

P0.4_SCL DVDDSCL_PULLEDUP

DVDD

P1.5_CS

P1.4_MISO1

P1.3_MOSI1

P1.2_SCLK1

P1.1

P0.2_MISO0

P0.0_SCLK0

P2.4

AFEDIE_GPIO1

DE1 AIN1

P0.5_SDA SDA_PULLEDUP

P0.11_SIN

P1.0

P0.11_SIN

P0.4_SCL

AIN5

RE1

AFEDIE_GPIO0

P1.0

SWDIO

SWCLK

XTALI

E11

1 2

A C

1 1

851

1 1

111

851

PAD

21 21

B10

J11

H11

G11

C10

J10

A11

D10

D11

E10

H10

G10

A10

B11

C11

F11

F10

DGND

AGND

DGND

AGND

WECE

AGND

OUT

V+

V-

OUT

V+

V-

AGND

WECE

GND

PAD

VDD

GND

INT

SDA

SCL

AGND

DGND

AGND

DGND

AGND

DGND

AGND

DGND

RESET_N

VDCDC_CAPOUT

VDCDC_CAP1P

VDCDC_CAP1N

DVDD_REG

DVDD

P0.4/I2C_SCL

BM/P2.4

P0.10/UART_SOUT

P0.11/UART_SIN

XTALO

VDCDC_CAP2N

GPIO1/PWM1/EXTCLK

P0.0/SPI0_CLK

P0.1/SPI0_MOSI

P0.2/SPI0_MISO

P0.3/SPIO_/CS0

P0.5/I2C_SDA

SWDIO

SWCLK

AGND_DD

XTALI

VCDC_CAP2P

GPIO0/PWM0/POR/HIBERNATE

AVDD_DD

DVDD_REG_AD

AVDD

AGND

DGND

P1.4/SPI1_MISO

P1.0/SYS_WAKE

DGND_AD

DVDD_AD

ADCVBIAS_CAP

P1.2/SPI1_CLK

VREF_2.5V

AVDD_REG

RC1_0

RC1_1

P1.3/SPI1_MOSI

P1.5/SPI1_/CS0

P1.1

RC0_1

RC0_0

CAP_POT1

VBIAS1

VBIAS0

CAP_POT0

CE1

VZERO1

AIN0

AIN1

AIN3/BUF_VREF1V8

AIN2

AGND_REF

AIN5

AIN6

VZERO0

CE0

RE1

DE1

SE1

AIN7_LPF1

RCAL0

RCAL1

VREF_1.8V

AIN4_LPF0

SE0

DE0

RE0

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR DRAWING NO.

SCALE

SIZE

REV

SHEET

APPROVED

DESCRIPTION

REVISIONS

OL G

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

ANV

OF ANALOG DEVICES.

SCHEMATIC

PTD ENGINEER

DESIGN VIEW

REV DATE

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