Caen V977 Technisches Dokument

Technical

Information

Manual

MOD. V977

27 August 2004

Revision n. 1

16 CHANNEL

I/O Register (Status A)

MANUAL REV.1

NPO:

00118/01:V977X.MUTX/01

CAEN will repair or replace any product within the guarantee period if the Guarantor declares

that the product is defective due to workmanship or materials and has not been caused by

mishandling, negligence on behalf of the User, accident or any abnormal conditions or

operations.

CAEN declines all responsibility for damages or

injuries caused by an improper use of the Modules

due to negligence on behalf of the User. It is strongly

recommended to read thoroughly the CAEN User's

Manual before any kind of operation.

CAEN reserves the right to change partially or entirely the contents of this Manual at any time

and without giving any notice.

Document type: Title: Revision date: Revision:

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TABLE OF CONTENTS

1. OVERVIEW............................................................................................................................................................................5

1.1. MODULE DESCRIPTION.................................................................................................................................................5

2. SPECIFICATIONS ...............................................................................................................................................................6

2.1. PACKAGING ...................................................................................................................................................................6

2.2. EXTERNAL COMPONENTS............................................................................................................................................6

2.3. INTERNAL COMPONENTS..............................................................................................................................................7

2.4. POWER REQUIREMENTS...............................................................................................................................................7

2.5. TECHNICAL SPECIFICATION TABLES..........................................................................................................................7

2.6. FRONT PANEL................................................................................................................................................................8

3. OPERATING MODES.........................................................................................................................................................9

3.1. FUNCTIONAL DESCRIPTION.........................................................................................................................................9

3.1.1. I/O register mode...........................................................................................................................................10

3.1.2.Multihit pattern unit mode............................................................................................................................10

3.1.3. Test channel....................................................................................................................................................11

3.2. OR LOGIC.....................................................................................................................................................................12

3.3. INTERRUPTER CAPABILITY........................................................................................................................................12

4. VME INTERFACE............................................................................................................................................................14

4.1. ADDRESSING CAPABILITY.........................................................................................................................................14

4.2. DATA TRANSFER CAPABILITY...................................................................................................................................14

4.3. INPUT SET REGISTER...................................................................................................................................................15

4.4. INPUT MASK REGISTER...............................................................................................................................................16

4.5. INPUT READ REGISTER...............................................................................................................................................16

4.6. SINGLE-HIT READ REGISTER......................................................................................................................................16

4.7. MULTI-HIT READ REGISTER.......................................................................................................................................16

4.8. OUTPUT SET REGISTER...............................................................................................................................................17

4.9. OUTPUT MASK REGISTER...........................................................................................................................................17

4.10. INTERRUPT MASK.......................................................................................................................................................17

4.11. OUTPUT CLEAR REGISTER..........................................................................................................................................17

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4.12. SINGLEHIT READ-CLEAR REGISTER..........................................................................................................................18

4.13. MULTIHIT READ-CLEAR REGISTER...........................................................................................................................18

4.14. TEST CONTROL REGISTER..........................................................................................................................................18

4.15. INTERRUPT LEVEL.......................................................................................................................................................19

4.16. INTERRUPT VECTOR....................................................................................................................................................19

4.17. SERIAL NUMBER..........................................................................................................................................................19

4.18. FIRMWARE REVISION..................................................................................................................................................19

4.19. CONTROL REGISTER...................................................................................................................................................19

4.20. DUMMY16....................................................................................................................................................................20

4.21. SOFTWARE RESET .......................................................................................................................................................20

REFERENCES.............................................................................................................................................................................21

LIST OF FIGURES

FIG. 2.1: MOD. V977 FRONT PANEL ..............................................................................................................................................8

FIG. 3.1: MOD. V977 CHANNEL STRUCTURE.................................................................................................................................9

FIG. 3.2: I/O REGISTER MODE........................................................................................................................................................10

FIG. 3.3: MULTIHIT PATTERN UNIT MODE....................................................................................................................................11

FIG. 3.4: TEST CHANNEL.................................................................................................................................................................12

FIG. 3.5: INTERRUPTER SCHEME....................................................................................................................................................13

FIG. 4.1: MOD. V977 BASE ADDRESS SETTING AND OUTPUT SELECTION...............................................................................15

LIST OF TABLES

TABLE 2.1: POWER REQUIREMENTS................................................................................................................................................7

TABLE 2.2: TECHNICAL FEATURES..................................................................................................................................................7

TABLE 4.1: ADDRESS MAP FOR THE MOD. V977.......................................................................................................................14

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1. Overview

1.1. Module description

The Mod. V977 is a 1-unit wide VME module that can work either as 16 channel general

purpose I/O Register or as Multihit Pattern Unit; the operating mode is selected via VME

and is signalled via front panel LED.

The module has 16 channels; each channel is provided with one input and one output

connector. Input signals can be indifferently NIM or TTL; an on-board switch allows to

select between NIM and TTL signals for the outputs.

2 LEDs signal the I/O status of each channel.

The module features an additional channel (TEST CHANNEL), which allows to send a

test pulse via a front panel pushbutton. The TEST output signal can be either NIM or TTL,

selected with the same on-board switch of the channels output.

Input signals can be individually masked via VME or globally via a front panel GATE

input. The channel status can be cleared either via VME or via the front panel common

CLEAR input. GATE and CLEAR signals can be indifferently NIM or TTL.

The channels global OR and /OR outputs are available as front panel signals and can be

eventually masked; OR and /OR can be either NIM or TTL, selected with the same on-

board switch of the channels output.

The module houses also a fully programmable VME RORA INTERRUPTER that

generates a VME interrupt request when the OR of a selected set of output channels has

a TRUE status.

The module uses the VME P1 and P2 connectors, then it fits into both standard and V430

VMEbus crates.

All the models have a special circuitry that allows the board to be removed from and

inserted in a powered crate without switching the crate off (Live Insertion).

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2. Specifications

2.1. Packaging

1-unit wide VME unit. Height: 6U.

2.2. External components

CONNECTORS:

Function Logic Type

connector

Note

16 CHANNELS INPUTS NIM or TTL LEMO 00 50 Ωimpedance

16 CHANNELS OUTPUTS NIM or TTL (selectable)

LEMO 00

1 TEST OUTPUT NIM or TTL (selectable)

LEMO 00

1 CLEAR INPUT NIM or TTL LEMO 00 50 Ωimpedance

1 GATE INPUT NIM or TTL LEMO 00 50 Ωimpedance

2 OR and NOT OR OUTPUT

NIM or TTL (selectable)

LEMO 00

LEDS

Name Function Color

16 I/O STATUS Depends on the module’s programming

status (see § 3.1)Green

16 I/O STATUS Depends on the module’s programming

status (see § 3.1)Green

1 DTACK DATA ACKNOWLEDGE command; lights up

each time a VME access is performed. Green

1 TEST Lights up as a test signal is sent via

pushbutton Green

1 PATTERN Indicates the module’s programming status;

lights up as the module is programmed in

PATTERN mode (see § 3.1)

Yellow

1NIM/TTL Indicates the selected outputs level:

RED=NIM

GREEN=TTL

Red/Green

All LEDs also lights up for a while at power ON to indicate that the board is configuring.

PUSHBUTTON:

No.1, to send the TEST input pulse.

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2.3. Internal components

SWITCHES (see Fig. 4.1):

No.4, rotary switches for the module VME Base address selection.

No.1 jumper for the output signal type selection (up: NIM, down: TTL).

2.4. Power requirements

Table 2.1: Power requirements

Power supply Current absorption

+5 V2.3A

2.5. Technical specification tables

Table 2.2: Technical features

Packaging 1U-wide VME unit

Input channels 16 NIM/TTL levels, 50 Ωimpedance

Output channels 16 NIM/TTL levels (selectable),

to be terminated on 50 Ω

Min. input width 2 ns

I/O delay T.B.D.

Double pulse resolution 5 ns

Output rise/fall time NIM: 1/1 ns; TTL: 3/3 ns

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2.6. Front Panel

Fig. 2.1: Mod. V977 Front Panel

Mod.

V977

16 CH

STATUS A

I/O REGISTER

PATTERN UNIT

CLR

DTACK

TST

/ORGATE

PATTERN NIM/TTL

INPUT

CONNECTORS OUTPUT

CONNECTORS

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3. Operating modes

3.1. Functional description

The Mod. V977 is a 16 channel general purpose I/O Register or as Multihit Pattern Unit

The following figure shows the simplified scheme of a single channel:

OUTPUT

CH #n

OUTPUT

TO IRQ

LOGIC

INPUT

CH #n

INPUT READ

VME REGISTER

CONTROL

PATTERN BIT

INPUT

GATE

INPUT MASK

VMEREGISTER

INPUT SET

VMEREGISTER

CONTROL

GATE MASK BIT

SINGLE HIT READ

VME REGISTER

MULTIHIT READ

VME REGISTER

OUTPUTMASK

VMEREGISTER OUTPUT SET

VME REGISTER

CONTROL

OR MASK BIT

INTERRUPT MASK

VME REGISTER

FROM TEST

CHANNEL

LOGIC

CLEAROUTPUT

VME REGISTER

INPUT

CLEAR

Fig. 3.1: Mod. V977 channel structure

The core of each channel is composed by a couple of FLIP-FLOPs, which perform the

memory functions. The two cascaded FLIP-FLOPs, as shown in Fig. 3.1, allow to detect

the following events: none, one or two input hits. The FLIP-FLOPs status of all channels

can be read via VME, in the SINGLEHIT READ REGISTER and MULTIHIT READ

FLIP_FLOP. The content of such register can also be read by accessing the SINGLEHIT

READ-CLEAR REGISTER and MULTIHIT READ-CLEAR REGISTER: in this case the

FLIP-FLOPs are cleared after readout.

The FLIP-FLOPs of all channels can also be cleared both via VME, by accessing the

CLEAR OUTPUT REGISTER, and via the front panel CLEAR signal.

The FLIP FLOPs are set either via an input hit or via VME write access (INPUT SET

The capabilty of receiving input hits can be masked via VME through the INPUT MASK

channels), which can be masked in its turn.

The status of the inputs can also be read directly via VME in the INPUT READ

The status of the channel LEDs and of the outputs depend on the module’s programming.

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3.1.1. I/O register mode

The module operates as I/O register if the PATTERN bit of the CONTROL REGISTER is

set to 0 (default setting).

In this case the simplified channel scheme is shown in Fig. 3.2.

PATTERN = 0

OUTPUT

CH#n

to OR and IRQ

LOGIC

INPUT

CH #n

INPUT READ

VME REGISTER

INPUT

GATE

INPUT MASK

VMEREGISTER

INPUT SET

VMEREGISTER

CONTROL

GATE MASK BIT

SINGLE HIT READ

VME REGISTER

OUTPUT MASK

VME REGISTER OUTPUT SET

VMEREGISTER

CLEAR OUTPUT

VME REGISTER

INPUT

CLEAR

Fig. 3.2: I/O register mode

In this operating mode the output of one channel is active when a single hit (from front

panel or VME generated) is received. The output can also be set by a write access to the

OUTPUT SET REGISTER.

The outputs can also be masked, individually for each channel, through the OUTPUT

MASK REGISTER.

In this operating mode, the two channel LEDs identify the channel status in the following

way:

Left LED: input signal active;

Right LED: output signal active.

3.1.2. Multihit pattern unit mode

The module operates as multihit pattern unit if the PATTERN bit of the CONTROL

In this case the simplified channel scheme is shown in Fig 3.3.

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