Cypress Semiconductor CY7C68033 Bedienungsanleitung

EZ-USB NX2LP-Flex™ Flexible USB NAND Flash Controller

CY7C68033/CY7C68034

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 001-04247 Rev. *D Revised September 21, 2006

CY7C68033/CY7C68034 Silicon Features

• Certified compliant for Bus- or Self-powered USB 2.0

operation (TID# 40490118)

• Single-chip, integrated USB 2.0 transceiver and smart SIE

• Ultra low power – 43 mA typical current draw in any mode

• Enhanced 8051 core

— Firmware runs from internal RAM, which is downloaded

from NAND flash at startup

— No external EEPROM required

• 15 KBytes of on-chip Code/Data RAM

— Default NAND firmware ~8 kB

— Default free space ~7 kB

• Four programmable BULK/INTERRUPT/ISOCHRONOUS

endpoints

— Buffering options: double, triple, and quad

• Additional programmable (BULK/INTERRUPT) 64-byte

endpoint

• SmartMedia StandardHardwareECCgeneration with1-bit

correction and 2-bit detection

• GPIF (General Programmable Interface)

— Allows direct connection to most parallel interfaces

— Programmable waveform descriptors and configuration

registers to define waveforms

— SupportsmultipleReady(RDY)inputsandControl(CTL)

outputs

• 12 fully-programmable GPIO pins

• Integrated, industry-standard enhanced 8051

— 48-MHz, 24-MHz, or 12-MHz CPU operation

— Four clocks per instruction cycle

— Three counter/timers

— Expanded interrupt system

— Two data pointers

• 3.3V operation with 5V tolerant inputs

• Vectored USB interrupts and GPIF/FIFO interrupts

• Separate data buffers for the Set-up and Data portions of a

CONTROL transfer

• Integrated I2C™ controller, runs at 100 or 400 kHz

• Four integrated FIFOs

— Integrated glue logic and FIFOs lower system cost

— Automatic conversion to and from 16-bit buses

— Master or slave operation

— Uses external clock or asynchronous strobes

— Easy interface to ASIC and DSP ICs

• Available in space saving, 56-pin QFN package

CY7C68034 Only Silicon Features:

• Ideal for battery powered applications

— Suspend current: 100 μA (typ.)

CY7C68033 Only Silicon Features:

• Ideal for non-battery powered applications

— Suspend current: 300 μA (typ.)

x20

PLL

/0.5

/1.0

/2.0

8051 Core

12/24/48 MHz,

four clocks/cycle

VCC

1.5k

D+

D–

Address (16)/Data Bus (8)

GPIF

Smart

USB

1.1/2.0

Engine

USB

2.0

XCVR

Additional I/Os

CTL (3)

RDY (2)

8/16

ECC

NAND

Boot Logic

(ROM)

NX2LP-Flex

24 MHz

Ext. Xtal

Connected for

full-speed USB

Integrated full- and

high-speed XCVR

15 kB

RAM

GeneralProgrammable

I/F to ASIC/DSP or bus

standards such as 8-bit

NAND, EPP, etc.

4 kB

FIFO

Up to 96 MB/s burst rate

High-performance,

enhanced 8051 core

with low power options

‘Soft Configuration’ enables

easy firmware changes FIFO and USB endpoint memory

(master or slave modes)

Enhanced USB core

simplifies 8051 code

I2C

Master

Block Diagram

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Document #: 001-04247 Rev. *D Page 2 of 33

Default NAND Firmware Features

Because the NX2LP-Flex™ is intended for NAND

Flash-based USB mass storage applications, a default

firmware image is included in the development kit with the

following features:

• High (480-Mbps) or full (12-Mbps) speed USB support

• Both common NAND page sizes supported

— 512 bytes for up to 1 Gb capacity

— 2K bytes for up to 8 Gb capacity

• 12 configurable general-purpose I/O (GPIO) pins

— 2 dedicated chip enable (CE#) pins

— 6 configurable CE#/GPIO pins

• Upto8NANDFlashsingle-device(single-die)chipsare

supported

• Up to 4 NAND Flash dual-device (dual-die) chips are

supported

• Compile option allows unused CE# pins to be config-

ured as GPIOs

— 4 dedicated GPIO pins

• Industry standard ECC NAND Flash correction

— 1-bit per 256-bit correction

— 2-bit error detection

• Industry standard (SmartMedia) page management for

wear leveling algorithm, bad block handling, and Physical

to Logical management.

• 8-bit NAND Flash interface support

• Support for 30-ns, 50-ns, and 100-ns NAND Flash timing

• Complies with the USB Mass Storage Class Specification

revision 1.0

The default firmware image implements a USB 2.0 NAND

Flash controller. This controller adheres to the Mass Storage

Class Bulk-Only Transport Specification. The USB port of the

NX2LP-Flex is connected to a host computer directly or via the

downstream port of a USB hub. Host software issues

commands and data to the NX2LP-Flex and receives status

and data from the NX2LP-Flex using standard USB protocol.

The default firmware image supports industry leading 8-bit

NAND Flash interfaces and both common NAND page sizes

of 512 and 2k bytes. Up to eight chip enable pins allow the

NX2LP-Flex to be connected to up to eight single- or four

dual-die NAND Flash chips.

Complete source code and documentation for the default

firmware image are included in the NX2LP-Flex development

kit to enable customization for meeting design requirements.

Additionally, compile options for the default firmware allow for

quick configuration of some features to decrease design effort

and increase time-to-market advantages.

Overview

Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB

NX2LP-Flex (CY7C68033/CY7C68034) is a firmware-based,

programmable version of the EZ-USB NX2LP™

(CY7C68023/CY7C68024), which is a fixed-function,

low-power USB 2.0 NAND Flash controller. By integrating the

USB 2.0 transceiver, serial interface engine (SIE), enhanced

8051 microcontroller, and a programmable peripheral

interface in a single chip, Cypress has created a very

cost-effective solution that enables feature-rich NAND

Flash-based applications.

The ingenious architecture of NX2LP-Flex results in USB data

transfer rates of over 53 Mbytes per second, the

maximum-allowable USB 2.0 bandwidth, while still using a

low-cost 8051 microcontroller in a small 56-pin QFN package.

Because it incorporates the USB 2.0 transceiver, the

NX2LP-Flex is more economical, providing a smaller footprint

solution than external USB 2.0 SIE or transceiver implemen-

tations. With EZ-USB NX2LP-Flex, the Cypress Smart SIE

handles most of the USB 1.1 and 2.0 protocol, freeing the

embedded microcontroller for application-specific functions

and decreasing development time while ensuring USB

compatibility.

The General Programmable Interface (GPIF) and

Master/Slave Endpoint FIFO (8- or 16-bit data bus) provide an

easy and glueless interface to popular interfaces such as

UTOPIA, EPP, I2C, PCMCIA, and most DSP processors.

Applications

The NX2LP-Flex allows designers to add extra functionality to

basic NAND Flash mass storage designs, or to interface them

with other peripheral devices. Applications may include:

• NAND Flash-based GPS devices

• NAND Flash-based DVB video capture devices

• Wireless pointer/presenter tools with NAND Flash storage

• NAND Flash-based MPEG/TV conversion devices

• Legacy conversion devices with NAND Flash storage

• NAND Flash-based cameras

• NAND Flash mass storage device with biometric (e.g.,

fingerprint) security

• Home PNA devices with NAND Flash storage

• Wireless LAN with NAND Flash storage

• NAND Flash-based MP3 players

• LAN networking with NAND Flash storage

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Document #: 001-04247 Rev. *D Page 3 of 33

Figure 1. Example DVB Block Diagram

Figure 2. Example GPS Block Diagram

The “Reference Designs” section of the Cypress web site

providesadditionaltoolsfortypical USB2.0applications.Each

reference design comes complete with firmware source and

object code, schematics, and documentation. Please visit

http://www.cypress.com for more information.

Functional Overview

USB Signaling Speed

NX2LP-Flex operates at two of the three rates defined in the

USB Specification Revision 2.0, dated April 27, 2000:

• Full speed, with a signaling bit rate of 12 Mbps

• High speed, with a signaling bit rate of 480 Mbps.

NX2LP-Flex does not support the low-speed signaling mode

of 1.5 Mbps.

8051 Microprocessor

The 8051 microprocessor embedded in the NX2LP-Flex has

256 bytes of register RAM, an expanded interrupt system and

three timer/counters.

8051 Clock Frequency

NX2LP-Flex has an on-chip oscillator circuit that uses an

external 24-MHz (±100-ppm) crystal with the following charac-

teristics:

• Parallel resonant

• Fundamental mode

• 500-μW drive level

• 12-pF (5% tolerance) load capacitors.

An on-chip PLL multiplies the 24-MHz oscillator up to

480 MHz, as required by the transceiver/PHY, and internal

counters divide it down for use as the 8051 clock. The default

8051 clock frequency is 12 MHz. The clock frequency of the

8051 can be changed by the 8051 through the CPUCS

Figure 3. Crystal Configuration.

Special Function Registers

Certain 8051 SFR addresses are populated to provide fast

access to critical NX2LP-Flex functions. These SFR additions

are shown in Table 1. Bold type indicates non-standard,

enhanced 8051 registers. The two SFR rows that end with ‘0’

and ‘8’ contain bit-addressable registers. The four I/O ports

A–D use the SFR addresses used in the standard 8051 for

ports 0–3, which are not implemented in NX2LP-Flex.

Because of the faster and more efficient SFR addressing, the

NX2LP-Flex I/O ports are not addressable in external RAM

space (using the MOVX instruction).

I2C Bus

NX2LPsupportsthe I2Cbusasamaster onlyat100-/400-kHz.

SCL and SDA pins have open-drain outputs and hysteresis

inputs. These signals must be pulled up to 3.3V, even if no I2C

device is connected. The I2C bus is disabled at startup and

only available for use after the initial NAND access.

LCD NX2LP-

Flex

Buttons

DVB

Decoder

NAND Bank(s)

CE[7:0]

CTL

I/O

D+/-

I/O I/O

NAND-Based

DVB Unit

Audio / Video I/O

NX2LP-

Flex

Buttons

GPS

NAND Bank(s)

CE[7:0]

CTL

I/O

D+/-

I/O I/O

NAND-Based

GPS Unit

LCD I/O 12 pf

12 pf

24 MHz

20 × PLL

C1 C2

12-pF capacitor values assumes a trace capacitance

of 3 pF per side on a four-layer FR4 PCA

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CY7C68033/CY7C68034

Document #: 001-04247 Rev. *D Page 4 of 33

Buses

The NX2LP-Flex features an 8- or 16-bit ‘FIFO’ bidirectional

data bus, multiplexed on I/O ports B and D.

The default firmware image implements an 8-bit data bus in

GPIF Master mode. It is recommended that additional inter-

faces added to the default firmware image use this 8-bit data

bus.

Enumeration

During the start-up sequence, internal logic checks for the

presence of NAND Flash with valid firmware. If valid firmware

is found, the NX2LP-Flex loads it and operates according to

the firmware. If no NAND Flash is detected, or if no valid

firmware is found, the NX2LP-Flex uses the default values

from internal ROM space for manufacturing mode operation.

The two modes of operation are described in the section

”Normal Operation Mode” on page 5 and ”Manufacturing

Mode” on page 5.

Table 1. Special Function Registers

x8x 9x Ax Bx CxDxExFx

0IOA IOB IOC IOD SCON1 PSW ACC B

1SP EXIF INT2CLR IOE SBUF1

2DPL0 MPAGE INT4CLR OEA

3DPH0 OEB

4DPL1 OEC

5DPH1 OED

6DPS OEE

7PCON

8 TCON SCON0 IE IP T2CON EICON EIE EIP

9 TMOD SBUF0

ATL0AUTOPTRH1 EP2468STAT EP01STAT RCAP2L

BTL1AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H

CTH0RESERVED EP68FIFOFLGS TL2

DTH1AUTOPTRH2 GPIFSGLDATH TH2

ECKCON AUTOPTRL2 GPIFSGLDATLX

FRESERVED AUTOPTRSET-UP GPIFSGLDATLNOX

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Document #: 001-04247 Rev. *D Page 5 of 33

Figure 4. NX2LP-Flex Enumeration Sequence

Normal Operation Mode

In Normal Operation Mode, the NX2LP-Flex behaves as a

USB 2.0 Mass Storage Class NAND Flash controller. This

includes all typical USB device states (powered, configured,

etc.). The USB descriptors are returned according to the data

stored in the configuration data memory area. Normal read

and write access to the NAND Flash is available in this mode.

Manufacturing Mode

In Manufacturing Mode, the NX2LP-Flex enumerates using

the default descriptors and configuration data that are stored

in internal ROM space. This mode allows for first-time

programming of the configuration data memory area, as well

as board-level manufacturing tests.

Default Silicon ID Values

To facilitate proper USB enumeration when no programmed

NAND Flash is present, the NX2LP-Flex has default silicon ID

values stored in ROM space. The default silicon ID values

should only be used for development purposes. Cypress

requires designers to use their own Vendor ID for final

products. A Vendor ID is obtained through registration with the

USB Implementor’s Forum (USB-IF). Also, if the NX2LP-Flex

is used as a mass storage class device, a unique USB serial

number is required for each device in order to comply with the

USB Mass Storage class specification.

Cypress provides all the software tools and drivers necessary

for properly programming and testing the NX2LP-Flex. Please

refer to the documentation in the development kit for more

information on these topics.

ReNumeration™

Cypress’s ReNumeration™ feature is used in conjunction with

the NX2LP-Flex manufacturing software tools to enable

first-time NAND programming. It is only available when used

in conjunction with the NX2LP-Flex Manufacturing tools, and

is not enabled during normal operation.

Bus-powered Applications

The NX2LP-Flex fully supports bus-powered designs by

enumerating with less than 100 mA, as required by the USB

2.0 specification.

Interrupt System

INT2 Interrupt Request and Enable Registers

NX2LP-Flex implements an autovector feature for INT2 and

INT4. There are 27 INT2 (USB) vectors, and 14 INT4

(FIFO/GPIF) vectors. See the EZ-USB Technical Reference

Manual (TRM) for more details.

USB-Interrupt Autovectors

The main USB interrupt is shared by 27 interrupt sources. To

save the code and processing time that normally would be

required to identify the individual USB interrupt source, the

NX2LP-Flex provides a second level of interrupt vectoring,

called Autovectoring. When a USB interrupt is asserted, the

NX2LP-Flex pushes the program counter onto its stack then

jumps to address 0x0500, where it expects to find a ‘jump’

instruction to the USB Interrupt service routine.

Developers familiar with Cypress’s programmable USB

devices should note that these interrupt vector values differ

from those used in other EZ-USB microcontrollers. This is due

to the additional NAND boot logic that is present in the

NX2LP-Flex ROM space. Also, these values are fixed and

cannot be changed in the firmware.

NAND Flash

Programmed?

Load Default

Descriptors and

Configuration Data

Manufacturing

Mode

Load Firmware

From NAND

Enumerate

According To

Firmware

Normal Operation

Mode

Start-up

Enumerate As

Unprogrammed

NX2LP-Flex

NAND Flash

Present?

Yes

Yes No

Table 2. Default Silicon ID Values

Default VID/PID/DID

Vendor ID 0x04B4 Cypress Semiconductor

Product ID 0x8613 EZ-USB®Default

Device release 0xAnnn Depends on chip revision

(nnn = chip revision, where first

silicon = 001)

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CY7C68033/CY7C68034

Document #: 001-04247 Rev. *D Page 6 of 33

If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP

Therefore, if the high byte (‘page’) of a jump-table address is

preloaded at location 0x544, the automatically-inserted

INT2VEC byte at 0x545 will direct the jump to the correct

address out of the 27 addresses within the page.

FIFO/GPIF Interrupt (INT4)

Just as the USB Interrupt is shared among 27 individual

USB-interrupt sources, the FIFO/GPIF interrupt is shared

among 14 individual FIFO/GPIF sources. The FIFO/GPIF

Interrupt, like the USB Interrupt, can employ autovectoring.

Table 4 shows the priority and INT4VEC values for the 14

FIFO/GPIF interrupt sources.

Table 3. INT2 USB Interrupts

USB INTERRUPT TABLE FOR INT2

Priority INT2VEC Value Source Notes

1 0x500 SUDAV Setup Data Available

2 0x504 SOF Start of Frame (or microframe)

3 0x508 SUTOK Setup Token Received

4 0x50C SUSPEND USB Suspend request

5 0x510 USB RESET Bus reset

6 0x514 HISPEED Entered high speed operation

7 0x518 EP0ACK NX2LP ACK’d the CONTROL Handshake

8 0x51C Reserved

9 0x520 EP0-IN EP0-IN ready to be loaded with data

10 0x524 EP0-OUT EP0-OUT has USB data

11 0x528 EP1-IN EP1-IN ready to be loaded with data

12 0x52C EP1-OUT EP1-OUT has USB data

13 0x530 EP2 IN: buffer available. OUT: buffer has data

14 0x534 EP4 IN: buffer available. OUT: buffer has data

15 0x538 EP6 IN: buffer available. OUT: buffer has data

16 0x53C EP8 IN: buffer available. OUT: buffer has data

17 0x540 IBN IN-Bulk-NAK (any IN endpoint)

18 0x544 Reserved

19 0x548 EP0PING EP0 OUT was Pinged and it NAK’d

20 0x54C EP1PING EP1 OUT was Pinged and it NAK’d

21 0x550 EP2PING EP2 OUT was Pinged and it NAK’d

22 0x554 EP4PING EP4 OUT was Pinged and it NAK’d

23 0x558 EP6PING EP6 OUT was Pinged and it NAK’d

24 0x55C EP8PING EP8 OUT was Pinged and it NAK’d

25 0x560 ERRLIMIT Bus errors exceeded the programmed limit

26 0x564 Reserved

27 0x568 Reserved

28 0x56C Reserved

29 0x570 EP2ISOERR ISO EP2 OUT PID sequence error

30 0x574 EP4ISOERR ISO EP4 OUT PID sequence error

31 0x578 EP6ISOERR ISO EP6 OUT PID sequence error

32 0x57C EP8ISOERR ISO EP8 OUT PID sequence error

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Document #: 001-04247 Rev. *D Page 7 of 33

If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP

Therefore, if the high byte (‘page’) of a jump-table address is

preloaded at location 0x554, the automatically-inserted

INT4VEC byte at 0x555 will direct the jump to the correct

address out of the 14 addresses within the page. When the

ISR occurs, the NX2LP-Flex pushes the program counter onto

its stack then jumps to address 0x553, where it expects to find

a ‘jump’ instruction to the ISR Interrupt service routine.

Reset and Wakeup

Reset Pin

The input pin RESET#, will reset the NX2LP-Flex when

asserted. This pin has hysteresis and is active LOW. When a

crystal is used as the clock source for the NX2LP-Flex, the

reset period must allow for the stabilization of the crystal and

the PLL. This reset period should be approximately 5 ms after

VCC has reached 3.0V. If the crystal input pin is driven by a

clock signal, the internal PLL stabilizes in 200 μs after VCC has

reached 3.0V[1]. Figure 5 shows a power-on reset condition

and a reset applied during operation. A power-on reset is

defined as the time reset is asserted while power is being

applied to the circuit. A powered reset is defined to be when

the NX2LP-Flex has previously been powered on and

operating and the RESET# pin is asserted.

Cypress provides an application note which describes and

recommendspoweron resetimplementationandcanbe found

on the Cypress web site. For more information on reset imple-

mentation for the EZ-USB family of products visit the

http://www.cypress.com website.

Table 4. Individual FIFO/GPIF Interrupt Sources

Priority INT4VEC Value Source Notes

1 0x580 EP2PF Endpoint 2 Programmable Flag

2 0x584 EP4PF Endpoint 4 Programmable Flag

3 0x588 EP6PF Endpoint 6 Programmable Flag

4 0x58C EP8PF Endpoint 8 Programmable Flag

5 0x590 EP2EF Endpoint 2 Empty Flag

6 0x594 EP4EF Endpoint 4 Empty Flag

7 0x598 EP6EF Endpoint 6 Empty Flag

8 0x59C EP8EF Endpoint 8 Empty Flag

9 0x5A0 EP2FF Endpoint 2 Full Flag

10 0x5A4 EP4FF Endpoint 4 Full Flag

11 0x5A8 EP6FF Endpoint 6 Full Flag

12 0x5AC EP8FF Endpoint 8 Full Flag

13 0x5B0 GPIFDONE GPIF Operation Complete

14 0x5B4 GPIFWF GPIF Waveform

Note

1. If the external clock is powered at the same time as the CY7C68033/CY7C68034 and has a stabilization wait period, it must be added to the 200 μs.

Figure 5. Reset Timing Plots

VIL

3.3V

3.0V

TRESET

VCC

RESET#

Power-on Reset

TRESET

VCC

RESET# VIL

Powered Reset

3.3V

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Document #: 001-04247 Rev. *D Page 8 of 33

Wakeup Pins

The 8051 puts itself and the rest of the chip into a power-down

mode by setting PCON.0 = 1. This stops the oscillator and

PLL. When WAKEUP is asserted by external logic, the oscil-

lator restarts, after the PLL stabilizes, and then the 8051

receives a wakeup interrupt. This applies whether or not

NX2LP-Flex is connected to the USB.

The NX2LP-Flex exits the power-down (USB suspend) state

using one of the following methods:

• USB bus activity (if D+/D– lines are left floating, noise on

these lines may indicate activity to the NX2LP-Flex and

initiate a wakeup).

• External logic asserts the WAKEUP pin

• External logic asserts the PA3/WU2 pin.

The second wakeup pin, WU2, can also be configured as a

general purpose I/O pin. This allows a simple external R-C

network to be used as a periodic wakeup source. Note that

WAKEUP is, by default, active LOW.

Program/Data RAM

Internal ROM/RAM Size

The NX2LP-Flex has 1 kBytes ROM and 15 kBytes of internal

program/data RAM, where PSEN#/RD# signals are internally

ORed to allow the 8051 to access it as both program and data

memory. No USB control registers appear in this space.

Internal Code Memory

This mode implements the internal block of RAM (starting at

0x0500) as combined code and data memory, as shown in

Figure 6, below.

Only the internal and scratch pad RAM spaces have the

following access:

• USB download (only supported by the Cypress Manufac-

turing Tool)

• Setup data pointer

• NAND boot access.

Figure 6. Internal Code Memory

Figure 7. Internal Register Addresses

Table 5. Reset Timing Values

Condition TRESET

Power-on Reset with crystal 5 ms

Power-on Reset with external

clock source 200 μs + Clock stability time

Powered Reset 200 μs

*SUDPTR, USB download, NAND boot access

FFFF

E200

E1FF

E000

3FFF

0000

7.5 kBytes

USB registers

and 4 kBytes

FIFO buffers

(RD#, WR#)

512 Bytes RAM Data

(RD#, WR#)*

15 kBytes RAM

Code and Data

(PSEN#, RD#,

WR#)*

0500 1 kbyte ROM

FFFF

E800

E7BF

E740

E73F

E700

E6FF

E500

E4FF

E480

E47F

E400

E200

E1FF

E000

E3FF

EFFF 2 KBytes RESERVED

64 Bytes EP0 IN/OUT

64 Bytes RESERVED

8051 Addressable Registers

Reserved (128)

128 bytes GPIF Waveforms

512 bytes

8051 xdata RAM

F000

(512)

Reserved (512)

E780 64 Bytes EP1OUT

E77F

64 Bytes EP1IN

E7FF

E7C0

4 KBytes EP2-EP8

buffers

(8 x 512)

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Document #: 001-04247 Rev. *D Page 9 of 33

Endpoint RAM

Size

• 3 × 64 bytes (Endpoints 0 and 1)

• 8 × 512 bytes (Endpoints 2, 4, 6, 8)

Organization

• EP0

— Bidirectional endpoint zero, 64-byte buffer

• EP1IN, EP1OUT

— 64-byte buffers, bulk or interrupt

• EP2,4,6,8

— Eight 512-byte buffers, bulk, interrupt, or isochronous.

— EP4 and EP8 can be double buffered, while EP2 and 6

can be either double, triple, or quad buffered.

For high-speed endpoint configuration options, see Figure 8.

Setup Data Buffer

A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup

data from a CONTROL transfer.

Endpoint Configurations (High-speed Mode)

Endpoints 0 and 1 are the same for every configuration.

Endpoint0 istheonly CONTROLendpoint,and endpoint1can

be either BULK or INTERRUPT. The endpoint buffers can be

configured in any 1 of the 12 configurations shown in the

vertical columns. When operating in full-speed BULK mode,

only the first 64 bytes of each buffer are used. For example, in

high-speed the max packet size is 512 bytes, but in full-speed

it is 64 bytes. Even though a buffer is configured to be a 512

byte buffer, in full-speed only the first 64 bytes are used. The

unused endpoint buffer space is not available for other opera-

tions. An example endpoint configuration would be:

EP2–1024 double buffered; EP6–512 quad buffered

(column 8 in Figure 8).

Figure 8. Endpoint Configuration

Default Full-Speed Alternate Settings

512

1024

512

EP2 EP2 EP2

EP6

EP8 EP8

EP0 IN&OUT

EP1 IN

EP1 OUT

1024

EP6 1024

512

EP8

512

EP6

512

EP2

512

EP4

512

EP2

512

EP4

512

EP2

512

EP4

512

EP2

512

EP2

512

EP2

512

1024

EP2

1024

EP2

1024

EP2

1024

512

EP6

1024

EP6

512

EP8

512

EP6

512

EP6

1024

EP6

512

EP8

512

EP6

512

12345678910 11 12

Table 6. Default Full-Speed Alternate Settings[2, 3]

Alternate Setting 0 1 2 3

ep0 64 64 64 64

ep1out 0 64 bulk 64 int 64 int

ep1in 0 64 bulk 64 int 64 int

ep2 0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×)

Notes

2. ‘0’ means ‘not implemented.’

3. ‘2×’ means ‘double buffered.’

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Document #: 001-04247 Rev. *D Page 10 of 33

Default High-Speed Alternate Settings

External FIFO Interface

Architecture

The NX2LP-Flex slave FIFO architecture has eight 512-byte

blocks in the endpoint RAM that directly serve as FIFO

memories, and are controlled by FIFO control signals (such as

SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).

In operation, some of the eight RAM blocks fill or empty from

the SIE, while the others are connected to the I/O transfer

logic.Thetransfer logictakestwo forms,theGPIFforinternally

generated control signals, or the slave FIFO interface for

externally controlled transfers.

Master/Slave Control Signals

The NX2LP-Flex endpoint FIFOS are implemented as eight

physically distinct 256x16 RAM blocks. The 8051/SIE can

switch any of the RAM blocks between two domains, the USB

(SIE) domain and the 8051-I/O Unit domain. This switching is

done virtually instantaneously, giving essentially zero transfer

time between ‘USB FIFOS’ and ‘Slave FIFOS.’ Since they are

physically the same memory, no bytes are actually transferred

between buffers.

At any given time, some RAM blocks are filling/emptying with

USB data under SIE control, while other RAM blocks are

available to the 8051 and/or the I/O control unit. The RAM

blocks operate as single-port in the USB domain, and

dual-port in the 8051-I/O domain. The blocks can be

configured as single, double, triple, or quad buffered as previ-

ously shown.

The I/O control unit implements either an internal-master (M

for master) or external-master (S for Slave) interface.

In Master (M) mode, the GPIF internally controls

FIFOADR[1:0] to select a FIFO. The two RDY pins can be

used as flag inputs from an external FIFO or other logic if

desired. The GPIF can be run from an internally derived clock

(IFCLK), at a rate that transfers data up to 96 Megabytes/s

(48-MHz IFCLK with 16-bit interface).

In Slave (S) mode, the NX2LP-Flex accepts an internally

derived clock (IFCLK, max. frequency 48 MHz) and SLCS#,

SLRD, SLWR, SLOE, PKTEND signals from external logic.

Each endpoint can individually be selected for byte or word

operation by an internal configuration bit, and a Slave FIFO

Output Enable signal SLOE enables data of the selected

width. External logic must ensure that the output enable signal

is inactive when writing data to a slave FIFO. The slave

interface must operate asynchronously, where the SLRD and

SLWR signals act directly as strobes, rather than a clock

qualifier as inasynchronous mode. ThesignalsSLRD,SLWR,

SLOE and PKTEND are gated by the signal SLCS#.

GPIF and FIFO Clock Rates

An 8051 register bit selects one of two frequencies for the

internally supplied interface clock: 30 MHz and 48 MHz. A bit

within the IFCONFIG register will invert the IFCLK signal.

The default NAND firmware image implements a 48-MHz

internally supplied interface clock. The NAND boot logic uses

the same configuration to implement 100-ns timing on the

NAND bus to support proper detection of all NAND Flash

types.

GPIF

The GPIF is a flexible 8- or 16-bit parallel interface driven by a

user-programmable finite state machine. It allows the

NX2LP-Flex to perform local bus mastering, and can

implement a wide variety of protocols such as 8-bit NAND

interface, printer parallel port, and Utopia. The default NAND

firmware and boot logic utilizes GPIF functionality to interface

with NAND Flash.

The GPIF on the NX2LP-Flex features three programmable

control outputs (CTL) and two general-purpose ready inputs

(RDY). The GPIF data bus width can be 8 or 16 bits. Because

ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)

ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×)

ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)

Table 6. Default Full-Speed Alternate Settings[2, 3] (continued)

Note

4. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.

Table 7. Default High-Speed Alternate Settings[2, 3]

Alternate Setting 0 1 2 3

ep0 64 64 64 64

ep1out 0 512 bulk[4] 64 int 64 int

ep1in 0 512 bulk[4] 64 int 64 int

ep2 0 512 bulk out (2×) 512 int out (2×) 512 iso out (2×)

ep4 0 512 bulk out (2×) 512 bulk out (2×) 512 bulk out (2×)

ep6 0 512 bulk in (2×) 512 int in (2×) 512 iso in (2×)

ep8 0 512 bulk in (2×) 512 bulk in (2×) 512 bulk in (2×)

[+] Feedback

Dieses Handbuch passt für folgende Modelle

Inhaltsverzeichnis

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