Cypress CY62167DV18 Bedienungsanleitung

16-Mbit (1M x 16) Static RAM

CY62167DV18 MoBL®

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05326 Rev. *C Revised April 25, 2007

Features

• Very high speed: 55 ns

• Wide voltage range: 1.65V–1.95V

• Ultra low active power

— Typical active current: 1.5 mA @ f = 1 MHz

— Typical active current: 15 mA @ f = fmax

• Ultra low standby power

• Easy memory expansion with CE1, CE2, and OE features

• Automatic power down when deselected

• CMOS for optimum speed and power

• Available in Pb-free 48-ball VFBGA package

Functional Description[1]

The CY62167DV18 is a high performance CMOS static RAM

organized as 1M words by 16 bits. This device features

advanced circuit design to provide ultra low active current.

This is ideal for providing More Battery Life™(MoBL®) in

portable applications such as cellular telephones. The device

also has an automatic power down feature that significantly

reduces power consumption by 99% when addresses are not

toggling. Placing the device into standby mode reduces power

consumption by more than 99% when deselected (CE1HIGH

or CE2 LOW or both BHE and BLE are HIGH). The input and

output pins (IO0through IO15) are placed in a high impedance

state when:

• Deselected (CE1 HIGH or CE2LOW)

• Outputs are disabled (OE HIGH)

• Both Byte High Enable (BHE) and Byte Low Enable (BLE)

are disabled (BHE, BLE HIGH)

• Write operation is active (CE1LOW, CE2HIGH and WE

LOW)

To write to the device, take Chip Enables (CE1 LOW and CE2

HIGH) and Write Enable (WE) input LOW. If BLE is LOW, then

data from IO pins (IO0through IO7) is written into the location

specified on the address pins (A0through A19). If BHE is LOW

then data from IO pins (IO8through IO15) is written into the

location specified on the address pins (A0through A19).

To read from the device, take Chip Enables (CE1 LOW and

CE2HIGH) and OE LOW while forcing the WE HIGH. If BLE

is LOW, then data from the memory location specified by the

address pins appear on IO0to IO7. If BHE is LOW, then data

from memory appears on IO8to IO15. See the “Truth Table” on

page 9 for a complete description of read and write modes.

Note

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

Logic Block Diagram

1M × 16

RAM Array IO0–IO7

ROW DECODER

A 8

A 7

A 6

A 5

A 2

COLUMN DECODER

A11

A12

A13

A14

A15

SENSE AMPS

DATA IN DRIVERS

A 4

A 3IO8–IO15

BLE

BHE

A16

A 0

A 1

A17

A 9

A18

A10

CE2

CE1

A19

BYTE

PowerDown

Circuit BHE

BLE

CE2

CE1

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CY62167DV18 MoBL®

Document #: 38-05326 Rev. *C Page 2 of 11

Product Portfolio

Product VCC Range (V) Speed

(ns)

Power Dissipation

Operating ICC (mA) Standby ISB2 (µA)

f = 1MHz f = fmax

Min Typ[2] Max Typ[2] Max Typ[2] Max Typ[2] Max

CY62167DV18LL 1.65 1.8 1.95 55 1.5 5 15 30 2.5 20

Pin Configuration [3]

Notes

2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.

3. DNU pins must be left floating or tied to VSS to ensure proper operation.

A11

A10

A3CE1

IO10

IO8

IO9

IO11

IO13

IO12

IO14

IO15

VSS

IO0

BHE

CE2

A17

BLE

IO2

IO1

IO3

IO4

IO5IO6

IO7

A15

A14

A13

A12

A19

A18 DNU

326

A16

DNU

VCC

VCC VSS

48-Ball VFBGA

Top View

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CY62167DV18 MoBL®

Document #: 38-05326 Rev. *C Page 3 of 11

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of

the device. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential . –0.2V to VCCmax + 0.2V

DC Voltage Applied to Outputs

in High-Z State[4, 5]........................... –0.2V to VCCmax + 0.2V

DC Input Voltage[4, 5] ........................–0.2V to VCCmax + 0.2V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage.......................................... > 2001V

(MIL-STD-883, Method 3015)

Latch up Current..................................................... > 200 mA

Operating Range

Range Ambient

Temperature VCC[6]

Industrial –40°C to +85°C 1.65V to 1.95V

DC Electrical Characteristics (Over the Operating Range)

Parameter Description Test Conditions

55 ns

UnitMin Typ[2] Max

VOH Output HIGH Voltage IOH = −0.1 mA 1.4 V

VOL Output LOW Voltage IOL = 0.1 mA 0.2 V

VIH Input HIGH Voltage 1.4 VCC + 0.2 V

VIL Input LOW Voltage –0.2 0.4 V

IIX Input Leakage Current GND < VI< VCC –1 +1 µA

IOZ Output Leakage Current GND < VO< VCC, Output Disabled –1 +1 µA

ICC VCC Operating Supply Current f = fMAX = 1/tRC VCC = 1.95V, IOUT = 0 mA,

CMOS level

15 30 mA

f = 1 MHz 1.5 5

ISB1 Automatic CE Power down

Current −CMOS Inputs

CE1> VCC −0.2V, CE2< 0.2V,

VIN > VCC −0.2V, VIN < 0.2V,

f = fMAX (Address and Data Only),

f = 0 (OE, WE, BHE and BLE)

2.5 20 µA

ISB2 Automatic CE Power down

Current −CMOS Inputs

CE1> VCC −0.2V, CE2< 0.2V,

VIN > VCC −0.2V or VIN < 0.2V,

f = 0, VCC=1.95V

2.5 20 µA

Notes

4. VIL(min) = –2.0V for pulse durations less than 20 ns.

5. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.

6. Full device AC operation requires linear VCC ramp from 0 to VCC(min) and VCC must be stable at VCC(min) for 500 µs.

7. Tested initially and after any design or process changes that may affect these parameters.

Capacitance [7]

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz, VCC = VCC(typ) 6pF

COUT Output Capacitance 8 pF

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CY62167DV18 MoBL®

Document #: 38-05326 Rev. *C Page 4 of 11

Thermal Resistance [7]

Parameter Description Test Conditions VFBGA Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Still Air, soldered on a 3 × 4.5 inch,

two-layer printed circuit board

55 °C/W

ΘJC Thermal Resistance

(Junction to Case)

16 °C/W

AC Test Loads and Waveforms

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

Rise Time = 1 V/ns Fall Time = 1 V/ns

OUTPUT V

Equivalent to: THEVENIN EQUIVALENT

ALL INPUT PULSES

RTH

Parameters 1.8V Unit

R1 13500 Ω

R2 10800 Ω

RTH 6000 Ω

VTH 0.80 V

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions Min Typ [2] Max Unit

VDR VCC for Data Retention 1.0 1.95 V

ICCDR Data Retention Current VCC= 1.0V, CE1> VCC – 0.2V, CE2< 0.2V,

VIN > VCC – 0.2V or VIN < 0.2V

10 µA

tCDR[7] Chip Deselect to Data Retention Time 0 ns

tR[8] Operation Recovery Time tRC ns

Data Retention Waveform[9]

VCC, min

tCDR

VDR >1.0V

CE1or

VCC

BHE,BLE

CE2

DATA RETENTION MODE

Notes

8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.

9. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.

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CY62167DV18 MoBL®

Document #: 38-05326 Rev. *C Page 5 of 11

Switching Characteristics (Over the Operating Range)[10]

Parameter Description 55 ns Unit

Min Max

Read Cycle

tRC Read Cycle Time 55 ns

tAA Address to Data Valid 55 ns

tOHA Data Hold from Address Change 10 ns

tACE CE1LOW and CE2 HIGH to Data Valid 55 ns

tDOE OE LOW to Data Valid 25 ns

tLZOE OE LOW to LOW Z[11] 5ns

tHZOE OE HIGH to High Z[11, 12] 20 ns

tLZCE CE1LOW and CE2 HIGH to Low Z[11] 10 ns

tHZCE CE1HIGH and CE2 LOW to High Z[11, 12] 20 ns

tPU CE1LOW and CE2 HIGH to Power up 0 ns

tPD CE1HIGH and CE2 LOW to Power down 55 ns

tDBE BLE/BHE LOW to Data Valid 55 ns

tLZBE BLE/BHE LOW to Low Z[11] 5ns

tHZBE BLE/BHE HIGH to HIGH Z[11, 12] 20 ns

Write Cycle[13]

tWC Write Cycle Time 55 ns

tSCE CE1LOW and CE2 HIGH to Write End 40 ns

tAW Address Setup to Write End 40 ns

tHA Address Hold from Write End 0 ns

tSA Address Setup to Write Start 0 ns

tPWE WE Pulse Width 40 ns

tBW BLE/BHE LOW to Write End 45 ns

tSD Data Setup to Write End 25 ns

tHD Data Hold from Write End 0 ns

tHZWE WE LOW to High- [11, 12] 20 ns

tLZWE WE HIGH to Low-Z[11] 10 ns

Notes

10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels

of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.

11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any

given device.

12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.

13. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate

a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that

terminates the write.

[+] Feedback

CY62167DV18 MoBL®

Document #: 38-05326 Rev. *C Page 6 of 11

Switching Waveforms

Read Cycle 1 (Address Transition Controlled)[14, 15]

Read Cycle 2 (OE Controlled)[15, 16]

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tPD

tHZBE

tLZBE

HZCE

tDBE

CE1

ADDRESS

CE2

BHE/BLE

DATA OUT

VCC

SUPPLY

CURRENT

HIGH

ICC

ISB

IMPEDANCE

Notes

14. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.

15. WE is HIGH for read cycle.

16. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2transition HIGH.

[+] Feedback

CY62167DV18 MoBL®

Document #: 38-05326 Rev. *C Page 7 of 11

Write Cycle 1 (WE Controlled)[13, 17, 18]

Write Cycle 2 (CE1or CE2 Controlled)[13, 17, 18]

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

NOTE 19

CE1

ADDRESS

CE2

DATA IO

BHE/BLE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

tSA

NOTE 19

CE1

ADDRESS

CE2

DATA IO

BHE/BLE

Notes

17. Data IO is high impedance if OE = VIH.

18. If CE1goes HIGH and CE2goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.

19. During this period, the IOs are in output state. Do not apply input signals.

[+] Feedback

CY62167DV18 MoBL®

Document #: 38-05326 Rev. *C Page 8 of 11

Write Cycle 3 (WE Controlled, OE LOW)[18]

Write Cycle 4 (BHE/BLE Controlled, OE LOW)[18]

Switching Waveforms (continued)

VALID DATA

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

tBW

NOTE 19

ADDRESS

DATA IO

BHE

/BLE

tHD

tSD

tSA

tHA

tAW

tWC

VALID DATA

tBW

tSCE

tPWE

NOTE 19

ADDRESS

DATA IO

BHE

/BLE

[+] Feedback

CY62167DV18 MoBL®

Document #: 38-05326 Rev. *C Page 9 of 11

Truth Table

CE1CE2WE OE BHE BLE Inputs/Outputs Mode Power

H X X X X X High Z Deselect/Power Down Standby (ISB)

X L X X X X High Z Deselect/Power Down Standby (ISB)

X X X X H H High Z Deselect/Power Down Standby (ISB)

L H H L L L Data Out (IO0–IO15) Read Active (ICC)

L H H L H L High Z (IO8–IO15);

Data Out (IO0–IO7)

Read Active (ICC)

L H H L L H Data Out (IO8–IO15);

High Z (IO0–IO7)

Read Active (ICC)

LHLXLLDataIn(IO

0–IO15) Write Active (ICC)

LHLXHLHighZ(IO

8–IO15);

Data In (IO0–IO7)

Write Active (ICC)

LHLXLHDataIn(IO

8–IO15);

High Z (IO0–IO7)

Write Active (ICC)

L H H H L H High Z Output Disabled Active (ICC)

L H H H H L High Z Output Disabled Active (ICC)

L H H H L L High Z Output Disabled Active (ICC)

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

55 CY62167DV18LL-55BVXI 51-85178 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm) (Pb-free) Industrial

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CY62167DV18 MoBL®

Document #: 38-05326 Rev. *C Page 10 of 11

use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to

be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Package Diagrams

Figure 1. 48-Ball VFBGA (8 x 9.5 x 1 mm), 51-85178

MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names

mentioned in this document are the trademarks of their respective holders.

A1 CORNER

0.75

Ø0.30±0.05(48X)

Ø0.25 M C A B

Ø0.05MC

0.15(4X)

0.21±0.05

1.00 MAX

SEATING PLANE

0.55 MAX.

0.25 C

0.10 C

A1 CORNER

TOP VIEW BOTTOM VIEW

234

3.75

5.25

465231

8.00±0.10

9.50±0.10

8.00±0.10

1.875

2.625

0.26 MAX.

51-85178-**

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