Excalibur DAS-429PCI/Mx Bedienungsanleitung

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DAS-429PCI/Mx

Multi-channel ARINC 429

Test and Simulation Board

for PCI Systems

User’s Manual

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Table of Contents

DAS-429PCI/Mx: User’s Manual page i

Table of Contents

1 Introduction

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2

1.2 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4

1.2.1 Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4

1.2.2 Board Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4

1.3 Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

1.4 PCI Configuration Space Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6

1.5 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

1.5.1 Vendor Identification Register (VID) . . . . . . . . . . . . . . . . . . . . . .1-7

1.5.2 Device Identification Register (DID) . . . . . . . . . . . . . . . . . . . . . .1-7

1.5.3 PCI Command Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8

1.5.4 PCI Status Register (PCISTS). . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

1.5.5 Revision Identification Register (RID) . . . . . . . . . . . . . . . . . . . .1-10

1.5.6 Class Code Register (CLCD) . . . . . . . . . . . . . . . . . . . . . . . . . .1-10

1.5.7 Cache Line Size Register (CALN) . . . . . . . . . . . . . . . . . . . . . . .1-11

1.5.8 Latency Timer Register (LAT) . . . . . . . . . . . . . . . . . . . . . . . . . .1-11

1.5.9 Header Type Register (HDR). . . . . . . . . . . . . . . . . . . . . . . . . . .1-12

1.5.10 Built-In Self-Test Register (BIST) . . . . . . . . . . . . . . . . . . . . . .1-12

1.5.11 Base Address Registers (BADR). . . . . . . . . . . . . . . . . . . . . . .1-13

1.5.12 Expansion ROM Base Address Register (XROM). . . . . . . . . .1-15

1.5.13 Interrupt Line Register (INTLN) . . . . . . . . . . . . . . . . . . . . . . . .1-15

1.5.14 Interrupt Pin Register (INTPIN) . . . . . . . . . . . . . . . . . . . . . . . .1-16

1.5.15 Minimum Grant Register (MINGNT) . . . . . . . . . . . . . . . . . . . .1-16

1.5.16 Maximum Latency Register (MAXLAT) . . . . . . . . . . . . . . . . . .1-16

1.6 PCI Global Interrupt Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-17

1.6.1 PCI Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . .1-17

1.6.2 PCI Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .1-17

2 Module Operation

2.1 Module General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2

2.2 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3

2.3 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4

2.3.1 Global Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . .2-4

2.3.2 Global Interrupt Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . .2-5

2.3.3 Global Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . .2-5

2.4 Module Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6

2.4.1 Start/Stop Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7

2.4.2 Module Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

2.4.3 Firmware Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

2.4.4 Channel Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9

2.4.5 Receiver Data Storage Mode Register . . . . . . . . . . . . . . . . . . . .2-9

2.4.6 Interrupt Status Busy Register. . . . . . . . . . . . . . . . . . . . . . . . . .2-10

2.4.7 Reset Time Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10

2.4.8 Module ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10

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Table of Contents

page ii Excalibur Systems

2.5 Receiver Merge Mode Control Registers . . . . . . . . . . . . . . . . . . . . . .2-11

2.5.1 Receiver Merge Start Pointer . . . . . . . . . . . . . . . . . . . . . . . . . .2-11

2.5.2 Receiver Merge End Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11

2.5.3 Receiver Merge Current Pointer . . . . . . . . . . . . . . . . . . . . . . . .2-11

2.5.4 Receiver Merge Filter Table Start Address . . . . . . . . . . . . . . . .2-11

2.5.5 Receiver Merge Word Count . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11

2.5.6 Receiver Merge Buffer Wraparound Register . . . . . . . . . . . . . .2-12

2.5.7 Receiver Merge Word Count Trigger Register . . . . . . . . . . . . .2-12

2.5.8 Receiver Merge Interval Count Trigger Register . . . . . . . . . . . .2-12

2.5.9 Receiver Merge Label Trigger Register. . . . . . . . . . . . . . . . . . .2-13

2.5.10 Receiver Merge Configuration Register . . . . . . . . . . . . . . . . .2-13

2.5.11 Receiver Merge Interrupt Condition Register . . . . . . . . . . . . .2-14

2.5.12 Receiver Merge Status Register . . . . . . . . . . . . . . . . . . . . . . .2-14

3 Transmit Mode

3.1 Transmit Channel Control Register Block Maps . . . . . . . . . . . . . . . . .3-2

3.1.1 Channel 2 Control Register Block Map . . . . . . . . . . . . . . . . . . . .3-2

3.1.2 Channel 5 Control Register Block Map . . . . . . . . . . . . . . . . . . . .3-2

3.2 Transmit Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . .3-3

3.2.1 Channel x Configuration Register . . . . . . . . . . . . . . . . . . . . . . . .3-3

3.2.2 Channel x Transmit Instruction Stack Pointer . . . . . . . . . . . . . . .3-3

3.2.3 Channel x Transmit Instruction Counter . . . . . . . . . . . . . . . . . . .3-4

3.2.4 Channel x Transmit Loop Counter. . . . . . . . . . . . . . . . . . . . . . . .3-4

3.2.5 Channel x Transmit Current Word Register. . . . . . . . . . . . . . . . .3-4

3.2.6 Channel x Transmit Current Loop Register . . . . . . . . . . . . . . . . .3-4

3.2.7 Channel x Interrupt Condition Register . . . . . . . . . . . . . . . . . . . .3-5

3.2.8 Channel x Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5

3.3 Transmit Instruction Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6

3.3.1 Control Word Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7

3.3.2 Word Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7

3.3.3 Interword Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7

3.3.4 Transmit Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7

3.4 Transmit Data Block Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8

4 Receive/ Monitor Mode

4.1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2

4.1.1 Sequential Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2

4.1.2 Look-Up Table Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2

4.1.3 Merge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3

4.2 Sequential/Merge Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3

4.2.1 Receive Buffer Storage Sequence . . . . . . . . . . . . . . . . . . . . . . .4-3

4.2.2 Receive Data Word Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4

4.2.3 Time Tag Word Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5

4.2.4 Receive Sequential Mode Filter Table Diagram . . . . . . . . . . . . .4-6

4.2.5 Receive Sequential Mode Status Word . . . . . . . . . . . . . . . . . . . .4-7

4.2.6 Receive Merge Mode Status Word . . . . . . . . . . . . . . . . . . . . . . .4-7

4.3 Look-up Table Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8

4.3.1 Receive Look-Up Table Storage Sequence . . . . . . . . . . . . . . . .4-8

4.3.2 Receive Look-Up Table Mode Diagram . . . . . . . . . . . . . . . . . . .4-8

4.3.3 Receive Look-Up Table Status/Control Word . . . . . . . . . . . . . . .4-9

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Table of Contents

DAS-429PCI/Mx: User’s Manual page iii

4.4 Receive Channel Control Register Block Maps . . . . . . . . . . . . . . . . .4-10

4.4.1 Channel 0 Control Register Block Map . . . . . . . . . . . . . . . . . . .4-10

4.4.2 Channel 1 Control Register Block Map . . . . . . . . . . . . . . . . . . .4-11

4.4.3 Channel 3 Control Register Block Map . . . . . . . . . . . . . . . . . . .4-12

4.4.4 Channel 4 Control Register Block Map . . . . . . . . . . . . . . . . . . .4-13

4.5 Receive Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . .4-14

4.5.1 Channel x Configuration Register . . . . . . . . . . . . . . . . . . . . . . .4-14

4.5.2 Channel x Receive Data Start Pointer . . . . . . . . . . . . . . . . . . . .4-15

4.5.3 Channel x Receive Data End Pointer . . . . . . . . . . . . . . . . . . . .4-15

4.5.4 Channel x Receive Data Current Pointer . . . . . . . . . . . . . . . . .4-15

4.5.5 Channel x Receive Look-up Table Start Address . . . . . . . . . . .4-15

4.5.6 Channel x Receive Filter Table Start Address. . . . . . . . . . . . . .4-15

4.5.7 Channel x Receive Data Word Count Register . . . . . . . . . . . . .4-16

4.5.8 Channel x Receive Buffer Wraparound Register. . . . . . . . . . . .4-16

4.5.9 Channel x Receive Data Word Counter Trigger Register . . . . .4-16

4.5.10 Channel x Receive Interval Counter Trigger Register . . . . . . .4-16

4.5.11 Channel x Receive Label Trigger Register . . . . . . . . . . . . . . .4-17

4.5.12 Channel x Interrupt Condition Register . . . . . . . . . . . . . . . . . .4-17

4.5.13 Channel x Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-18

5 Mechanical and Electrical Specifications

5.1 Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

5.2 LED Indicators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2

5.3 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2

5.3.1 Connector J1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2

5.3.2 Connector J1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .5-3

5.3.3 Connector J1 Communication I/O Signals Description . . . . . . . .5-4

5.3.4 PCI Bus Edge Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . .5-5

6 Ordering Information

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Table of Contents

page iv Excalibur Systems

Figures

Figure 1-1 DAS-429PCI/Mx Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 1-2 M429R4T2 Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 1-3 DAS-429PCI/Mx Memory Structure. . . . . . . . . . . . . . . . . . . . . . 1-5

Figure 1-4 PCI Configuration Space Header . . . . . . . . . . . . . . . . . . . . . . . 1-6

Figure 2-1 Module M429R4T2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . 2-3

Figure 2-2 Global Registers Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 2-3 Module Control Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Figure 3-1 Channel 2 Control Register Block Map . . . . . . . . . . . . . . . . . . . 3-2

Figure 3-2 Channel 5 Control Register Block Map . . . . . . . . . . . . . . . . . . . 3-2

Figure 3-3 Transmit Instruction Stack Structure . . . . . . . . . . . . . . . . . . . . . 3-6

Figure 3-4 Transmit Data Words memory Format . . . . . . . . . . . . . . . . . . . 3-8

Figure 3-5 Data Bytes In Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Figure 3-6 32-bit ARINC Word Bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Figure 4-1 Receive Sequential Mode Buffer Structure . . . . . . . . . . . . . . . . 4-3

Figure 4-2 Receive Data Word Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Figure 4-3 Receive Word Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Figure 4-4 Time Tag Word Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Figure 4-5 Receive Sequential Mode Filter Table. . . . . . . . . . . . . . . . . . . . 4-6

Figure 4-6 Receive Look-up Table Mode Structure . . . . . . . . . . . . . . . . . . 4-8

Figure 4-7 Channel 0 Control Register Block Map . . . . . . . . . . . . . . . . . . 4-10

Figure 4-8 Channel 1 Control Register Block Map . . . . . . . . . . . . . . . . . . 4-11

Figure 4-9 Channel 3 Control Register Block Map . . . . . . . . . . . . . . . . . . 4-12

Figure 4-10 Channel 4 Control Register Block Map . . . . . . . . . . . . . . . . . . 4-13

Figure 5-1 DAS-429PCI/Mx Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Figure 5-2 Connector J1 Layout (Front View). . . . . . . . . . . . . . . . . . . . . . . 5-2

Tables

Table 1-1 Address nvRAM/EPROM Boot Values . . . . . . . . . . . . . . . . . . . . 1-13

Table 5-1 Connector J1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Table 5-2 Connector J1 Communication I/O Signals Description . . . . . . . . . 5-4

Table 5-3 PCI Bus Edge Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

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Chapter 1 Introduction

DAS-429PCI/Mx: User’s Manual page 1 - 1

1 Introduction

Chapter 1 provides an overview of the DAS-429PCI/Mx avionics communication

board. The following topics are covered:

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2

1.2 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4

1.2.1 Software Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4

1.2.2 Board Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4

1.3 Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

1.4 PCI Configuration Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6

1.5 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

1.5.1 Vendor Identification Register (VID) . . . . . . . . . . . . . . . . . . . . . .1-7

1.5.2 Device Identification Register (DID). . . . . . . . . . . . . . . . . . . . . . .1-7

1.5.3 PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8

1.5.4 PCI Status Register (PCISTS) . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

1.5.5 Revision Identification Register (RID) . . . . . . . . . . . . . . . . . . . .1-10

1.5.6 Class Code Register (CLCD). . . . . . . . . . . . . . . . . . . . . . . . . . .1-10

1.5.7 Cache Line Size Register (CALN) . . . . . . . . . . . . . . . . . . . . . . .1-11

1.5.8 Latency Timer Register (LAT) . . . . . . . . . . . . . . . . . . . . . . . . . .1-11

1.5.9 Header Type Register (HDR). . . . . . . . . . . . . . . . . . . . . . . . . . .1-12

1.5.10 Built-In Self-Test Register (BIST). . . . . . . . . . . . . . . . . . . . . . .1-12

1.5.11 Base Address Registers (BADR) . . . . . . . . . . . . . . . . . . . . . . .1-13

1.5.12 Expansion ROM Base Address Register (XROM). . . . . . . . . .1-15

1.5.13 Interrupt Line Register (INTLN) . . . . . . . . . . . . . . . . . . . . . . . .1-15

1.5.14 Interrupt Pin Register (INTPIN) . . . . . . . . . . . . . . . . . . . . . . . .1-16

1.5.15 Minimum Grant Register (MINGNT) . . . . . . . . . . . . . . . . . . . .1-16

1.5.16 Maximum Latency Register (MAXLAT) . . . . . . . . . . . . . . . . . .1-16

1.6 PCI Global Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-17

1.6.1 PCI Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . .1-17

1.6.2 PCI Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .1-17

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Chapter 1 Introduction

page 1 - 2 Excalibur Systems

1.1 Overview

The DAS-429PCI/Mx is a modular ARINC-429 memory-mapped, multi-channel

(up to 24) test, simulation, and monitor board for PCI systems. The

DAS-429PCI/Mx provides a total solution for developing and testing ARINC-429

interfaces and for performing system simulation of the ARINC-429 bus, both in

the lab and in the field.

The DAS-429PCI/Mx is based on the latest Surface Mount Technology, which

substantially reduces the area required. The DAS-429PCI/Mx comes configured

with 2(x) transmit and 4(x) receive channels (where x = number of modules

ordered). The channels are organized in four independent modules (P/N:

M429R4T2), each configured with 4 receive and 2 transmit channels. Each

module contains an on board hi-speed controller and 16K x 16 true

dual-port RAM. Each module is accessed through a paging mechanism and

operates independently. Each module can be set up to generate interrupts to the

host in a variety of circumstances through an extensive interrupt structure. Both

transmit and receive channels may be programmed for Hi (100Khz) or Lo

(12.5Khz) speed bit rates. In addition, either odd or even parity may be

programmed for transmit channels.

All control registers and data blocks can be accessed directly in real time. The

board supports filtering of receive data and multiple data storage modes. Status

and time tag information are appended to each word. The transmit channels

operate via a transmitter “instruction” stack which allows scheduling of data

transmissions and reduces the need for host computer intervention. The

DAS-429PCI/Mx comes complete with C driver software libraries, including

source code.

The DAS-429PCI/Mx is ideally suited for developing, simulating, testing and

monitoring ARINC-429 interfaces for multi-channel applications requiring a

single PCI board.

DAS-429PCI/Mx Board Features:

See Chapter 6: Ordering Information for exact part numbers.

Up to 24 ARINC-429 channels (Receive and

Transmit)

Eurocard 3U size

Compatible with PCI computers

Easy to install and operate

Organized in 4 modules, each containing:

4 Receive channels

2 Transmit channels

16k ×16 true dual-port RAM

On board 32 bit processor

12.5Khz bit and 100Khz bit data rates

Selectable even/odd parity

Programmable interword gap

Real time operation

Transmission modes:

One-shot

Loop

N-times

Two Receive/Monitor modes:

Sequential

Look-up table

32 bit time tagging per word

Merge mode stores data from multiple receive

channels in one buffer

Label filtering

Start triggers

Receive count interval triggers

Interrupt and polling modes of operation

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Chapter 1 Introduction

DAS-429PCI/Mx: User’s Manual page 1 - 3

Figure 1-1 below illustrates the DAS-429PCI/Mx’s block diagram

Figure 1-1 DAS-429PCI/Mx Block Diagram

Figure 1-2 below illustrates the block diagram of a single M429R4T2 module.

Figure 1-2 M429R4T2 Module Block Diagram

PCI

BUS

CNTRL

ADDR/DATA

20 MHz

PCI

INTERFACE

CONTROLLER

ARINC-429

CONNECTIONS

ARINC-429

MODULE #0

(M429R4T2)

ARINC-429

MODULE #1

(M429R4T2)

ARINC-429

MODULE #2

(M429R4T2)

ARINC-429

MODULE #3

(M429R4T2)

RX0(i)*

TX0(j)**

RX1(i)

TX1(j)

RX2(i)

TX2(j)

RX3(i)

TX3(j)

40 MHz

OSC

* i - Receive channel index (0,1,3,4)

** j - Transmit channel index (2,5)

LOCAL

BUS

20MHz

ADDR/

DATA

CNTRL

MC68340

Micro-

Controller

Local Bus

Interface

RX3

RX4

TX5

16K x 16

Dual Port

RAM

128K x 16

Program

RAM

128K x 8

Boot

Flash

ENC/DEC

Logic

Block

FPGA

ARINC-429

DRIVER

ARINC-429

DRIVER ARINC-429

CHANNELS

RX0

RX1

TX2

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