Excalibur Excalibur EPXA1 Kurzanleitung

MNL-EPXA1DEVBD-1.1

EPXA1 Development Board

101 Innovation Drive

San Jose, CA 95134

(408) 544-7000

http://www.altera.com

Hardware Reference Manual

September 2002

Version 1.1

ii Altera Corporation

EPXA1 Development Board Hardware Reference Manual

Copyright 2002 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all

other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera

Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera

products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.

Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty,

but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or

liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to

in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on

Altera Corporation iii

About this Manual

This manual provides comprehensive information about the Altera®

EPXA1 development board.

Table 1 shows the manual revision history.

How to Find

Information

■The Adobe Acrobat Find feature allows you to search the contents of

a PDF file. Click on the binoculars icon in the top toolbar to open the

Find dialog box.

■Bookmarks serve as an additional table of contents.

■Thumbnail icons, which provide miniature previews of each page,

provide a link to the pages.

■Numerous links, shown in green text, allow you to jump to related

information.

Table 1. Revision History

Date Description

August 2002 First publication

September 2002 Minor amendments

iv Altera Corporation

About this Manual EPXA1 Development Board Hardware Reference Manual

How to Contact

Altera

For the most up-to-date information about Altera products, go to the

Altera world-wide web site at http://www.altera.com.

For technical support on this product, go to

http://www.altera.com/mysupport. For additional information about

Altera products, consult the sources shown in Table 2.

Note:

(1) You can also contact your local Altera sales office or sales representative.

Table 2. How to Contact Altera

Information Type USA & Canada All Other Locations

Technical support http://www.altera.com/mysupport/ http://www.altera.com/mysupport/

(800) 800-EPLD (3753)

(7:00 a.m. to 5:00 p.m.

Pacific Time)

(408) 544-7000 (1)

(7:00 a.m. to 5:00 p.m.

Pacific Time)

Product literature http://www.altera.com http://www.altera.com

Altera literature services lit_req@altera.com (1) lit_req@altera.com (1)

Non-technical customer

service

(800) 767-3753 (408) 544-7000

(7:30 a.m. to 5:30 p.m.

Pacific Time)

FTP site ftp.altera.com ftp.altera.com

Altera Corporation v

EPXA1 Development Board Hardware Reference Manual About this Manual

Typographic

Conventions

The EPXA1 Development Board Hardware Reference Manual uses the

typographic conventions shown in Table 3.

Table 3. Conventions

Visual Cue Meaning

Bold Type with Initial

Capital Letters

Command names, dialog box titles, checkbox options, and dialog box options are

shown in bold, initial capital letters. Example: Save As dialog box.

bold type External timing parameters, directory names, project names, disk drive names,

filenames, filename extensions, and software utility names are shown in bold type.

Examples: fMAX, \QuartusII directory, d: drive, chiptrip.gdf file.

Bold italic type Book titles are shown in bold italic type with initial capital letters. Example:

1999 Device Data Book.

Italic Type with Initial

Capital Letters

Document titles are shown in italic type with initial capital letters. Example: AN 75

(High-Speed Board Design).

Italic type Internal timing parameters and variables are shown in italic type. Examples: tPIA, n+ 1.

Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:

<file name>, <project name>.pof file.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:

Delete key, the Options menu.

“Subheading Title” References to sections within a document and titles of Quartus II Help topics are

shown in quotation marks. Example: “Configuring a FLEX 10K or FLEX 8000 Device

with the BitBlaster™Download Cable.”

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,

input. Active-low signals are denoted by suffix _n, e.g., reset_n.

Anything that must be typed exactly as it appears is shown in Courier type. For

example: c:\quartusII\qdesigns\tutorial\chiptrip.gdf. Also, sections

of an actual file, such as a Report File, references to parts of files (e.g., the AHDL

keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in

Courier.

1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is

important, such as the steps listed in a procedure.

■Bullets are used in a list of items when the sequence of the items is not important.

The checkmark indicates a procedure that consists of one step only.

The hand points to information that requires special attention.

The angled arrow indicates you should press the Enter key.

The feet direct you to more information on a particular topic.

Notes:

Altera Corporation vii

Contents

About this Manual ..................................................................................iii

How to Find Information ............................................................................................................iii

How to Contact Altera .................................................................................................................. iv

Typographic Conventions ............................................................................................................. v

EPXA1 Development Board ........................................................................9

Features .............................................................................................................................................9

Functional Overview .......................................................................................................................9

EPXA1 Development Board Components .................................................................................10

EPXA1 Device .........................................................................................................................10

Prototyping Area ....................................................................................................................11

Interfaces .................................................................................................................................13

Development Board Expansion ...........................................................................................20

Jumper Configuration ...................................................................................................................23

Clocks ...............................................................................................................................................24

Jumper Configuration for the Clock Inputs .......................................................................26

Sources for the Stripe Clock Reference ...............................................................................27

Sources for CLK3 & CLK4 ....................................................................................................28

Device Configuration ....................................................................................................................28

Booting from Flash Memory ................................................................................................28

Using the Quartus II Software .............................................................................................29

JTAG Interfaces ..............................................................................................................................29

Power Supply .................................................................................................................................30

Test Points & Test Pads .................................................................................................................32

Signals ..............................................................................................................................................33

UART .......................................................................................................................................33

Expansion Headers ................................................................................................................34

Configuration/Debugging Interfaces .................................................................................37

Development Board Pin-Outs ......................................................................................................38

Configuration .........................................................................................................................39

SDR SDRAM Interface ..........................................................................................................40

EBI ............................................................................................................................................42

UART1 & UART2 ...................................................................................................................44

Fast I/O Pins ...........................................................................................................................44

Test Points ...............................................................................................................................45

Test Pads ..................................................................................................................................45

Prototyping Area ....................................................................................................................46

Expansion Header I/O Pins .................................................................................................47

General Usage Guidelines ............................................................................................................48

viii Altera Corporation

Contents Excalibur EPXA1 Development Board Hardware Refewrence Manual

Anti-Static Handling ..............................................................................................................48

Power Consumption ..............................................................................................................48

Test Core Functionality .........................................................................................................49

Unused I/O Pins ....................................................................................................................50

Altera Corporation 9

Specifications

EPXA1 Development Board

Features ■Powerful development board for embedded processor FPGA designs

–Features an EPXA1F484 device

–Supports intellectual property-based (IP-based) designs using a

microprocessor

■Industry-standard interconnections

–10/100 megabits per second (Mbps) Ethernet

–Two RS-232 ports

■Memory subsystem

–8 Mbytes of flash memory

–32 Mbytes of single data rate (SDR) SDRAM

■Multiple clocks for communications system design

■Multiple ports for configuration and debugging

–IEEE Std. 1149.1 Joint Test Action Group (JTAG)

–Support for configuring the EPXA1 device using flash memory,

with a MasterBlaster™or ByteBlasterMV™cable

–Multi-ICE header for debugging

■Expansion headers for greater flexibility and capacity

–5-V standard expansion header

–5-V long expansion card header

■Additional user-interface features

–One user-definable 8-bit dual in-line package (DIP) switch block

–Four user-definable push-button switches, plus reset switch

–Ten user-definable LEDs, plus function-specific LEDs

■Test points provided to facilitate system development

Functional

Overview

The EPXA1 development board is a powerful, low-cost, product which

you can use as a desktop hardware platform to start developing

embedded systems immediately. In addition, the board can be used for

system prototyping, emulation, hardware and software development or

other special requirements. The development board provides a flexible,

powerful debug and development environment to support the

development of systems using Excalibur™devices.

10 Altera Corporation

EPXA1 Development Board Hardware Reference Manual

EPXA1

Development

Board

Components

This section describes the components on the EPXA1 development board,

which is shown in Figure 1.

Figure 1. EPXA1 Development Board Layout

EPXA1 Device

The EPXA1 development board features the lowest-cost member of the

Excalibur family, the EPXA1. The EPXA1 device contains an ARM922T™

32-bit RISC microprocessor combined with an APEX™20KE FPGA in a

484-pin FineLine BGA™package.

Table 1 on page 10 lists the main features of the device.

Table 1. EPXA1 Device Features

Feature Capacity

Maximum system gates 263,000

Typical gates 100,000

LEs 4,160

ESBs 26

Maximum RAM bits 53,248

Maximum macrocells 416

Maximum user I/O pins 186

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