3.3.4 Reprogramming of user FPGA configuration............................................................................. 41
4
Transportation, unpacking and storage............................................................................................ 43
4.1 Transportation............................................................................................................................................. 43
4.2 Unpacking................................................................................................................................................... 43
4.3 Storage....................................................................................................................................................... 43
ANNEX A DISCLAIMER………………………………………………………………………………………………………………..44
LIST OF TABLES
Table 1-1: Ordering information ……………………………………………………………………….………………........................11
Table 1-2: Delivery checklist……………………………………………………………………………………………………………..12
Table 1-3: Additional accessories……………………………………………………………………………………………………….12
Table 2-1: Identification of ISA bus contacts, row A…………………………………………………………………………………..17
Table 2-2: Identification of ISA bus contacts, row B…………………………………………………………………………………..18
Table 2.3: XP10 connector contacts ……………………………………………………………………………………………………19
Table 2-4: Table of XP11 connector contacts………………………………………………………………………………………….23
Table 3-1: SA1 switch setting……………………………………………………………………………………………………………29
Table 3-2: Type of inputs…………………………………………………………………………………………………………………31
Table 3-3: Trigger threshold per each group of eight input channels……………………………………………………………….32
Table 3-4: Setting the load type connection……………………………………………………………………………………………33
Table 3-5: Control register……………………………………………………………………………………………………………….35
Table 3-6: Event front edge codes for groups of inputs………………………………………………………………………………36
Table 3-7: De-bouncing time codes for groups of inputs……………………………………………………………………………..36
Table 3-8: Control register……………………………………………………………………………………………………………….36
Table 3-9: Register of interrupts…………………………………………………………………………………………………………36
Table 3-10: Register of inputs……………………………………………………………………………………………………………37
Table 3-11: Register of events…………………………………………………………………………………………………………..37
Table 3-12: Control register……………………………………………………………………………………………………………...38
Table 3-13: Register of data……………………………………………………………………………………………………………..38
Table 3-14: Register of outputs………………………………………………………………………………………………………….40
Table 3-15: Port (BA+Eh) through reading……………………………………………………………………………………………..40
Table 3-16: Port (BA+Fh) through reading……………………………………………………………………………………………..40
LIST OF FIGURES
Fig. 1-1: External view of DIC324……………………………………………………………………………………………………….13
Fig. 1-2: Overall dimensions and location of main components of DIC324………………………………………………………...14
Fig. 2-1: Block diagram of DIC324………………………………………………………………………………………………………15
Fig. 2-2: Location of the SA1 base address switch……………………………………………………………………………………16
Fig. 2-3: Numbering of XS4 connector contacts……………………………………………………………………………………….18
Fig. 2-4: Digital input connector………………………………………………………………………………………………………….19
Fig. 2-5: Diagram of DIC324 input channel…………………………………………………………………………………………….20
Fig. 2-6: Connection type jumpers………………………………………………………………………………………………………20
Fig. 2-7: XP12 jumper…………………………………………………………………………………………………………………….21
Fig. 2-8: Digital output connector………………………………………………………………………………………………………..21
Fig. 2-9: Diagram of the connector's ports' outputs……………………………………………………………………………………22
Fig. 2-10: Input channel 1 diagram……………………………………………………………………………………………………...24
Fig. 2-11: SA1 base address setting switch…………………………………………………………………………………………....24
Fig. 3-1: SA1 base address setting switch…………………………………………………………………………………………......27
Fig. 3-2: Connection to the module……………………………………………………………………………………………………..30
Fig. 3-3: Matrix diagram…………………………………………………………………………………………………………………..35
Fig. 3-4: Integrated parts of the block-diagram………………………………………………………………………………………...39
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