Freescale Semiconductor E200z3 Bedienungsanleitung

e200z3 Power Architecture™

Core Reference Manual

Supports

e200z3

e200z335

e200z3coreRM

Rev. 2

06/2008

Freescale, the Freescale logo, and StarCore and the Freescale logo are

trademarks or registered trademarks of Freescale Semiconductor, Inc. in

the U.S. and other countries. All other product or service names are the

property of their respective owners. HyperTransport is a trademark of the

HyperTransport Technology Consortium. The Power Architecture and

Power.org word marks and the Power and Power.org logos and related

marks are trademarks and service marks licensed by Power.org. The

PowerPC name is a trademark of IBM Corp. and is used under license.

RapidIO is a registered trademark of the RapidIO Trade Association. IEEE

nnn, nnn, and nnn are trademarks or registered trademarks of the Institute

of Electrical and Electronics Engineers, Inc. (IEEE). This product is not

endorsed or approved by the IEEE.

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale Semiconductor assume any liability arising out of the application or use of

any product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters which may be

provided in Freescale Semiconductor data sheets and/or specifications can and do

vary in different applications and actual performance may vary over time. All operating

parameters, including “Typicals” must be validated for each customer application by

customer’s technical experts. Freescale Semiconductor does not convey any license

under its patent rights nor the rights of others. Freescale Semiconductor products are

not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in which the failure of the Freescale Semiconductor product

could create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs, damages, and expenses, and reasonable attorney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Freescale

Semiconductor was negligent regarding the design or manufacture of the part.

Document Number: e200z3coreRM

Rev. 2, 06/2008

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

USA/Europe or Locations Not Listed:

Freescale Semiconductor, Inc.

Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284

+1-800-521-6274 or

+1-480-768-2130

www.freescale.com/support

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

www.freescale.com/support

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku

Tokyo 153-0064

Japan

0120 191014 or

+81 3 5437 9125

support.japan@freescale.com

Asia/Pacific:

Freescale Semiconductor China Ltd.

Exchange Building 23F

No. 118 Jianguo Road

Chaoyang District

Beijing 100022

China

+86 010 5879 8000

support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor

Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

+1-800 441-2447 or

+1-303-675-2140

Fax: +1-303-675-2150

LDCForFreescaleSemiconductor

@hibbertgroup.com

e200z3 Power Architecture Core Reference Manual, Rev. 2

Freescale Semiconductor iii

Contents

Paragraph

Number Title

Page

Number

General Information......................................................................................................... viii

Related Documentation...................................................................................................... ix

Terminology Conventions....................................................................................................x

Acronyms and Abbreviations ..............................................................................................x

Chapter 1

e200z335 Core Complex Overview

1.1 Overview of the e200z3 and e200z335............................................................................1-1

1.1.1 Features........................................................................................................................1-4

1.2 Programming Model........................................................................................................ 1-5

1.2.1 Register Set.................................................................................................................. 1-5

1.3 Instruction Set..................................................................................................................1-7

1.4 VLE Category..................................................................................................................1-8

1.5 Interrupts and Exception Handling.................................................................................. 1-8

1.5.1 Interrupt Handling........................................................................................................ 1-9

1.5.2 Interrupt Classes ..........................................................................................................1-9

1.5.3 Interrupt Types........................................................................................................... 1-10

1.5.4 Interrupt Registers...................................................................................................... 1-10

1.6 Microarchitecture Summary .......................................................................................... 1-12

1.6.1 Instruction Unit Features ........................................................................................... 1-13

1.6.2 Integer Unit Features ................................................................................................. 1-13

1.6.3 Load/Store Unit (LSU) Features................................................................................ 1-13

1.6.4 Memory Management Unit (MMU) Features ...........................................................1-14

1.6.5 System Bus (Core Complex Interface) Features........................................................ 1-14

1.6.6 Nexus 32+ Module Features...................................................................................... 1-14

1.7 Legacy Support of PowerPC Architecture..................................................................... 1-14

1.7.1 Instruction Set Compatibility..................................................................................... 1-15

1.7.1.1 User Instruction Set ............................................................................................... 1-15

1.7.1.2 Supervisor Instruction Set...................................................................................... 1-15

1.7.2 Memory Subsystem ................................................................................................... 1-15

1.7.3 Interrupt Handling...................................................................................................... 1-15

1.7.4 Memory Management................................................................................................ 1-16

1.7.5 Reset........................................................................................................................... 1-16

1.7.6 Little-Endian Mode.................................................................................................... 1-16

e200z3 Power Architecture Core Reference Manual, Rev. 2

iv Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

Chapter 2

2.1 PowerPC Book E Registers ............................................................................................. 2-4

2.2 e200z3-Specific Registers................................................................................................ 2-6

2.3 e200z3-Specific Device Control Registers...................................................................... 2-7

2.4 Processor Control Registers............................................................................................. 2-7

2.4.1 Machine State Register (MSR).................................................................................... 2-7

2.4.2 Processor ID Register (PIR) ........................................................................................ 2-9

2.4.3 Processor Version Register (PVR)............................................................................. 2-10

2.4.4 System Version Register (SVR)................................................................................. 2-10

2.5 Registers for Integer Operations.................................................................................... 2-11

2.5.1 General-Purpose Registers (GPRs)............................................................................ 2-11

2.5.2 Integer Exception Register (XER)............................................................................. 2-11

2.6 Registers for Branch Operations.................................................................................... 2-12

2.6.1 Condition Register (CR)............................................................................................ 2-12

2.6.1.1 CR Setting for Integer Instructions........................................................................ 2-14

2.6.1.2 CR Setting for Store Conditional Instructions.......................................................2-14

2.6.1.3 CR Setting for Compare Instructions .................................................................... 2-14

2.6.2 Count Register (CTR)................................................................................................ 2-15

2.6.3 Link Register (LR)..................................................................................................... 2-15

2.7 SPE and SPFP APU Registers....................................................................................... 2-16

2.7.1 Signal Processing/Embedded Floating-Point Status and Control

2.7.2 Accumulator (ACC)................................................................................................... 2-19

2.8 Interrupt Registers..........................................................................................................2-19

2.8.1 Interrupt Registers Defined by Book E...................................................................... 2-19

2.8.1.1 Save/Restore Register 0 (SRR0)............................................................................ 2-20

2.8.1.2 Save/Restore Register 1 (SRR1)............................................................................ 2-20

2.8.1.3 Critical Save/Restore Register 0 (CSRR0)............................................................2-20

2.8.1.4 Critical Save/Restore Register 1 (CSRR1)............................................................2-21

2.8.1.5 Data Exception Address Register (DEAR)............................................................ 2-21

2.8.1.6 Interrupt Vector Prefix Register (IVPR)................................................................ 2-21

2.8.1.7 Interrupt Vector Offset Registers (IVORs)............................................................ 2-22

2.9 Exception Syndrome Register (ESR) ............................................................................2-23

2.9.1 VLE Mode Instruction Syndrome..............................................................................2-25

2.9.2 Misaligned Instruction Fetch Syndrome.................................................................... 2-25

2.9.3 Precise External Termination Error Syndrome..........................................................2-25

2.9.4 e200z3-Specific Interrupt Registers........................................................................... 2-26

2.9.4.1 Debug Save/Restore Register 0 (DSRR0)............................................................. 2-26

2.9.4.2 Debug Save/Restore Register 1 (DSRR1)............................................................. 2-26

e200z3 Power Architecture Core Reference Manual, Rev. 2

Freescale Semiconductor v

Contents

Paragraph

Number Title

Page

Number

2.9.4.3 Machine Check Syndrome Register (MCSR)........................................................ 2-26

2.10 Software-Use SPRs (SPRG0–SPRG7 and USPRG0) ................................................... 2-27

2.11 Timer Registers..............................................................................................................2-28

2.11.1 Timer Control Register (TCR)................................................................................... 2-29

2.11.2 Timer Status Register (TSR)...................................................................................... 2-30

2.11.3 Time Base (TBU and TBL) ....................................................................................... 2-31

2.11.4 Decrementer Register ................................................................................................ 2-33

2.11.5 Decrementer Auto-Reload Register (DECAR)..........................................................2-33

2.12 Debug Registers.............................................................................................................2-34

2.12.1 Debug Address and Value Registers.......................................................................... 2-34

2.12.1.1 Instruction Address Compare Registers (IAC1–IAC4).........................................2-34

2.12.1.2 Data Address Compare Registers (DAC1–DAC2)................................................ 2-35

2.12.1.3 Data Value Compare Registers (DVC1–DVC2) (e200z335 only) ........................ 2-35

2.12.2 Debug Counter Register (DBCNT) ........................................................................... 2-36

2.12.3 Debug Control and Status Registers (DBCR0–DBCR3)...........................................2-36

2.12.3.1 Debug Control Register 0 (DBCR0)...................................................................... 2-36

2.12.3.2 Debug Control Register 1 (DBCR1)...................................................................... 2-39

2.12.3.3 Debug Control Register 2 (DBCR2)...................................................................... 2-41

2.12.3.4 Debug Control Register 3 (DBCR3)...................................................................... 2-43

2.12.3.5 Debug Control Register 4 (DBCR4) (e200z335 only)..........................................2-48

2.12.4 Debug Status Register (DBSR).................................................................................. 2-49

2.12.5 Debug External Resource Control Register (DBERC0)............................................ 2-50

2.13 Hardware Implementation-Dependent Registers........................................................... 2-57

2.13.1 Hardware Implementation-Dependent Register 0 (HID0).........................................2-57

2.13.2 Hardware Implementation-Dependent Register 1 (HID1).........................................2-59

2.14 Branch Target Buffer (BTB) Registers.......................................................................... 2-61

2.14.1 Branch Unit Control and Status Register (BUCSR)..................................................2-61

2.15 L1 Cache Configuration Registers................................................................................. 2-61

2.15.1 L1 Cache Configuration Register 0 (L1CFG0) .........................................................2-61

2.16 MMU Registers.............................................................................................................. 2-62

2.16.1 MMU Control and Status Register 0 (MMUCSR0).................................................. 2-62

2.16.2 MMU Configuration Register (MMUCFG) .............................................................. 2-62

2.16.3 TLB Configuration Registers (TLBnCFG)................................................................ 2-63

2.16.3.1 TLB Configuration Register 0 (TLB0CFG)..........................................................2-63

2.16.3.2 TLB Configuration Register 1 (TLB1CFG)..........................................................2-64

2.16.4 MMU Assist Registers (MAS0–MAS4, MAS6)....................................................... 2-65

2.16.5 Process ID Register (PID0)........................................................................................ 2-69

2.17 Support for Fast Context Switching...............................................................................2-69

2.17.1 Context Control Register (CTXCR) .......................................................................... 2-70

2.18 SPR Register Access...................................................................................................... 2-70

2.18.1 Invalid SPR References ............................................................................................. 2-70

e200z3 Power Architecture Core Reference Manual, Rev. 2

vi Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

2.18.2 Synchronization Requirements for SPRs................................................................... 2-70

2.18.3 Special-Purpose Register Summary........................................................................... 2-71

2.18.4 Reset Settings............................................................................................................. 2-74

2.19 Parallel Signature Unit Registers................................................................................... 2-76

2.19.1 Parallel Signature Control Register (PSCR).............................................................. 2-77

2.19.2 Parallel Signature Status Register (PSSR)................................................................. 2-78

2.19.3 Parallel Signature High Register (PSHR).................................................................. 2-78

2.19.4 Parallel Signature Low Register (PSLR)................................................................... 2-79

2.19.5 Parallel Signature Counter Register (PSCTR)...........................................................2-79

2.19.6 Parallel Signature Update High Register (PSUHR) .................................................. 2-80

2.19.7 Parallel Signature Update Low Register (PSULR).................................................... 2-80

Chapter 3

Instruction Model

3.1 Operand Conventions ...................................................................................................... 3-1

3.1.1 Data Organization in Memory and Data Transfers...................................................... 3-1

3.1.2 Alignment and Misaligned Accesses........................................................................... 3-1

3.1.3 e200z3 Floating-Point Implementation ....................................................................... 3-2

3.2 Unsupported Instructions and Instruction Forms.............................................................3-2

3.3 Optionally Supported Instructions and Instruction Forms...............................................3-2

3.4 Implementation-Specific Instructions.............................................................................. 3-3

3.5 BookE Instruction Extensions ......................................................................................... 3-3

3.6 Memory Access Alignment Support................................................................................ 3-4

3.7 Memory Synchronization and Reservation Instructions.................................................. 3-4

3.8 Branch Prediction ............................................................................................................3-5

3.9 Interruption of Instructions by Interrupt Requests........................................................... 3-5

3.10 e200z3-Specific Instructions............................................................................................ 3-6

3.10.1 Integer Select APU ...................................................................................................... 3-6

3.10.2 Debug APU..................................................................................................................3-6

3.10.3 Wait APU (e200z335 only).......................................................................................... 3-6

3.10.4 Volatile Context Save/Restore APU (e200z335 only).................................................3-7

3.10.5 SPE APU Instructions.................................................................................................. 3-7

3.10.6 Embedded Vector and Scalar Single-Precision Floating-Point APU

Instructions ............................................................................................................ 3-15

3.10.6.1 Options for Embedded Floating-Point APU Implementations.............................. 3-16

3.11 Unimplemented SPRs and Read-Only SPRs................................................................. 3-16

3.12 Invalid Instruction Forms............................................................................................... 3-17

3.13 Instruction Summary...................................................................................................... 3-17

3.13.1 Instruction Index Sorted by Mnemonic..................................................................... 3-18

3.13.2 Instruction Index Sorted by Opcode.......................................................................... 3-29

e200z3 Power Architecture Core Reference Manual, Rev. 2

Freescale Semiconductor vii

Contents

Paragraph

Number Title

Page

Number

Chapter 4

Interrupts and Exceptions

4.1 Overview.......................................................................................................................... 4-1

4.2 e200z3 Interrupts ............................................................................................................. 4-2

4.3 Exception Syndrome Register (ESR) ..............................................................................4-4

4.4 Machine State Register (MSR)........................................................................................ 4-5

4.4.1 Machine Check Syndrome Register (MCSR).............................................................. 4-7

4.4.1.1 Interrupt Vector Prefix Register (IVPR).................................................................. 4-8

4.5 Interrupt Vector Offset Registers (IVORn)...................................................................... 4-8

4.6 Interrupt Definitions ...................................................................................................... 4-10

4.6.1 Critical Input Interrupt (IVOR0)................................................................................ 4-10

4.6.2 Machine Check Interrupt (IVOR1)............................................................................ 4-11

4.6.2.1 Machine Check Interrupt Enabled (MSR[ME]=1)................................................ 4-11

4.6.2.2 Checkstop State ..................................................................................................... 4-12

4.6.2.3 Non-Maskable Interrupts (NMI) (e200z335 only)................................................ 4-13

4.6.3 Data Storage Interrupt (IVOR2) ................................................................................ 4-13

4.6.4 Instruction Storage Interrupt (IVOR3) ...................................................................... 4-14

4.6.5 External Input Interrupt (IVOR4).............................................................................. 4-15

4.6.6 Alignment Interrupt (IVOR5).................................................................................... 4-16

4.6.7 Program Interrupt (IVOR6) ....................................................................................... 4-16

4.6.8 Floating-Point Unavailable Interrupt (IVOR7).......................................................... 4-17

4.6.9 System Call Interrupt (IVOR8).................................................................................. 4-18

4.6.10 Auxiliary Processor Unavailable Interrupt (IVOR9).................................................4-18

4.6.11 Decrementer Interrupt (IVOR10) .............................................................................. 4-19

4.6.12 Fixed-Interval Timer Interrupt (IVOR11).................................................................. 4-19

4.6.13 Watchdog Timer Interrupt (IVOR12) ........................................................................ 4-20

4.6.14 Data TLB Error Interrupt (IVOR13) ......................................................................... 4-21

4.6.15 Instruction TLB Error Interrupt (IVOR14)................................................................ 4-21

4.6.16 Debug Interrupt (IVOR15) ........................................................................................ 4-22

4.6.17 System Reset..............................................................................................................4-25

4.6.18 SPE APU Unavailable Interrupt (IVOR32)............................................................... 4-26

4.6.19 SPE Floating-Point Data Interrupt (IVOR33) ...........................................................4-27

4.6.20 SPE Floating-Point Round Interrupt (IVOR34) ........................................................ 4-27

4.7 Exception Recognition and Priorities ............................................................................ 4-28

4.7.1 Interrupt Priorities...................................................................................................... 4-29

4.8 Interrupt Processing....................................................................................................... 4-32

4.8.1 Enabling and Disabling Exceptions........................................................................... 4-33

4.8.2 Returning from an Interrupt Handler......................................................................... 4-33

4.9 Process Switching.......................................................................................................... 4-34

e200z3 Power Architecture Core Reference Manual, Rev. 2

viii Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

Chapter 5

Memory Management Unit

5.1 Overview.......................................................................................................................... 5-1

5.1.1 MMU Features............................................................................................................. 5-1

5.1.2 TLB Entry Maintenance Features Summary ............................................................... 5-1

5.2 Effective-to-Real Address Translation............................................................................. 5-2

5.2.1 Effective Addresses ..................................................................................................... 5-4

5.2.2 Address Spaces ............................................................................................................ 5-4

5.2.3 Virtual Addresses and Process ID................................................................................ 5-4

5.2.4 Translation Flow.......................................................................................................... 5-5

5.2.5 Permissions..................................................................................................................5-6

5.3 Translation Lookaside Buffer .......................................................................................... 5-7

5.3.1 IPROT Invalidation Protection in TLB1 ..................................................................... 5-8

5.3.2 Replacement Algorithm for TLB1............................................................................... 5-8

5.3.3 The G Bit (of WIMGE) ............................................................................................... 5-9

5.3.4 TLB Entry Field Summary.......................................................................................... 5-9

5.4 Software Interface and TLB Instructions....................................................................... 5-10

5.5 TLB Operations ............................................................................................................. 5-11

5.5.1 Translation Reload..................................................................................................... 5-11

5.5.2 Reading the TLB........................................................................................................ 5-12

5.5.3 Writing the TLB......................................................................................................... 5-12

5.5.4 Searching the TLB..................................................................................................... 5-12

5.5.5 TLB Coherency Control ............................................................................................ 5-12

5.5.6 TLB Miss Exception Update ..................................................................................... 5-12

5.5.7 TLB Load on Reset.................................................................................................... 5-13

5.6 MMU Configuration and Control Registers.................................................................. 5-13

5.6.1 MMU Configuration Register (MMUCFG) .............................................................. 5-13

5.6.2 TLB0 and TLB1 Configuration Registers ................................................................. 5-14

5.6.3 Data Exception Address Register (DEAR)................................................................ 5-14

5.6.4 MMU Control and Status Register 0 (MMUCSR0)..................................................5-14

5.6.5 MMU Assist Registers (MAS) .................................................................................. 5-14

5.6.5.1 MAS Registers Summary ...................................................................................... 5-14

5.6.5.2 MAS Register Updates .......................................................................................... 5-14

5.7 Effect of Hardware Debug on MMU Operation............................................................5-15

Chapter 6

Instruction Pipeline and Execution Timing

6.1 Overview of Operation .................................................................................................... 6-1

6.1.1 Control Unit.................................................................................................................6-2

e200z3 Power Architecture Core Reference Manual, Rev. 2

Freescale Semiconductor ix

Contents

Paragraph

Number Title

Page

Number

6.1.2 Instruction Unit............................................................................................................ 6-2

6.1.3 Branch Unit..................................................................................................................6-3

6.1.4 Instruction Decode Unit............................................................................................... 6-3

6.1.5 Exception Handling ..................................................................................................... 6-3

6.2 Execution Units................................................................................................................6-3

6.2.1 Integer Execution Unit................................................................................................. 6-3

6.2.2 Load/Store Unit............................................................................................................6-3

6.3 Instruction Pipeline.......................................................................................................... 6-4

6.3.1 Description of Pipeline Stages..................................................................................... 6-4

6.3.2 Instruction Buffers ....................................................................................................... 6-5

6.3.3 Single-Cycle Instruction Pipeline Operation ............................................................... 6-7

6.3.4 Basic Load and Store Instruction Pipeline Operation..................................................6-8

6.3.5 Change-of-Flow Instruction Pipeline Operation..........................................................6-9

6.3.6 Basic Multi-Cycle Instruction Pipeline Operation..................................................... 6-10

6.3.7 Additional Examples of Instruction Pipeline Operation for Load and Store.............6-10

6.3.8 Move to/from SPR Instruction Pipeline Operation.................................................... 6-11

6.4 Stalls Caused by Accessing SPRs.................................................................................. 6-13

6.5 Instruction Serialization................................................................................................. 6-13

6.6 Interrupt Recognition and Exception Processing...........................................................6-14

6.7 Instruction Timings........................................................................................................ 6-16

6.7.1 SPE and Embedded Floating-Point Instruction Timing.............................................6-21

6.7.1.1 SPE Integer Simple Instructions Timing ............................................................... 6-22

6.7.1.2 SPE Load and Store Instruction Timing................................................................6-23

6.7.1.3 SPE Complex Integer Instruction Timing .............................................................6-24

6.7.1.4 Vector Floating-Point APU Instruction Timing.....................................................6-27

6.7.1.5 SPE Scalar Floating-Point Instruction Timing ......................................................6-28

6.8 Operand Placement on Performance.............................................................................. 6-29

Chapter 7

External Core Complex Interfaces

7.1 Overview.......................................................................................................................... 7-1

7.2 Signal Index.....................................................................................................................7-2

7.3 Signal Descriptions..........................................................................................................7-7

7.3.1 Processor State Signals.............................................................................................. 7-20

7.3.2 JTAG ID Signals........................................................................................................ 7-29

7.4 Internal Signals ..............................................................................................................7-30

7.5 Timing Diagrams ........................................................................................................... 7-30

7.5.1 Processor Instruction/Data Transfers......................................................................... 7-30

7.5.1.1 Basic Read Transfer Cycles................................................................................... 7-32

7.5.1.2 Read Transfer with Wait State ............................................................................... 7-33

e200z3 Power Architecture Core Reference Manual, Rev. 2

xFreescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

7.5.1.3 Basic Write Transfer Cycles .................................................................................. 7-34

7.5.1.4 Write Transfer with Wait States............................................................................. 7-35

7.5.1.5 Read and Write Transfers ...................................................................................... 7-36

7.5.1.6 Misaligned Accesses.............................................................................................. 7-39

7.5.2 Burst Accesses........................................................................................................... 7-43

7.5.3 Address Retraction..................................................................................................... 7-49

7.5.3.1 Error Termination Operation ................................................................................. 7-51

7.5.4 Address Retraction..................................................................................................... 7-55

7.5.5 Power Management ................................................................................................... 7-57

7.5.6 Interrupt Interface ...................................................................................................... 7-58

Chapter 8

Power Management

8.1 Overview.......................................................................................................................... 8-1

8.1.1 Power Management Signals......................................................................................... 8-2

8.1.2 Power Management Control Bits................................................................................. 8-3

8.1.3 Software Considerations for Power Management.......................................................8-3

8.1.4 Debug Considerations for Power Management...........................................................8-3

Chapter 9

Debug Support

9.1 Introduction...................................................................................................................... 9-2

9.2 Overview.......................................................................................................................... 9-2

9.2.1 Software Debug Facilities............................................................................................ 9-2

9.2.1.1 PowerPC Book E Compatibility.............................................................................. 9-3

9.2.2 Additional Debug Facilities......................................................................................... 9-3

9.2.3 Hardware Debug Facilities .......................................................................................... 9-3

9.2.4 Sharing Debug Resources by Software/Hardware in e200z335.................................. 9-4

9.2.4.1 Simultaneous Hardware and Software Debug Event Handing in e200z335...........9-4

9.3 Debug Registers............................................................................................................... 9-5

9.4 Software Debug Events and Exceptions.......................................................................... 9-6

9.5 External Debug Support................................................................................................. 9-11

9.5.1 OnCE Introduction..................................................................................................... 9-12

9.5.2 JTAG/OnCE Signals.................................................................................................. 9-15

9.5.3 OnCE Internal Interface Signals................................................................................ 9-16

9.5.3.1 CPU Address and Attributes.................................................................................. 9-16

9.5.3.2 CPU Data............................................................................................................... 9-16

9.5.4 OnCE Interface Signals ............................................................................................. 9-16

9.5.5 OnCE Controller and Serial Interface........................................................................ 9-18

Inhaltsverzeichnis

Andere Freescale Semiconductor Computerhardware Handbücher

Freescale Semiconductor

Freescale Semiconductor FRDM-KL25Z Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor PowerQUICC III MPC8555E Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor PowerQUICC III Montage- und Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor MPC8260 PowerQUICC II Family Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor TWR-MPC8309 Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor 56F8013 Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor TWR-VF65GS10 Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor EVBCRTOUCH Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor i.MX 6SoloLite Linux Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor TWR-LS1021A Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor MPC8569E-MDS-PB Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor 56F827 Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor USB-KW24D512 Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor MTRCKTSPS5604P Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor MED-EKG Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor MCS08QG8 Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor HC05P3 Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor i.MX27 PDK 1.0 Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor TWR-MCF51QM Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor MSC8144E Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor FRDM-KE06 Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor MCF5329 Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor MCF54455 Bedienungsanleitung

Freescale Semiconductor

Freescale Semiconductor 802.15.4/Zigbee Bedienungsanleitung

Beliebte Computerhardware Handbücher anderer Marken

EMC2

EMC2 VNX Series Betriebsanleitung

Panasonic

Panasonic DV0PM20105 Bedienungsanleitung

Mitsubishi Electric

Mitsubishi Electric Q81BD-J61BT11 Bedienungsanleitung

Gigabyte

Gigabyte B660M DS3H AX DDR4 Bedienungsanleitung

Raidon

Raidon iT2300 Bedienungsanleitung

National Instruments

National Instruments PXI-8186 Bedienungsanleitung

Hauppauge

Hauppauge WinTV-HVR-2250 Bedienungsanleitung

Kontron

Kontron CP6002 Bedienungsanleitung

Manhattan

Manhattan 702843 Bedienungsanleitung

Aphex

Aphex 230 Bedienungsanleitung

AMD

AMD Phenom II Betriebshandbuch

Intel

Intel NUC 12 Pro Bedienungsanleitung

dbx

dbx Zone Pro 1260 Bedienungsanleitung

Galaxy

Galaxy GHDX2-2430S-24F4D Bedienungsanleitung

Intel

Intel AXXRMFBU4 Bedienungsanleitung

Kontron

Kontron DIMM-PC/MD Bedienungsanleitung

ST X-NUCLEO-SAFEA1B Betriebsanleitung

STEINWAY LYNGDORF

STEINWAY LYNGDORF SP-1 Bedienungsanleitung

Freescale Semiconductor e200z3 Bedienungsanleitung

Beliebte Computerhardware Handbücher anderer Marken