GigaDevice Semiconductor GD32W51 Series Bedienungsanleitung

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GigaDevice Semiconductor Inc.

GD32W51x

Arm®Cortex®-M3332-bit MCU

User Manual

Revision 1.0

( Nov 2021 )

                                                         GD32W51x User Manual 

 
Table of Contents 
Table of Contents.................................................................................................................2
List of Figures ....................................................................................................................24 
List of Tables ......................................................................................................................32 
System and memory architecture ............................................................................37 
1. Arm Cortex-M33 processor......................................................................................37 
2. System architecture.................................................................................................38 
3. TrustZone® overview................................................................................................40 
3.1. TrustZone® security attribution..................................................................................40 
3.2. Peripheral classification...........................................................................................42 
4. Memory map.............................................................................................................43 
4.1. On-chip SRAM memory ..........................................................................................47 
4.2. SRAM1 Write protection..........................................................................................47 
4.3. SRAM1 security protection ......................................................................................48 
4.4. SRAM1 Erase........................................................................................................48 
4.5. On-chip flash memory overview................................................................................48 
5. Boot configuration...................................................................................................48 
6. System configuration controller (SYSCFG).............................................................51 
6.1. SYSCFG main features...........................................................................................51 
6.2. SYSCFG TrustZone security and privilege .................................................................51 
6.3. SYSCFG registers..................................................................................................52 
7. Device electronic signature .....................................................................................64 
7.1. Memory density information.....................................................................................64 
7.2. Unique device ID (96 bits) .......................................................................................65 
Flash memory controller (FMC) ................................................................................67 
1. Overview...................................................................................................................67 
2. Characteristics.........................................................................................................67 
3. Systemoverview......................................................................................................67 
4. Function overview....................................................................................................68 
4.1. Flash memory architecture ......................................................................................68 
4.2. Read operations ....................................................................................................69 
4.3. Unlock the FMC_CTL/FMC_SECCTL register ............................................................70 
4.4. Page erase ...........................................................................................................71 
4.5. Mass erase...........................................................................................................72 
4.6. Main flash programming..........................................................................................74 
4.7. Option bytes..........................................................................................................75 

                                                         GD32W51x User Manual 

 
4.8. TrustZone security protection...................................................................................77 
4.9. Security protection .................................................................................................78 
4.10. Write protection......................................................................................................82 
4.11. Flash privileged and unprivileged mode.....................................................................82 
4.12. FLASH interrupts ...................................................................................................82 
5. Register definition....................................................................................................84 
5.1. Unlock key register (FMC_KEY)...............................................................................84 
5.2. Option byte unlock key register (FMC_OBKEY) ..........................................................84 
5.3. Status register (FMC_STAT) ....................................................................................85 
5.4. Control register (FMC_CTL).....................................................................................85 
5.5. Address register (FMC_ADDR) ................................................................................87 
5.6. Option byte status register (FMC_OBSTAT) ...............................................................88 
5.7. Secure Unlock key register (FMC_SECKEY)..............................................................88 
5.8. Secure status register (FMC_SECSTAT)....................................................................89 
5.9. Secure Control register (FMC_SECCTL) ...................................................................90 
5.10. Secure Address register (FMC_SECADDR) ...............................................................91 
5.11. Option byte register (FMC_OBR)..............................................................................92 
5.12. Option byte user register (FMC_OBUSER).................................................................93 
5.13. Secure mark configuration register 0 (FMC_SECMCFG0)............................................93 
5.14. Secure dedicated mark protection register 0 (FMC_DMP0)...........................................94 
5.15. Option byte write protection area register 0 (FMC_OBWRP0) .......................................94 
5.16. Secure mark configuration register 1 (FMC_SECMCFG1)............................................95 
5.17. Secure dedicated mark protection register 1 (FMC_DMP1)...........................................96 
5.18. Option byte write protection area register 1 (FMC_OBWRP1) .......................................96 
5.19. Secure mark configuration register 2(FMC_SECMCFG2).............................................97 
5.20. Secure mark configuration register 3 (FMC_SECMCFG3)............................................98 
5.21. NO-RTDEC region register x (FMC_NODECx, x=0,1,2,3).............................................98 
5.22. Offset region register (FMC_OFRG)..........................................................................99 
5.23. Offset value register (FMC_OFVR) ...........................................................................99 
5.24. Secure dedicated mark protection control register (FMC_DMPCTL).............................100 
5.25. Privilege configuration register (FMC_PRIVCFG)......................................................101 
5.26. Product ID register (FMC_PID)...............................................................................101 
Electronic fuse (EFUSE)...........................................................................................102 
1. Overview.................................................................................................................102 
2. Characteristics.......................................................................................................102 
3. Block diagram........................................................................................................102 
4. Function overview..................................................................................................103 
4.1. EFUSE architecture..............................................................................................103 
4.2. EFUSE macro description .....................................................................................103 
4.3. Read operation....................................................................................................107 
4.4. Program operation ...............................................................................................107 

                                                         GD32W51x User Manual 

 
5. Register definition..................................................................................................108 
5.1. Control and status register (EFUSE_CS) .................................................................108 
5.2. Address register (EFUSE_ADDR)...........................................................................109 
5.3. Control register (EFUSE_CTL)...............................................................................110 
5.4. Trustzone control register(EFUSE_TZCTL) .............................................................. 111 
5.5. Flash protection control register (EFUSE_FP_CTL)...................................................112 
5.6. User control register (EFUSE_USER_CTL)..............................................................112 
5.7. MCU initialization data register (EFUSE_MCU_INIT_DATA)........................................113 
5.8. Firmware AES key register (EFUSE_AES_KEY).......................................................114 
5.9. RoTPK key register (EFUSE_ROTPK_KEY) ............................................................114 
5.10. Debug password register (EFUSE_DP)...................................................................114 
5.11. IAK key or GSSA register (EFUSE_IAK_GSSA)........................................................115 
5.12. Product UID register (EFUSE_PUID) ......................................................................115 
5.13. HUK key register (EFUSE_HUK_KEY)....................................................................116 
5.14. RF data register (EFUSE_RF_DATA)......................................................................116 
5.15. User data register (EFUSE_USER_DATA)...............................................................116 
5.16. EFUSE Pre-TrustZone enable register (EFUSE_PRE_TZEN) .....................................117 
5.17. TrustZone boot address register (EFUSE_TZ_BOOT_ADDR).....................................117 
5.18. No-TrustZone boot address register (EFUSE_NTZ_BOOT_ADDR)..............................118 
Instruction cache (ICACHE)..................................................................................... 119 
1. Introduction............................................................................................................119 
2. Characteristics.......................................................................................................119 
3. Function overview..................................................................................................119 
3.1. ICACHE initialization.............................................................................................120 
3.2. Paired master cache.............................................................................................120 
3.3. ICACHE TAG memory ..........................................................................................121 
3.4. Address remapping ..............................................................................................121 
3.5. Cacheable and uncacheable access .......................................................................123 
3.6. ICACHE performance monitoring............................................................................124 
3.7. ICACHE interrupts................................................................................................124 
4. Register definition..................................................................................................126 
4.1. Control register (ICACHE_CTL)..............................................................................126 
4.2. Status register (ICACHE_STAT) .............................................................................127 
4.3. Interrupt enable register (ICACHE_INTEN) ..............................................................127 
4.4. Flag clear register (ICACHE_FC)............................................................................128 
4.5. Hit monitor counter register (ICACHE_HMC)............................................................128 
4.6. Miss monitor counter register (ICACHE_MMC).........................................................129 
4.7. Configuration register (ICACHE_CFGx)...................................................................129 
Power management unit (PMU) ..............................................................................131 
1. Overview.................................................................................................................131 
2. Characteristics.......................................................................................................131 

                                                         GD32W51x User Manual 

 
3. Function overview..................................................................................................132 
3.1. Battery backup domain .........................................................................................132 
3.2. VDD / VDDA power domain...................................................................................133 
3.3. 1.2V power domain ..............................................................................................135 
3.4. Power saving modes ............................................................................................136 
3.5. Security description..............................................................................................141 
4. Register definition..................................................................................................143 
4.1. Control register 0 (PMU_CTL0) ..............................................................................143 
4.2. Control and status register 0 (PMU_CS0) ................................................................145 
4.3. Control register 1 (PMU_CTL1) ..............................................................................147 
4.4. Control and status register 1 (PMU_CS1) ................................................................148 
4.5. RF Control register (PMU_RFCTL) .........................................................................148 
4.6. Secure configuration register (PMU_SECCFG).........................................................149 
4.7. Privilege configuration register (PMU_PRICFG)........................................................150 
Reset and clock unit (RCU) .....................................................................................152 
1. Reset control unit (RCTL) ......................................................................................152 
1.1. Overview ............................................................................................................152 
1.2. Function overview ................................................................................................152 
2. Clock control unit (CCTL)......................................................................................153 
2.1. Overview ............................................................................................................153 
2.2. Characteristics.....................................................................................................155 
2.3. Function overview ................................................................................................156 
3. RCU security protection.........................................................................................159 
4. RCU privilege protection........................................................................................161 
5. Register definition..................................................................................................163 
5.1. Control register (RCU_CTL)...................................................................................163 
5.2. PLL register (RCU_PLL)........................................................................................166 
5.3. Clock configuration register 0 (RCU_CFG0).............................................................167 
5.4. Clock interrupt register (RCU_INT) .........................................................................170 
5.5. AHB1 reset register (RCU_AHB1RST) ....................................................................173 
5.6. AHB2 reset register (RCU_AHB2RST) ....................................................................174 
5.7. AHB3 reset register (RCU_AHB3RST) ....................................................................175 
5.8. APB1 reset register (RCU_APB1RST).....................................................................176 
5.9. APB2 reset register (RCU_APB2RST).....................................................................178 
5.10. AHB1 enable register (RCU_AHB1EN)....................................................................179 
5.11. AHB2 enable register (RCU_AHB2EN)....................................................................182 
5.12. AHB3 enable register (RCU_AHB3EN)....................................................................183 
5.13. APB1 enable register (RCU_APB1EN)....................................................................183 
5.14. APB2 enable register (RCU_APB2EN)....................................................................185 
5.15. AHB1 sleep mode enable register (RCU_AHB1SPEN)...............................................187 
5.16. AHB2 sleep mode enable register (RCU_AHB2SPEN)...............................................189 

                                                         GD32W51x User Manual 

 
5.17. AHB3 sleep mode enable register (RCU_AHB3SPEN)...............................................190 
5.18. APB1 sleep mode enable register (RCU_APB1SPEN)...............................................190 
5.19. APB2 sleep mode enable register (RCU_APB2SPEN)...............................................192 
5.20. Backup domain control register (RCU_BDCTL).........................................................194 
5.21. Reset source/clock register (RCU_RSTSCK)............................................................195 
5.22. PLL clock spread spectrum control register (RCU_PLLSSCTL) ...................................197 
5.23. PLL clock configuration register (RCU_PLLCFG) ......................................................198 
5.24. Clock configuration register 1 (RCU_CFG1).............................................................199 
5.25. Additional clock control register (RCU_ADDCTL) ......................................................202 
5.26. Secure protection configuration register (RCU_SECP_CFG).......................................203 
5.27. Secure protection status register (RCU_SECP_STAT) ...............................................205 
5.28. AHB1 secure protection status register (RCU_AHB1SECP_STAT) ..............................206 
5.29. AHB2 secure protection status register (RCU_AHB2SECP_STAT) ..............................209 
5.30. AHB3 secure protection status register (RCU_AHB3SECP_STAT) ..............................210 
5.31. APB1 secure protection status register (RCU_APB1SECP_STAT) ...............................210 
5.32. APB2 secure protection status register (RCU_APB2SECP_STAT) ...............................212 
5.33. Voltage key register (RCU_VKEY)..........................................................................214 
5.34. Deep-sleep mode voltage register (RCU_DSV).........................................................214 
Interrupt/event controller (EXTI).............................................................................216 
1. Overview.................................................................................................................216 
2. Characteristics.......................................................................................................216 
3. Interrupts function overview..................................................................................216 
4. External interrupt and event (EXTI) block diagram...............................................220 
5. External interrupt and Event function overview....................................................220 
6. EXTI event protection.............................................................................................222 
7. EXTI security protection ........................................................................................223 
8. EXTI privilege protection .......................................................................................223 
9. Register definition..................................................................................................224 
9.1. Interrupt enable register (EXTI_INTEN) ...................................................................224 
9.2. Event enable register (EXTI_EVEN)........................................................................224 
9.3. Rising edge trigger enable register (EXTI_RTEN)......................................................225 
9.4. Falling edge trigger enable register (EXTI_FTEN) .....................................................226 
9.5. Software interrupt event register (EXTI_SWIEV).......................................................226 
9.6. Pending register (EXTI_PD)...................................................................................227 
9.7. Security configuration register (EXTI_SECCFG) .......................................................228 
9.8. Privilege configuration register (EXTI_PRIVCFG)......................................................228 
9.9. Lock register (EXTI_LOCK) ...................................................................................229 
General-purpose and alternate-function I/Os (GPIO and AFIO).........................230 
1. Overview.................................................................................................................230 

                                                         GD32W51x User Manual 

 
2. Characteristics .......................................................................................................230 
3. Function overview..................................................................................................230 
3.1. GPIO pin configuration..........................................................................................232 
3.2. External interrupt/event lines..................................................................................233 
3.3. Alternate functions (AF).........................................................................................233 
3.4. Additional functions ..............................................................................................233 
3.5. Input configuration................................................................................................233 
3.6. Output configuration.............................................................................................233
3.7. Analog configuration.............................................................................................234 
3.8. Alternate function (AF) configuration .......................................................................235 
3.9. GPIO locking function...........................................................................................235 
3.10. GPIO single cycle toggle function ...........................................................................236 
4. TrustZone GPIO security........................................................................................236 
5. Register definition..................................................................................................237 
5.1. Port control register (GPIOx_CTL, x=A..C)...............................................................237 
5.2. Port output mode register (GPIOx_OMODE, x=A..C).................................................239 
5.3. Port output speed register (GPIOx_OSPD, x=A..C) ...................................................241 
5.4. Port pull-up/pull-down register (GPIOx_PUD, x=A..C)................................................243 
5.5. Port input status register (GPIOx_ISTAT, x=A..C)......................................................245 
5.6. Port output control register (GPIOx_OCTL, x=A..C)...................................................245 
5.7. Port bit operate register (GPIOx_BOP, x=A..C) .........................................................246 
5.8. Port configuration lock register (GPIOx_LOCK, x=A..C) .............................................246 
5.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A..C)..................................247 
5.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A..C)..................................248 
5.11. Bit clear register (GPIOx_BC, x=A..C).....................................................................250 
5.12. Port bit toggle register (GPIOx_TG, x=A..C).............................................................250 
5.13. GPIO secure configuration register (GPIOx_SCFG) (x=A…C).....................................251 
TrustZone protection controller union (TZPCU)...................................................252 
1. Overview.................................................................................................................252 
2. Characteristics.......................................................................................................252 
3. Function overview..................................................................................................252 
3.1. Block diagram......................................................................................................252 
3.2. Illegal access definition.........................................................................................254 
3.3. TrustZone® security privilege controller (TZSPC)......................................................255 
3.4. TrustZone® block based memory protection controller (TZBMPC)...............................256 
3.5. TrustZone® illegal access controller (TZIAC)............................................................256 
3.6. SPC/GSSA debug................................................................................................257 
4. TZSPC Register definition .....................................................................................258 
4.1. TZSPC control register (TZPCU_TZSPC_CTL).........................................................258 
4.2. TZSPC secure access mode configuration register 0 (TZPCU_TZSPC_SAM_CFG0) .....258 
4.3. TZSPC secure access mode configuration register 1 (TZPCU_TZSPC_SAM_CFG1) .....261 

                                                         GD32W51x User Manual 

 
4.4. TZSPC secure access mode configuration register 2 (TZPCU_TZSPC_SAM_CFG2) .....263 
4.5. TZSPC privilege access mode configuration register 0 (TZPCU_TZSPC_PAM_CFG0)...264 
4.6. TZSPC privilege access mode configuration register 1 (TZPCU_TZSPC_PAM_CFG1)...266 
4.7. TZSPC privilege access mode configuration register 2 (TZPCU_TZSPC_PAM_CFG2)...269 
4.8. TZSPC external memory x non-secure mark register 0 
(TZPCU_TZSPC_TZMMPCx_NSM0)...................................................................................270 
4.9. TZSPC external memory x non-secure mark register 1 
(TZPCU_TZSPC_TZMMPCx_NSM1)...................................................................................271 
4.10. TZSPC external memory x non-secure mark register 2 
(TZPCU_TZSPC_TZMMPCx_NSM2)...................................................................................272 
4.11. TZSPC external memory x non-secure mark register 3 
(TZPCU_TZSPC_TZMMPCx_NSM3)...................................................................................273 
4.12. TZSPC debug configuration register (TZPCU_TZSPC_DBG_CFG) .............................274 
5. TZBMPC0 registers definition................................................................................275 
5.1. TZBMPC0 control register (TZPCU_TZBMPC0_CTL)................................................275 
5.2. TZBMPC0 vector register y (TZPCU_TZBMPC0_VECy) ............................................276 
5.3. TZBMPC0 lock register 0 (TZPCU_TZBMPC0_LOCK0).............................................276 
6. TZBMPC1 registers definition................................................................................277 
6.1. TZBMPC1 control register (TZPCU_TZBMPC1_CTL)................................................277 
6.2. TZBMPC1 vector register y (TZPCU_TZBMPC1_VECy) ............................................278 
6.3. TZBMPC1 lock register 0 (TZPCU_TZBMPC1_LOCK0).............................................279 
7. TZBMPC2 registers definition................................................................................279 
7.1. TZBMPC2 control register (TZPCU_TZBMPC2_CTL)................................................279 
7.2. TZBMPC2 vector register y (TZPCU_TZBMPC2_VECy) ............................................280 
7.3. TZBMPC2 lock register 0 (TZPCU_TZBMPC2_LOCK0).............................................281 
8. TZBMPC3 registers definition................................................................................281 
8.1. TZBMPC3 control register (TZPCU_TZBMPC3_CTL)................................................282 
8.2. TZBMPC3 vector register y (TZPCU_TZBMPC3_VECy) ............................................282 
8.3. TZBMPC3 lock register 0 (TZPCU_TZBMPC3_LOCK0).............................................283 
9. TZIAC Register definition.......................................................................................284 
9.1. TZIAC interrupt enable register 0 (TZPCU_TZIAC_INTEN0) .......................................284 
9.2. TZIAC interrupt enable register 1 (TZPCU_TZIAC_INTEN1) .......................................286 
9.3. TZIAC interrupt enable register 2 (TZPCU_TZIAC_INTEN2) .......................................289 
9.4. TZIAC status register 0 (TZPCU_TZIAC_STAT0) ......................................................291 
9.5. TZIAC status register 1 (TZPCU_TZIAC_STAT1) ......................................................293 
9.6. TZIAC status register 2 (TZPCU_TZIAC_STAT2) ......................................................296 
9.7. TZIAC flag clear register 0 (TZPCU_TZIAC_STATC0)................................................298 
9.8. TZIAC flag clear register 1 (TZPCU_TZIAC_STATC1)................................................300 
9.9. TZIAC flag clear register 2 (TZPCU_TZIAC_STATC2)................................................303 
CRC calculation unit (CRC) ..................................................................................306 
1. Overview .............................................................................................................306 

                                                         GD32W51x User Manual 

 
2. Characteristics....................................................................................................306 
3. Function overview ..............................................................................................307 
4. Register definition ..............................................................................................308 
4.1. Data register (CRC_DATA)....................................................................................308 
4.2. Free data register (CRC_FDATA) ...........................................................................308 
4.3. Control register (CRC_CTL)...................................................................................309 
True random number generator (TRNG) ............................................................310 
1. Overview .............................................................................................................310 
2. Characteristics....................................................................................................310 
3. Function overview ..............................................................................................310 
3.1. Operation flow .....................................................................................................311 
3.2. Error flags...........................................................................................................311 
4. Register definition ..............................................................................................312 
4.1. Control register (TRNG_CTL).................................................................................312 
4.2. Status register (TRNG_STAT) ................................................................................312 
4.3. Data register (TRNG_DATA)..................................................................................313 
Direct memory access controller (DMA) ............................................................315 
1. Overview.............................................................................................................315 
2. Characteristics....................................................................................................315 
3. Block diagram.....................................................................................................316 
4. Function overview..............................................................................................317 
4.1. Secure & priviledge ..............................................................................................318 
4.2. Peripheral handshake...........................................................................................319 
4.3. Data process.......................................................................................................321 
4.4. Address generation ..............................................................................................327 
4.5. Circular mode......................................................................................................327 
4.6. Switch-buffer mode...............................................................................................328 
4.7. Transfer flow controller..........................................................................................328 
4.8. Transfer operation................................................................................................329 
4.9. Transfer finish......................................................................................................330 
4.10. Channel configuration...........................................................................................331 
5. Interrupts.............................................................................................................332 
5.1. Flag ...................................................................................................................333 
5.2. Exception............................................................................................................334 
5.3. Error ..................................................................................................................335 
6. Register definition ..............................................................................................337 
6.1. Interrupt flag register 0 (DMA_INTF0)......................................................................337 
6.2. Interrupt flag register 1 (DMA_INTF1)......................................................................338 

                                                         GD32W51x User Manual 

 
6.3. Interrupt flag clear register 0 (DMA_INTC0)..............................................................339 
6.4. Interrupt flag clear register 1 (DMA_INTC1)..............................................................339 
6.5. Channel x control register (DMA_CHxCTL) ..............................................................340 
6.6. Channel x counter register (DMA_CHxCNT).............................................................344 
6.7. Channel x peripheral base address register (DMA_CHxPADDR) .................................344 
6.8. Channel x memory 0 base address register (DMA_CHxM0ADDR)...............................345 
6.9. Channel x memory 1 base address register (DMA_CHxM1ADDR)...............................346 
6.10. Channel x FIFO control register (DMA_CHxFCTL) ....................................................346 
6.11. Security status register (DMA_SSTAT) ....................................................................347 
6.12. Security status clear register (DMA_SSC)................................................................348 
6.13. Channel x security control register (DMA_CHxSCTL) ................................................349 
Debug (DBG)...........................................................................................................351 
1. Overview.............................................................................................................351 
2. JTAG/SW function description...........................................................................351 
2.1. Switch JTAG or SW interface.................................................................................351 
2.2. Pin assignment ....................................................................................................351 
2.3. JTAG daisy chained structure.................................................................................352 
2.4. Debug reset ........................................................................................................352 
2.5. JEDEC-106 ID code.............................................................................................352 
3. Debug hold function description........................................................................352 
3.1. Debug support for power saving mode ....................................................................352 
3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and RTC.......................................353 
4. DBG registers......................................................................................................354 
4.1. ID code register (DBG_ID).....................................................................................354 
4.2. Control register 0 (DBG_CTL0) ..............................................................................354 
4.3. Control register 1 (DBG_CTL1) ..............................................................................355 
4.4. Control register 2 (DBG_CTL2) ..............................................................................357 
Analog to digital converter (ADC) .......................................................................358 
1. Overview .............................................................................................................358 
2. Characteristics....................................................................................................358 
3. Pins and internal signals ....................................................................................359 
4. Function overview ..............................................................................................360 
4.1. ADC clock...........................................................................................................360 
4.2. ADCON switch.....................................................................................................360 
4.3. Regular and inserted channel groups ......................................................................360 
4.4. Conversion modes ...............................................................................................361 
4.5. Inserted channel management ...............................................................................365 
4.6. Analog watchdog .................................................................................................366 
4.7. Data alignment ....................................................................................................366 
4.8. Programmable sampling time.................................................................................367 