HP 13220 Handbuch

()

~?~:;~:;

()

Mod u1e

Manual

Part

No.

13220-91087

REVISED

JAN···

()

4····B2

DATA

TERMINAL

TECHNICAL

INFORMATION

HEWLETT~PACKARD

Printed

U.S.A.

0 c

(~~:;

~:;

0 7' M

()

d u1e

Manual

Part

No.

13220-91087

I~EVISED

JAN···

()

4····0t?

NOTICE

The

inforMation

contained

this

dOCUMent

subject

change

w:i.ti"lou"t

notic€~.

HEWl..ETT····Pt-.CI{ARD t'\AI{EB

WARI~ANTY

OF ANY

I{IND

WITH

'~EGAI~l)

THIS

MATERIAL,

INCLUDING,

BUT

NOT

LIMITED

THE

IMPLIED

WARRANTIES

MERCHANTABILITY

AND FITNESS

FOR

PARTICULAR

PURPOSE.

Hewlett-Packard

shall

not

liable

for

errors

contained

herein

for

incidental

con~)f:~quf.·!n·t:i.al

dat

...

aqE~s

c()nn~:~ction

with

th(·!

fUl'nis;hinq,

~)E~l'for'Manc:~?,

use

this

Material.

This

dOCUMent

contains

proprietary

inforMation

which

protected

cop

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reproduced

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yr'

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j.9S;:-!.

HEWI...ETT--PACKARD COMPANY

NOTE:

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docuME!nt

par't

th(~

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DATA

TERMINAl...

pr'oduct

~:)

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for'

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ion

Pi:\

(HP j.3

;:~

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()

) .

i.O

IN"l"RODUCTION

The

02620-60087

Processor

PCA

perforMs

the

terMinal

logic

functions

for

the

2622A

terMinal.

Its

operation

based

the

Z80A

Microprocessor

and

the

National

SeMiconductor

8367

CRT

Controller

(CRTC).

The

control

and

I/O

section

the

Processor

PCA

provides

control

~;>

i qna1

~:>

:i.

put

/ 0 ut

put

and

tap

roc

(~s~:;:i.

n(J

fun

c t j. 0

n~:;

The

MeM

0 r' y

section

provides

16K

bytes

dynaMic

RAM

for

display

MeMory,

scratch

pad

MeMory

and

data

buffers,

and

space

for

six

byte

RUMs

which

32K

are

used

for

COMplete

terMinal

operation

(8K

ROM

optional

with

integral

printer).

The

video

control

section

provides

all

tiMing

signals

for

driving

the

sweep

circuitry

and

video

logic

well

perforMing

direct

MeMory

access

CDMA)

display

data.

detailed

description

the

operation

each

these

sections

follows

:i.

~:;ec

ion

0 .

2.0

OPERATING

PARAMETERS.

SUMMary

operating

paraMeters

for

the

Processor

Module

contained

tables

1.0

through

4.0

Table

1.0

Physical

ParaMeters

===============================================================================

Par'

t Si ze (I... x W x

W(~

i qh t 1

NUI"',IHH'

NOMf:·~nclatul'~~

....

0.1

Inche~;

(Pounds>

1=============1==============================1=======================1========1

1 I 1 1 1

1 1 1 1 1

02620-60087

Processor

PCA

12.3

10.9

O.S

1.4

1 1 1 1

I 1 1 1

1 1 1 1

===============================================================================

:'5;:~:~O

Pl'

()Cf.~<':;~;()l'

Mod

uIe'

Table

2.0

Reliability

and

EnvironMental

InforMation

~5220

....

f/1

H'7

()

Rev JAN-()4····f32

================:========~======================================================

EnvironMental:

Class

Restrictions:

Type

tested

product

level

I==~===========~==============================================================

Failure

Rate:

3.71

(percent

per

1000

hours)

===================~======~====================================================

Table

3.0

Power

Supply

RequireMents

Measured

(At

+/-5%

Unless

Otherwise

Specified)

===~=============================~=============================================

+16

Volt

Supply

+12

Volt

Supply

Volt

Supply

-12

Volt

Supply

ill 0

200

2.0

A I @

NOT

APPLICABLE I I I I

:::

::;:

:~:

::::

::::::::

::::

::::::::::::

::::::::

::::

:;::

::::

::::::::

:'~:::::

:::: ::::

::::

:.::::::

:::: :::: :::: :::: ::::

:::::-.::::::

::::

::::::::

::::

:::

=::::::::::::

:::: ::::

::::::::

::::

::::::::

:.~:::::

::::::::::::

:::: ::::

::::::::::::

:::::::::".::

:::::::::::

:::: ::::

::::

::::::::

I I I

115

volts

220

volts

I I I

A I

I I I

NOT

APPL.ICABL.E I

NOT

APPLICABLE I

===============================================================================

13~~2

()

0 C

£~

~:;

~:)

()

du1e

Table

4.0

Connector

InforMation

:1.

3~~~:~

0···9108'7/04

(::~

v JAN···

()

4···B;?

===~==========~===~========~===================================================

Connector

Signal

and

No. 1

NaM(~

1==============1================

···1

....

··7

....

·-9

....

:1.

0 I

....

:1.1

....

:1.

;,?

"-L3 t

-14

·16

....

1·7

-1t3

-·19

"-20

....

·-22

-;~3

-24

"-25

-26

PRINTER

PWI~

ON/FAIL

WRITE

DATA

()

DATA

DATA 2

DATA

GND

PINT

+SV

GND

GNU

GND

Signal

Description

=============================================\

PRINTER

Negative

True,

Printer

Strobe

Negative

True,Power

On/Failing

Negative

True,

Write

signal

Negative

True,

Fun~tion

select

bit

LSB

Negative

True,

Data

MSB

Negative

True,

Data

Set

printer

contrast

Negative

True,

Printer

Interrupt

Negative

True,

Function

select

bit

Vcc

Power

Retul'n

~5~~2()

Pl'OC(~SS)Ol'

Module

13220-91.08'7/0S

Rev

JAN-()4-B2

Table

4.0

Connector

InforMation

(Cont'd)

===============================================================================~

Connector

Signal

and

No.

NaMe

Signal

Description

\==============1================

==============================================

J;:.~

I 1

-·1

+5V

-.~:~

-3

+SV

-4

+12V

-S

GND

-6

GND

...

..........

......

POWER

SUPPL.Y

+SV

Power

N/C

+5V

Power

+1;':'~V

Power

R€~t

ur'n f

01'

Power

Ret

urn

for'

ow(~r

-'7

PWR

ON/FAIL

Negative

True,

Power

On/Failing

-8

-1.2V

-12V

Power

-9

BATTERY

Positive

Battery

TerMinal

-10

BATRET

Negative

Battery

TerMinal

........................................

............

._.-

....

''''

.....

.....................

••

.-.-

-.--

......

.......

.............

_.-.-

...........

.....

..........

-.-.-

....

''''

...

_.-

....

.....

_._.-

--'-

_.-

J~3

1 I

.....

....

. I

-1

HLFBRT

-2

-3

RETURN

........

...........

_._._.

I --4

FUL.L.BI~

T \

-5

RETURN

-6

RETURN

I I

....

iJ'f~:'ifi)rf

-8

HORDR

.....

........

, _

..........

........

...........

..........

............

...............

.............

•.

)

....

·3

...

-4

·s

·6

....

·7

-·B

·9

....

()

····1.1

....

\(EYO

KEYj

KEY2

KEY:~

I<EY4

KEYS

KEY6

KEYACT

GNI>

BELL..

+Sv

SWEEP

Negative

true,

Half

Bright

Video

N/C

Return

for

half

bright

twisted

pair

Negative

true,

Full

Bright

Video

Return

for

Video

twisted

pair

Return

for

Drive

signals

Negative

True,

Vertical

Drive

Horizontal

Drive

KEYBOARD

Key

Data

(LSB)

KE~y

Data

Key

Data

Key

Data

Key

Data

N/C

K(~~y

Dc:l

)(ey

Data

(MSS)

Key

Active

(Status

key

selected)

Pow(~r

Return

Bell

Line

+5v

Power

================================~===============================================

~5;.:!.2

Pr'oc(::~ssor'

Module

Table

4.0

Connector

InforMation

(Cont'd)

~5220'-91

08'7/06

Rev

JAN-()4'-B2

~===============================================================================

Connector

Signal

and

No. I

NaM€~

Des;cr'iption

==============1================1==============================================

DATA

COMM

....

j. N/C

-.;~

+SV

Pod P

ow€~r

"'~3

+SV

Pod

Power

....

GN!)

P()w(~r

R(~tul'n

~~S

GNl>

OWf-~r'

I~et

urn

"~6

GND

P()w(~r

Return

~'J

DeDi

Rat(:~

S~~lect

(23)

··8

Nit

(~c

f:d.

(·~d

l)clti:\

(3)

··10

Nit

·1 i

(,(:'

.,,,:>

Clf~dr'

Send

(5)

....

Di:l

S(?t

Rei:ld

(6)

"~13

N/C

·14

Nit

....

Si~}na

Gr'

und

(7)

-··16

NIt

....

N/C

....

OCR1

Rinq

Ind:i.cator

(~~2

)

·j.9

+1;~V

+12V

Pod

Power

....

--1;:!V

'-1~~\)

Pod

Power

--21

Tr';HlSMl.

t(~d

Data

(2)

;;!;,?

r~eqllest

Send

(4)

....

;:?~~

Ready

(20)

"-;?4

Nit

"-25

N/C

....

NIt

-~27

N/C

··;,?8

N/C

-29

N/C

-~3

()

Nit

"-31

N/C

"-3;.~

GND

Return

··33 SHIEL.l)

Shi(-.~ld

Ground

( 1 )

....

~34

N/C

(n)

denotes

the

RS-232

nUMber

================================================================================

~3~!'~~0

Pl'

()c€-~~:;s()r'

M()d

1:3220·-91.

OB'7

10'7

Rev

JAN····

04'-(32

3.0

FUNCTIONAL

DESCRIPTION

Refer

t()

bl()ck

diagraM

(fig.

1),

scheMatic

diagraMs

(figs.

2,3),

tiMing

diagraMs

(figs.

4-8),

COMponent

location

diagraM

(fig.

and

parts

list

(fig.

10)

located

the

appendix.

The

following

describes

the

()peration

the

three

Major

sections

the

Processor

peA)

control

and

lID,

MeMory,

and

video

c()ntrol.

CONTROL.

AND

I/O

SECTION

Clock

25.7715

MHz

crystal

attached

the

CRTC

which

oscillates

the

video

d()t

frequency.

This

buffered

the

CRTC

and

again

74LS244

(US11)

beCOMe

DRCX,

buffered

dot

rate

clock.

This

clock

then

divided

seven

the

748163

(Ub11)

produce

3.6816

MHz,

which

shaped

and

its

associated

circuitry

produce

SYMMetrical

clock

for

the

ZaOA,

which

has

zero

level

0.4SV

and

one

level>

4.4V.

This

clock

also

divided

two

produce

1.8408

MHz

clock

which

the

datacoMM

chip

(U613)

uses

produce

baud

rates.

lOOA

The

laOA

Microprocessor

perforMS

the

Major

control

and

data

Manipula-

tion

functions

the

processor

peA.

provides

addresses

and

control

signals

read

and

write

data

frOM

and

both

MeMory

and

I/O

ports.

also

responds

two

externally

generated

interrupts,

NNMI

and

NINT,

which,

when

enabled,

interrupt

current

execution

and

cause

the

ZaOA

branch

its

interrupt

service

routine.

The

ZBOA

also

responds

bus

request

signal,

NBUSREQ,

allowing

the

CRTC

control

the

systeM

b u

~:)es

power

(or

reset)

the

ZaOA

begins

executing

instructions

frOM

prograM

MeMory

beginning

address

OOOOH.

routine

executed

which

initializes

variables

and

devices

according

inforMation

contained

non-volatile

MeM()ry

(CMOS)

and

perforMS

self

test

ROM

and

RAM.

error

detected

series

beeps

are

issued

the

keyboard

which

indicate

the

failing

ROM

RAM.

After

inintialization

the

prograM

enters

Major

10()P

responding

inputs

frOM

the

keyboard

and

datacoMM

por'ts.

Three

74LS244's

(U4'7,U57,U511)

buffer

the

address

and

control

lines

frOM

the

Z80A.

The

decoder,

U76,

used

separate

prograM

MeMory

into

six

blocks,

each

bytes

long.

The

addressed

ROM

en-

abled

during

a MeMory

read

the

TNRD

and

TNMREQ

signals

()r

during

instructi()n

fetch

the

NMl

signal.

Since

the

tiMe

read

the

data

instruction

fetch

less

than

that

for

MeM()ry

read,

the

NM1

signal

was

used

provide

early

enable

the

ROM

allowing

respond

within

the

required

tiMe.

ROMs

with

access

tiMes

350

frOM

address

300

frOM

enable

are

required

t()

run

the

systeM

full

speed.

[PROMs

ROMs

with

450

access

tiMes

frOM

address

May

used

installing

JUMper

and

reMoving

JUMper

W6,

which

causes

the

ZaOA

wait

one

cycle

l()nger

during

instructi()n

fetches.

The

quad

latch

U610

and

ass()ciated

gating

provides

the

required

wait

signal

th~:~

ZBOA.,

13220

Processor

Module

13220-91087/08

Rev

JAN-04-82

3.1.3

I/O

Ports

CMUS

The

Z80A

capable

addressing

2S6

different

input/output

ports.

I/O

addresses

froM

the

ZaOA

appear

address

bits

AO-A7

and

the

accuMulator

contents

appear

bits

A8-A1S.

I/O

addresses

0-7FH

are

used

access

locations

the

nonvolatile

CMOS

RAM,

U73,

where

configuration

data

stored.

Since

the

CMOS

RAM

not

fast

enough

respond

within

the

I/O

cycle

tiMe

wait

state

generated

(by

U6l0)

each

tiMe

the

CMOS

RAM

accessed.

Diodes

CR6-CR8

ensure

that

around

volts

always

t~e

CMOS

supply

pin.

EMMitter

follower

Circuit,

Q3,

Makes

sure

that

during

power

off

the

CMOS

always

disabled

before

the

l80A

buses

beCOMe

undefined

and

reMains

until

buses

beCOMe

defined

power

on.

During

power

off

the

battery

Maintains

CMOS

contents.

power

configuration

fixed,

the

COMS

RAM

May

replaced

HM7611

PROM

(however

Must

realized

that

the

standard

read/COMpleMent/write

test

for

the

CMOS

self

test

would

show

CMOS

error

since

the

prOM

cannot

written).

DATACOMM

The

SY6SS1

Asynchronous

COMMunications

Interface

Adapter

perforMS

the

parallel

serial

conversion,

error

detection

and

baud

rate

generation

functions

required

for

serial

data

COMMunication.

appears

the

laOA

four

read

only

and

four

write

only

ports

with

address

bit

TA2

selecting

the

read/write

function.

This

done

COMpensate

for

the

unique

tiMing

the

6500

series

devices.

The

SY6551

selected

the

rising

edge

SELDC

which

inverted

frOM

U24,

the

decoder.

The

addresses

the

SY6SS1

(U613)

are

AO-A7H.

The

status

inputs

the

SY6SSl

produce

undesirable

results

and

therefore

are

forced

their

active

low

states

while

the

necessary

status

signals

are

routed

through

another

port.

RS-232

line

driver,

USi4,

and

receiver,

U614,

are

~sed

convert

frOM

TTL

levels

RS-232

levels

(+-12V)

and

vice

versa.

TranSMitted

signals

are:

send

data

(SD),

terMinal

ready

(TR),

request

send

(RS)

and

optional

control

driver

1 (OCD1).

Received

signals

are:

receive

d~ta

(RD),

data

Mode

(DM),

optional

control

receiver

(OCR1),

and

clea~

send

(eS).

The

datacoMM

subsysteM

operates

asynChronous,

full-duplex,

point-

to-point

environMent.

Characters

May

tranSMitted

and

received

siMultaneously

(full-duplex)

with

character

flow

occurring

over

randOM

tiMe

intervals

(asynchronous).

achieve

hardware

synchronization

each

character

fraMed

by a

start

bit

and

stop

bit

stop

bits

110

baud).

The

addition

the

fraMing

bits

for

tranSMitted

characters

and

the

detection

fraMing

bits

for

the

received

characters

are

done

the

SY65S1.

The

parity

(for

error

detection)

the

character

selectable

(in

the

datacoMM

configuration

Menu)

and

also

generated

and

detected

the

SY6SS1

which

reports

errors

(parity,

fraMing,

and

overrun)

the

ZaOA

Means

status

the

SY6SS1

which

read

when a

character

received.

The

data

tranSMission

and

reception

rates

are

set

the

ZaOA

internal

reqister

within

the

SY6SS1.

13220

Processor

Module

13220-91087/09

Rev

JAN-04-82

Rates

are

selectable

(in

the

datacoMM

configuration

Menu) frOM

110

9600

baud.

The

datacoMM

status

inputs

and

outputs

provide

the

necessary

control

lines

connect

the

terMinal

host

COMputer

via

a ModeM,

provide

direct

hardware

handshaking

between

the

terMinal

and

host.

power-on

the

and

lines

are

activated

indicate

that

the

terMinal

ready.

Upon

receipt

ModeM

disconnect

escape

sequence

(esc

the

line

brought

inactive

for

.about

two

seconds

disconnect

the

ModeM.

The

presence

ModeM

connection

detected

which

causes

the

indicator

"LED"

(an

asterisk

'*')

displayed

the

bOttoM

center

the

display.

The

signal

frOM

the

host

when

active

allows

the

terMinal

tranSMit

data

and

goes

inactive

halt

tranSMission

(the

terMinal

May

ignore

depending

datacoMM

configuration).

The

state

OCDl

controlled

configuration

strap

with

its

default

state

being

low

(inactive).

This

line

selects

the

ModeM

rate

for

dual

speed

ModeMS. OCRl

Monitored

datacoMM

self

test

detect

the

presence

the

loopback

test

hood.

All

ModeM

status

lines

are

active

high

(+12V).

Upon

receipt

character

frOM

datacoMM

the

SY6SS1

generates

interrupt

signal

(NINT)

the

lBOA.

This

causes

the

ZaOA

branch

the

datacoMM

interrupt

service

routine

which

reads

the

SY6S51

status,

clearing

the

interrupt,

and

errors

are

present,

inputs

th~

character

and

places

into

the

datacoMM

buffer

RAM.

Characters

for

which

errors

(parity,

fraMing

overrun)

are

present

cause

delete

character

placed

the

buffer.

Teus

PORTS

The

reMaining

I/O

ports

are

buffered

the

ZaOA

data

bus

the

biderectional

bus

driver,

U37.

This

was

done

because

data

bus

The

signal

TNRD

selects

the

direction

the

driver

which

enabled

for

all

I/O

accesses

except

CMOS

RAM

and

datacOMM.

U25

forMS

the

keystatus

port

located

address

80H.

The

keystatus

port

returns

the

status

keys

tiMe,

which

keys

are

deterMined

th~

keyboard/display

port

(U26).

Four

bits

the

key

address

(colUMn

address)

are

supplied

by U26

(located

address

B8H)

and

three

frOM

the

eRTC

scan

line

outputs

(row

address).

the

row

address

(scan

line

count)

frOM

the

CRTC

change,

keystates

are

clocked

into

the

keystatus

shift

high

bit

indicating

key

active)

frOM

which

they

are

later

read.

The

colUMn

address

increMented

(during

an NMI)

for

each

the

first

sixteen

display

rows

thereby

scanning

the

entire

range

keyboard

addresses.

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