Hyundai PD421 Bedienungsanleitung

Hyundai

Plasma Display

PD421 Svc Manual

--1--

Plasma Display PD421

. Circuit Service Methods

1. W hite Ba lance Adjustment

l Refer to adjustment specifications for information on makin g adjustments

m When white alance has to e adjusted during service

- If the module is replaced, it must e readjusted u sing VG -828 equipment,

according to the adjustment specifications

- When making progra m upgrades [ ROM (UM04) replacement] or replaci ng A/V

B/D, the values stored i n A/V B /D’ s EPROM (UM12) should e written down

and re-ente

The method of white Balane Adjustment efore ROM or B/D IS Replaced

red into the new new Rom or A/V Board.

efore Rom or B/D is

Replaced

select the Video Mode

Select "Device" from

the menu

Select AD9883

R.G.B-Gain value

Factory Mode Exit

Select the pc mode

Enter into the Factory

mode

Select the Device

Select AD9883

R.G.B-Gain value

R.G.B-Gain valye

Enter the Menu+42+

Mute key

Select "White" from the

R.G.B-Gain value

R.G.B-Blas value

Select "Device"

Select FLI2300

Brightness and

Contrast values

Factory Mode Exit

Select the DTV mode

Enter into the Factory

mode

Enter into the

Factory Mode

Separate Record(a)

Separate Record(c)

Separate Record(d)

Separate Record( )

--2--

After ROM or B/D

replaced

Select the Video mode

After selecting AD9883

enter(c) Data recorded

in R,G and B-Gain and

Bi as values separately

After exiting from the

Factory select the

PC mode

Enter the Facrory to

select the PC mode

Enter(a) Data recorded

in R.G and B-Gain and

Bias values separately

After selecting AD9883

enter(c) Data recorded in

R.G and B-Gain and Bias

values separately

Completed adjustments of

the White alance

Enter in to the Factory

mode

After selecting "Whte"

enter (a) Data recorded

in Bias values

Separately

After selecting

FLI2300, enter( ) Data

recorded in Brightness

and Contrast values

separately

After exiting from

Factory, select the

DTV mode

After entering into

Factory to select

White enter(a) Data

recorded tn R,G and

B-Gain and Bias

values separately

:When ROM and AV B/D are

replaced without additional

equipment, this is how to

adjust the white alance

--3--

Plasma Display PD421

2. A/V Circuit BLOCK Diagram

1) PC Mode

PC inputs, R, G, B , H, and V signals, are entered through D-S u 15pin

(DSUB1). They are entered into the DTV/PC sele ction switch, B A7657

(UA01). When PC is selected in M CU, the signals are entered into the AD

converter, AD 9883 (UA02).

In AD9883, the signals are c onverted into 24 its and entered into scaler

ASI500.

BA7657 selects PC when pin16 is high and selects DT V when pin 16 is low.

AD9883 is controlled using the SDA/SCL line of pin 57/56.

PC input resolution is fh: 30~70k a nd fv: 50~85Hz, and the maximum

resolution is 1080x768 at 85Hz.

If the resolution is a ove the specifications, an out of range m essage is

displayed on the upper left hand corner of the screen. However, even if the

resolution is within the specified range, if the input timing is different from

the timing indicated on the manual, a ‘not found vesa o r out of range’

message can e displayed. Please check the timing to identify the cause of

the ‘out of range’ message.

PC input sync can rece ive H/V composite or separate, ut if DPMS ON is

selected in the PDP menu, DPMS cannot o perate in composite and c an

operate only in separate sync.

The Auto Adjust function, which is used to adjust the picture position and

size, should e carried out in the Windows desktop screen or full cross hatch.

The D TV signals, 480p, 720p, and 1080i, from the set-top ox with a D-Su

out port, can e received through the D-Su port and displayed in the PC

mode.

DVI Mode

Signals entering through the DVI port (D V101) are converted to 24 its in

the TMDS Receiver, SIL161B (UT02 ), and entered in scalar ASI500.

SIL161B is an output port and is activated when pin num er 2 is high.

DTV signa ls 480p, 720p, and 1080i can e displayed through the DVI port .

However, PD421 cannot only display 60Hz DTV signals. It is una le to

display 50Hz DTV signals. PC can support oth 50Hz and 60Hz signals.

The resolution of DVI Mode is the same as the PC Mode.

--4--

2) DTV Mode

DTV signals are entered as Y, P (C ), and Pr(Cr) component signals,

separated into Y, C , Cr, H, and V sync on (xan51AcuxA01) and entered to BA7 657.

If pin 16 is low, DTV signals are entered into ADC9883.

In the AD9883, like the PC signals, the DTV signals are converted to 24 its

and entered into scalar ASI500.

DTV signa l is composed of 480p (50/60Hz) for SD, 720p (50/60Hz) for HD,

and 1080i (50/ 60Hz). If the video signal, 480i component (DVD component

output), is entered, the screen will not display properly. Also,

ecause synchronization signal

if the connections are incorrect, it will not operate properly

is in Y singal color Data is in Cr/C

3) DVD Mode

DVD signals entered as Y, P , and Pr components are applied when entered

as 480i (NT or PAL). 480p DVD signals should e entered through the DTV

component port.

Y, P , and P r signals entered through the DVD component port are entered

into the video decoders, Main VPC3230 (UDM01) and Su VPC3230 (U DS01),

where they are converted to Y (8 its) and UV (8 its) digital sig nals and sent

to the deinterlacer IC, F LI2310 (UF L1).

UV digital signal means P (C ), and Pr(Cr) signals that have een converted

to digital signals.

The v ideo decoder, VPC3230, automatically detects NTSC and PAL/S ECAM,

identifies them as roadcast signals, converts the interlacer signal into the

progressive signal (fh : 15.7Khz-> 31Khz) in t he deinterlacer IC, FL I2310

(UF L1), and sends to the scalar ASI500.

When the PD 421’s main screen is in PC, DVI or DTV mode, the su -screen

of the PIP or POP function is processed in the Main VI DEO DECODER

(UDM01) and the MODE can e DVD, S-VHS, Video, or Scart.

PIP or POP etween video modes is ena led y main video decoder (U DS01),

su video decoder (UDS01), and F IFO memory, MS81V04160 (UF M01). If the

main screen is DVD, then the su - screen will e S-VHS, Vid eo, or Scart.

Please refer to the ta le in the ack for more information on PIP or POP.

4) S-Video

S-Video signals are entered as Y/ C signals, which is composed of Luminance

--5--

Plasma Display PD421

color signals. The NT SC and PAL/SECAM are automatically detected y the

video decoders, main VPC3230 and su VPC3230, and converted to Y (8 its)

and UV (8 its) and sent to the deinterla cer IC, FLI2310, as 16 it digital

signal.

S-Video input and composite video input share a single audio jack.

Therefore, while the pictures for the two inputs can e viewed at the same

time, only one of the sounds can e heard. PIP/POP operati ons are the same

as descri ed for the DVD mode.

5) Video

Video signal is a composite signal that com ines the Luminance (Y) and color

(CHROMA) .

It is entered through the main VPC3230 and su VPC3230 when selected in

the input selection switch, TA8851 (UMX01).

If the signal is NTSC, it is first entered into the 3D Com Filter (fi lter that

separates the composite to Y/C signal), UPD 64083 (UCF 01) and separated into

Luminance signal Y and color signal, C. The separated signals then enter the

mux switch, TA8851, sent to TA8851 pin44 LU MA IN and pin43 CROMA IN,

and finally sent to Main VPC3230.

When the video input is displayed on the main screen, it passes through the

3D com filter, ut if it is displayed on the su - screen (when using PIP or

POP), the video input does not pass through the 3D com filter a nd i s

displayed using the composite signal.

PAL/SECAM signal cannot e processed y the 3D com filter. It i s sent as

composite signal to the main VPC3230 and su VPC3230.

If the signal is NTSC, the video input switch, BF 7654 (UDM02), which is

located in front of the main VPC3230, select the 3D Com -Y to send the

signal as a Y signal to the VPC 3230. If the signal is Pa l, it selects CVB S to

send the signal as a composite signal to the VPC3230.

Signals entered into VPC3230 are converted to 16 it digital signal (Y (8 its)

and UV (8 its)) and sent to the scalar through the deinterlacer IC, F L I2310.

6) Scart Mode

Scart only supports CV BS signals, which are processed in the same way as

video signals. The RF signal is not supported, and therefore, the Scart pin8

ID signal is ignored.

--6--

Plasma Display PD421

7) PIP/POP Support Mode Map

Main PC DTV DVD S-VHS Video Scart DVI

PC X

X O X

DTV X X O X

DVD O O O OOO

OOO

S-VHS X O O O

Video X O O

Scart X O

DVI X X O O O O X

X: Not supported, O: Supported

Note: When displaying NTSC or P AL signals to PIP or POP , if the signals are displayed

as Main: NT SC, Su : P AL or in reverse, the picture can e seen, ut the size scaling for

the su -scr een will not display properly. This is ecause the signal is meant for the

main screen. Main screen use s 50Hz PAL or 60Hz NTSC and su scre en uses 60Hz

NTSC or 50Hz .

8) Scaler Output

Scaler output signals, R, G, and B (each 8 its), are outputted as 24 it TTL

signal, converted into LVDS signal in the LVDS converter, DS90C3 85

(ULV01), and sent to the logic B/D in the PDP module. Output timing:

fh : 29.1Khz

fv : PAL 50Hz

NTSC 60Hz

DCLK : a out 27Mhz

9) Audio part

Audio input port for each mode:

Input Port Remark

PC/DVI RCA L/R 1E A Shared

DTV RCA L/R 1E A

DVD RCA L /R 1E A

CVBS/S-Video RCA L/R 1E A Shared

Scart cart Jack L/R

--7--

Plasma Display PD421

Audio input signal for PC/DVI, DT V, and DV D modes is entered into the

audio processor IC, MSP3450G , and audio input signal for VID E O/S-VIDEO,

and SCART modes is first selected in MUX 8851 a nd entered into the audio

processor.

As in other chips, the audio processor (MSP34 50G) uses the SCL and SDA

line to control volume, and left/right alance and mono/stereo.

The L/R audio signal sent y MSP3450 is a mplified in the amplifier, TA2 024

(UAU1) and sent to the speaker.

TA2024B support 10W( ased on impedance 8Y ) of output for each L/R.

3. Trou le shooting

1) Diagnosing defective module

If the power does not come on or if the module operates a normally, check

module defect. To do this, remove the rear cover and A/V B/D to reveal the

module’s logic B /D. The following figure represents the s/w on the logic B/D.

SW 2001

Signal 1 2 Remark

External up up up Forwarding

Criteria

Internal up down

If the switch is set to internal signals, it will operate without external signals,

ut the screen will e displayed in full white.

Therefore the module operation can e checked without the A/V oard.

Here, e aware that the pin 8 and pin 9 of the power B /D’s CN802(11p),

which is located a ove the module’s logic B /D, must e shorted and the A/C

power supplied in order for the module to operate normally. Pin 8 is marked

as PS-ON elow the connector (CN802).

If module itself is tested and it does not power on or the picture is a normal,

the module is defective.

When reconnecting the A/V B /D, make sure to change the switch to external

signals.

- The most common module defect is the appearance of a lack or right

vertical line.

1 2 3 4

down

--8--

- Bar

This occ urs when the FPC wire, which connects the address line elow the

module, is damaged. Because the wi re is on the ottom, it can e e asily

damaged when the module is lifted and assem led or from external shock. Use

caution when handling the module and use the handle on the ottom of the

module to lift or move.

If the vertical ar appears at the same location for all modes, the F PC wire is

damaged.

FPC wire cannot e replaced. The entire module needs to e replaced.

- If the module does not power on, it is mostly likely due to an open fuse on the

power B/D. Check the lack and round fuse on the power B/D.

2) Diagnosis y Pro lem Ty pe

- Power comes on, ut the picture does display

Check the AV B/D ’s communication lines, SDL and SDA lines.

ICs c ontrolled y the SDA and SCL line are ADC9883, F LI2310, MSP 3450G,

VPC3230, 3D com filter, and TA8851. If after powering on, the SDA and SCL

line’s Vp- p is less than 4V and checks elow 2.5V, the communication line is

loaded at some point. Open and check each IC’s communication line.

- Can also occur when the connection etween the graphic B/D and video B/D is

ad.

- If the picture turns off or the volume is muted while viewing through the set-

top ox, please check the status of the set-top ox first.

- For a normal picture when using P IP/POP function, refer to the s ection on

Video Mode in the manual

- If the OSD screen cracks or displays a normally:

May e caused y ad connection etween the graphic B/D’s sc aler a nd

SDRAM, K4S643232C (UF B 01, UFB02). Use the clea ner to clean the around

the scaler and the UFB01/02.

OSD is processed y the scaler (ASI 500).

- If the power is on and the input signals and connections are normal, ut the

picture does not display:

--9--

Plasma Display PD421

AIN

OUTA

MIDSCV

SYNC

PROCESSING

AND CLOCK

GENERATION

HSYNC

COAST

CLAMP

FILT

DTACK

HSOUT

VSOUT

SOGOUT

REF REF

BYPASS

SERIAL REGISTER

AND

POWER MANAGEMENT

SCL

SDA

AD9883

CLAMP 8

A/D

GENERAL DESCRIPTION

The AD9883 is a complete 8- it, 110 MSPS monolithic analog

interface optimized for capturing RGB graphics signals from

personal computers and workstations. Its 110 MSPS encode

rate capa ility and full-power analog andwidth of 300 MHz

supports resolutions up to SXGA (1280X 1024 at 60Hz).

The AD9883 includes a 110 MHz triple ADC with internal

1.25 V reference, a PLL, and programma le gain, offset, and

clamp control. The user provides only a 3.3 V power supply,

analog input, and HSYNC and COAST signals. Three- state

CMOS outputs may e powered from 2.5 V to 3.3 V.

The AD9883’s on-chip PLL generates a pixel clock from HSYNC

and COAST inputs. Pixel clock output freque ncies range from

12 MHz to 110 MHz. PLL clock jitter is 500 ps p-p typical at

10 MSPS. When the COAST signal is presented, the PLL

maintains its output frequency in the a sence of HSYNC. A

sampling phase adjustment is provided. Data, HSYNC and

Clock output phase relationships are maintained. The AD9883

also offers full sync processing for composite sync and sync-on-

green applications.

A clamp signal is generated internally or may e provided y the

user through the CLAMP input pin. This interface is fully pro-

gramma le via a two-wire serial interface.

Fa ricated in an advanced CMOS process, the AD9883 is

provided in a space-saving 80-lead LQFP surface mount plastic

ackage and is specified over th e 0 C to 70 C temperature range.

Sync Detect fo Hot ugg ng

Midscale Clamping

Power-Down Mode

Low Power : 500mW tYPICAL

Composite Sync Applications Require an External Coast

MC68HC705BD7B

AD9883

Critical Parts Specification

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