Icom IC-2SET Bedienungsanleitung

ICOM

SERVICE

MANUAL

144MHz FM TRANSCEIVER

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INTRODUCTfON

This service manual describes the latest service information for the

IC-2SAT/SET 144 MHz FM TRANSCEIVER at the time of going to press.

5versions of the IC‘2SAT/SET have been designed. This service manual

covers each version.

VERSION NUMBER VERSION MODEL

if 02 Europe IC-2SET

if04 Italy

#05 U.S.A,

#07 Ausiralia IC-2SAT

#09 Asia

To upgrade quality, any electric or mechanical pari and internal circuits are

subject to change without notice or obligation

DANGER

NEVER connect the transceiver to an AC outlet or to aDC power supply that

uses more than 16 V. This will ruin the transceiver.

DO NOT expose the transceiver to rain, snow or any liquids,

DO NOT reverse the polarities of the power supply when connecting the

transceiver.

DO NOT apply an RF signal of more than 20 dBm (100 mW) to the antenna

connector. This could damage the transceiver's front end,

ORDERING PARTS

Be sure to include the following four points when ordering replacement parts;

1.10-digit order numbers

2. Component part number and name

3. Equipment model name and unit name

4. Quantity required

<SAMPLE ORDER

1150000730 1C SCI 096 1C-3SAT MAIN UNIT 5pieces

8810005720 Screw PH BO W2 x20 2K IC-2SAT Rear panel 10 pieces

Addresses are provided on the inside back cover for your convenience.

REPAIR NOTE

1. Make sure aproblem is internal before disassembling the transceiver.

2. DO NOT open the transceiver until the transceiver is disconnected from a

power source.

3. DO NOT force any of the variable components. Turn them slowly and

smoothly.

4. DO NOT short any circuits or electronic parts, An Insulated tuning tool

MUST be used for all adjustments,

5. DO NOT keep power OIM for along time when the transceiver is defective.

6. DO NOT transmit power inlo asignal generator or asweep generator.

7. ALWAYS connect a30 dB"“40 dB attenuator between the transceiver and

adeviation meter or spectrum analyzer when using such test equipment.

8. READ the instructions of test equipment thoroughly before connecting

equipment to the transceiver.

TABLE OF CONTENTS

SECTION 1SPECIFICATIONS 1—1

SECTION 2INSIDE VIEWS 2—1

SECTION 3BLOCK DIAGRAM 3—1

SECTION 4CIRCUIT DESCRIPTION 4—1~6

-1RECEIVER CIRCUITS 4—1

4-2 TRANSMITTER CIRCUITS 4—2

4-3 PLL CIRCUITS 4—3

4-4POWER SUPPLY CIRCUITS 4—4

4-5OTHER CIRCUITS 4—4

4-6CPU PORT ALLOCATIONS (LOGIC UNIT) 4—5

SECTION 5MECHANICAL PARTS AND DISASSEMBLY 5—1~2

5-1FRONT PARTS 5—1

5-2CHASSIS PARTS 5—2

SECTION 6ADJUSTMENT PROCEDURES 6—1~5

6-1PREPARATION BEFORE SERVICING 6—1

6-2 PLL ADJUSTMENT 6—2

6-3 RECEIVER ADJUSTMENT 6—3

4TRANSMITTER ADJUSTMENT 6—4

SECTION 7BOARD LAYOUTS 7-1-10

7-1LOGIC (LGC) UNIT 7—1

2MAIN (MIN) UNIT 7—4

7-3 MBD AND AF UNITS 7—6

7-4 10 AND MIC UNITS 7—7

7-5 DET AND REG UNITS 7—8

7-6 RF AND APC UNITS 7—9

7-7 PLL AND PRT UNITS 7—10

SECTION 8PARTS LIST 8-1-7

SECTION 9OPTIONAL UNITS 9-1-3

9-1UT-50 TONE SQUELCH UNIT 9—1

9-2 UT-51 TONE ENCODER UNIT 9—2

9-3 UT-49 DTMF DECODER UNIT 9—3

SECTION 10 VOLTAGE DIAGRAM 10 —1

SECTION 1SPECIFICATIONS

GENERAL

•Frequency coverage

•Mode

•Selectable tuning step

•Memory channels

•Antenna impedance

•Power supply requirement

•Current drain (at 13.8 VDC)

•Usable temperature range

•Frequency stability

•Dimensions

•Weight

TRANSMITTER

•Output power (at 13.8 VDC)

•Modulation system

•Max. frequency deviation

•Spurious emissions

•Microphone impedance

RECEIVER

•Receive system

•Intermediate frequencies

•Sensitivity

•Selectivity

•Spurious rejection ratio

•Audio output power

•Audio output impedance

MODEL VERSION FREQUENCY

COVERAGE

IC-2SAT U.S.A.

140.00~150.00 MHz*

Asia

IC-2SET Italy

IC-2SAT Australia 144.00~148.00 MHz

IC-2SET Europe 144.00—146.00 MHz

‘Specifications apply to only 144.00~148.00 MHz.

F3 (FM)

5, 10, 12.5, 15, 20, 25 and 50 kHz

48 plus acall channel

50 0

6~16 VDC negative ground or battery packs BP-81 ~BP-85 or battery case BP-90

Receive 16mA (power saved)

250 mA (max. audio output)

Transmit 650 mA (LOW 1)

1500 mA (HIGH)

-10 “C~-F60 °C(-f 14 °F~-F140 T)

±15 ppm (-10 “C-+60 °C)(-M4 T-+140 ”F)

49 (W) X102.5 (H) X35 (D) mm

1.9 (W)x4.0 (H)x 1.4 (D) in

(Projections not included)

280 g(9.9 oz)

High 5.0 W

Low 3.5/1 .5/0.5 W(selectable)

Variable reactance frequency modulation

±5 kHz

Less than -60 dB

2kO

Double-conversion superheterodyne

1st 30.875 MHz

2nd 455 kHz

0.18 pV for 12 dB SINAD

More than 15kHz/-6dB

Less than 30kHz/-60dB

More than 60 dB

More than 200 mW at 10 %distortion with an 8Qload

All stated specifications are subject to change without notice or obligation.

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1—1

SECTION 2INSIDE VIEWS

MAIN UNIT

RF amplifier circuit (RF UNIT)-

-1st IF filter (Fit :30M16B)

AF amplifier circuit (AF UNIT)

ARC circuit fAPC UN1T)-

2rd LO crystal (X2: CR-214 30.42 MHz)

Demodulator circuit {DET UNIT)

Power module {IC1 :SC1096)=

Microphone amplifier circuit {MIC UNIT)

PLL circuit (PLL UNIT)

Internal NiCd battery^

(BT1: P^03ER/F23G1)

Charging circuit {PRT UNIT)-

LOGIC UNIT

CPU clock

{XI; CSB800J220 798.642 kHz) -CPU (IC1: HD404608A21H)

Microphone (MCI :WM-62A)-

Lifhium backup battery^

(BT1: CL202O-1VC)

Buili4n clock crystal

{X2: DT-26S 32.768 kHz)

CPU resetyCPU power supply circuit

(RES BOARD)

Keyboard (LGC BBOARD)

DET

UNIT

main

unit

SECTION 3BLOCK DIAGRAM

3—1

LOGIC

UNIT

SECTION 4CIRCUIT DESCRIPTION

4-1 RECEIVER CIRCUITS

4-1-1 ANTENNA SWITCHING CIRCUIT

(MAIN AND APC UNITS)

Received signals enter the antenna connector and pass

through aiow-pass filter (L2~L4, C21~C25). The signals

are applied to the antenna switching circuit (D7, D9, L5,

L6, and C26~C28) and then to the RF UNIT via the RFIN

signal line. The antenna switching circuit employs a

two-stage A/4-type diode switching system.

The antenna switching circuit functions as alow-pass

filter while in receiving and becomes very high impedance

while in transmitting.

4-1-2 RF CIRCUIT (RF UNIT)

The signals from the antenna switching circuit pass

through abandpass fiiter (LI, D2), and are applied to

the RF amplifier (Q1, Q2).

Amplified signais are reappiied to the other bandpass

filter (L2, L3, D4, D5) to suppress unwanted signals.

The signals are applied to the 1st mixer circuit (MAIN

UNITQ1).

D2, D4 and D5 are varactor diodes that track the band-

pass filters and are controlled by the PLL lock voltage.

These diodes tune the center frequency of the bandpass

filters for wide bandwidth reception and good image

response rejection.

4-1-3 1ST MIXER CIRCUIT (MAIN UNIT)

The signals from the RF circuit are mixed with the 1st LO

signal from the PLL UNIT to produce a30.875 MHz 1st

IF signal.

4-1-4 1ST IF CIRCUIT (MAIN AND DET UNITS)

After passing through the matching circuit (LI), the 1st IF

signal is applied to apair of crystai filters (FI1) to suppress

out-of-band signals. The 1st IF signal enters the DET

UNIT and is amplified at the IF amplifier (Q2) and then

applied to the 2nd mixer circuit.

4-1-5 2ND IF AND DEMODULATOR

CIRCUITS (DET UNIT)

The 1st IF signal from Q2 is appiied to the 2nd mixer

section of IC1, and is mixed with the 2nd LO signal to be

converted to a455 kHz 2nd IF signal.

IC1 contains the 2nd mixer, local oscillator, limiter

ampiifier and quadrature detector circuits. The local

oscillator section and X2 generate 30.42 MHz for the

2nd LO signal.

The 2nd IF signal from the 2nd mixer (101, pin 4) passes

through the ceramic filter, FI1, where unwanted signals

are suppressed. It is then amplified at the limiter amplifier

section (Id, pin 6) and applied to the quadrature detector

section (101, pin 10 and ceramic discriminator XI) to

demodulate the 2nd IF signal into an AF signal.

AF signal output from Id pin 1 1 is applied to the squelch

circuit and de-emphasis circuit (R7, 024, 025). This de-

emphasis circuit is an integrated circuit with frequency

characteristics of -6 dB/octave. The resulting signal is

applied to the AF amp, optional tone squelch and optional

DTMF decoder circuits.

RECEIVER CIRCUIT BLOCK DIAGRAM

4—1

4-1-6 AF AMP CIRCUIT (AF AND VR UNITS)

The AF signal is applied to Q1 and Q2 on the AF UNIT.

Q1 is an active filter that functions as ahigh-pass filter

to suppress tone signals for the tone squelch operation.

Q2 is also an active filter that functions as alow-pass

filter to suppress higher noise signals.

The filtered signal is applied to the [VOL] control (R1)

on the VR UNIT via the AF mute circuit (Q3). When the

squelch is closed, Q3 cuts the AF signal as the AF mute

switch. The AF signal is power-amplified at the AF

power amplifier (ICt) to drive the speaker.

The AF voltage regulator (Q4~Q6) supplies power to

the AF power amplifier. The AFS signal from the MAIN

UNIT controls Q6 and mutes AF output while receiving

no signal or no specified tone/DTMF signal.

4-1-7 SQUELCH CIRCUIT (DET UNIT)

Some of the noise components in the AF signal from IC1

pin 11 are applied to IC1 pin 13 via C11, R8, Cl 3and

C14. The [SQL] control (R2) on the VR UNIT adjusts the

pin 13 input level.

The active filter section in IC1 amplifies noise components

of frequencies of 20 kHz and above, and outputs the

resulting signals from pin 14. Output signals are rec-

tified by D1 and are converted to DC voltage.

The rectified voltage triggers the squelch switch (Q1).

The coliector of Q1 outputs the squelch signal. The

signal is applied to the CPU (IC1, pin 27) on the LOGIC

UNIT through the BUSY signal line. The CPU outputs the

RMUTE and BUSY LED signals.

The RMUTE signal, decoded at the output expander

(IC1) on the 10 UNIT, activates the AF mute circuit (03)

on the AF UNIT to cut the AF signal. The BUSY LED

signal is applied to 01 on the LOGIC UNIT, turning OFF

the receive indicator.

4-2 TRANSMITTER CIRCUITS

4-2-1 MICROPHONE AMPLIFIER (MIC UNIT)

AF signals from the built-in condenser microphone or

from the [MIC] jack are applied to IC1 pin 3, and are

pre-emphasized to -F6 dB/octave through C6 and R4

connected to pin 2. IC1 functions as the microphone

amplifier and the limiter.

The output signals from IC1 pin 1pass through the

splatter filter circuit (IC1 pins 5and 6) where signals

of 3kHz and above are attenuated. IC1 pin 7then

outputs the signals. The signals are applied to the

modulation circuit (PLL UNIT, D2) in the VCO to produce

an FM signal.

The VCO circuit (02, L2, D2) on the PLL UNIT oscillates

the transmit frequency with AF signal modulation.

4-2-2 DRIVE AMPLIFIER (MAIN UNIT)

The VCO output, buffer-amplified at 05 on the PLL

UNIT, is applied to the the transmit/receive switching

circuit (D14) on the MAIN UNIT. The VCO output is then

amplified at the predrive amplifier (07) and the drive

amplifier (06).

The voltage controlled by the APC circuit is applied to the

collector of 06 and 07 to protect the RF power module

from damage by an antenna mismatch.

4-2-3 RF POWER AMPLIFIER (MAIN UNIT)

IC1 is apower module which provides stable 5Woutput

power.

An RF signal from the drive amplifier (06) is applied to

IC1 pin 1. The amplified signal is output from pin 4,

and applied to the antenna connector through the diode

switching and low-pass filter circuits.

TRANSMITTER CIRCUIT BLOCK DIAGRAM

Fig. 2

4—2

4-2-4 APC CIRCUIT (MAIN AND APC UNITS)

The APC circuit protects the power module (IC1) from

amismatched output load and selects HIGH and LOW

output power.

The output power level from the power module (IC1) is

detected at the APC detector (D10~D12). When antenna

impedance is matched at 50 Q, the detected level is

at aminimum. However, when antenna impedance is

mismatched, the detected voltage is higher than when

matched.

When the antenna impedance is mismatched, the base

voltage of Q3b (APC UNIT) Is higher than the other base

voltage of Q3a (reference voltage). Q3b decreases the

collector current of Q1 using Q2. Collector current of

Q1 is used at the drive amplifiers (Q6, Q7) on the MAIN

UNIT. Hence, when the antenna Impedance is mis-

matched, the output power is decreased.

The output power selecting circuit uses the APC circuit.

The PCON voltage from the lO UNIT shifts the reference

voltage, changing the output power to HIGH or LOW

1~3.

4-2-5 ANTENNA SWITCHING CIRCUIT

(MAIN UNIT)

When transmitting, D7 and D9 are turned ON. The RF

output signal is not applied to the receiver circuit, passing

through D9 and C60, the low-pass filter (L2~L4, C21

~C25) and then to the antenna. The low-pass filter

suppresses high harmonic components.

4-3 PLL CIRCUITS

4-3-1 GENERAL (PLL UNIT)

The PLL circuit, using aone chip modulus prescaler (IC1),

directly generates the transmit frequency with the Tx

VCO (Q2) and the 1st LO frequency with the Rx VCO (01).

The modulus prescaler (IC1) sets the dividing ratio based

on serial data from the CPU, and compares the phases

of aVCO signal and the reference oscillator frequency.

It detects the out-of-step phase and outputs it. The

reference frequency is oscillated at XI

4-3-2 REFERENCE OSCILLATOR CIRCUIT

(PLL UNIT)

Areference frequency is produced by the local oscillator

section of IC1 and XI. C22 provides frequency control.

4-3-3 LOOP FILTER CIRCUIT (PLL UNIT)

Phase-detected signals from IC1 pin 13 are converted to

DC voltage by alag-lead loop filter (R17, R18, C28, C29).

The frequency at which the VCO oscillates is controlled

by varactor diodes (D1, D2). DC voltage (PLL lock

voltage) is provided through the buffer amplifier (06).

01 0provides Rx bandpass filter tuning.

PLL CIRCUIT

IC1 M54959FP

PLL

OUTPUT

XI Fig. 3

4-3-4 VCO CIRCUIT (PLL UNIT)

IC-2SAT/SET has 2VCO circuits for transmitting and

receiving. IC1 pins 10 and 11 output control signals

for selecting the receive VCO circuit (Q1, LI, D1) or

transmit VCO circuit (02, L2, D2). Varactor diodes (D1,

D2) provide frequency control. The buffer amplifiers

(Q3~Q5) do not affect the PLL output signal from VCO

oscillation. 07 selects the transmit or receive VCO

circuit.

4-3-5 UNLOCK SENSOR CIRCUIT (PLL UNIT)

When the PLL circuit is unlocked, IC1 pin 14 is “HIGH”

and the “HIGH" signal is applied to the CPU pin 7as an

unlock signal.

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4-4 POWER SUPPLY CIRCUITS

4-4-1 VOLTAGE LINES

LINE DESCRIPTION

Vcc The internal or attached battery pack voltage

or external DC power passed through the

power switch.

-1-5 Common 5Vconverted from the Vcc line at Q1

and Q2 on the REG UNIT using IC1 as the

reference voltage.

-I-5S 5Vcontrolled by the power saver function.

This voltage is converted from Vcc at 03 and

04 on the REG UNIT using IC2 output as the

reference voltage.

R-I-5S Receive 5Vcontrolled by the power saver

function and SEND signal line. This voltage is

converted from Vcc at 05 and 06 on the REG

UNIT using IC3 output as the reference

voltage.

T-l-5 Transmit 5Vcontrolled by the TMUTE signal

line. This voltage is converted from Vcc at 04

and 05 on the APC UNIT.

AF 7VAF amp power source controlled by the AFS

signal line. R14/R15 provides reference

voltage.

4-4-2 CPU POWER SUPPLY CIRCUIT

(LOGIC UNIT)

When the power switch is turned OFF and the

internal/externai battery pack is discharged, avoltage is

appiied to the CPU (IC1) pin 73 via R29 from the iithium

backup battery (BT1) installed In the transceiver to provide

backup for the memory contents.

When the internai or attached battery pack voltage or

external DC power is applied to the transceiver, BT1 is

charged using the current regulator (C3).

4-4-3 +5S AND R+5S SWITCHING

CIRCUITS (REG UNIT)

The IC-2SAT/SET has apower saver to reduce current

consumption to approx. 1/4.

The PSC (Power Saver Control) signal is applied to IC2.

IC2 controls +5S regulator (G3, C4, D1) to turn CN and

CFF +5S voltage.

PSC and SEND signals are applied to ICS. ICS controls

R-t-5S regulator (05, Q6, D2). R+5S turns OFF during

power saved period or transmitting.

4-4-4 CHARGING CIRCUIT (PRT UNIT)

Voltage from the [DC 13.8V] jack is applied to current

control circuit (01, 02, D5, D6) to charge an internal or

attached battery pack (except the BP-85).

When the external battery pack is attached, the current

from D2 charges the attached battery pack. When the

external battery pack is removed, the current from D2

charges the internal battery pack.

The mechanical switch (MP7) selects the battery packs.

This circuit charges one of the battery packs in approx. 15

hours.

Over voltage protector (D4) decreases the transceiver

circuit damage from over voltage and reverse polarity

connections of the power supply.

4-5 OTHER CIRCUITS

5-1 S/RF INDICATOR CIRCUIT

(DET, MAIN AND LOGIC UNITS)

Aportion of the 2nd IF signal is output from IC1 pin 12

on the DET UNIT via the SD signal line. The signal is

rectified at D1 on the MAIN UNIT to obtain an S-indicator

signal. The S-indicator signal is applied to IC2b pin 5

on the LOGIC UNIT.

IC2b pin 6receives an S-indicator reference signal from

the CPU KEYSO—3 terminals via the D/A converter (R11,

R37~R40). The CPU terminals increase the reference

signal level.

When the D/A converted level becomes greater than the

indicator level, IC2b pin 7becomes “LOW.” The CPU

detects the signal strength level using the KEYS0~3

terminal outputs and indicates the signal strength level

on the function display when receiving the “LOW” signal.

While transmitting, the S/RF indicator indicates the

selected output power.

SINDICATOR CIRCUIT

4-5-2 DISPLAY BACKLIGHT CIRCUIT

(LOGIC UNIT)

When the [LIGHT] switch is pushed, pin 77 of the CPU

outputs “HIGH.” The signal is applied to 01 to light up

the backlight LEDs (DS2, DS3).

4—4

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