Infineon SPI DMA 1 Bedienungsanleitung
Scope of work
QSPI is used to conduct SPI Master Slave communication using the
DMA module.
This example implements an SPI full duplex communication.
QSPI2 is configured as an SPI master and QSPI3 is configured as an SPI
slave. Both master and slave exchange eight bytes of data.
Four DMA channels are used to enable data transfer between RAM and
QSPI FIFOs without CPU intervention:
›DMA channel 1 is configured as SPI master Tx
›DMA channel 2 is configured as SPI master Rx
›DMA channel 3 is configured as SPI slave Tx
›DMA channel 4 is configured as SPI slave Rx
An LED is used to signal the successful data communication.
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2020-01-17 Copyright © Infineon Technologies AG 2020. All rights reserved.
Introduction
›The Queued Synchronous Peripheral Interface (QSPI) enables any
synchronous serial communication with external devices based on the
standardized SPI-bus signals: clock, data-in, data-out and slave select.
›The QSPI works in full duplex mode either as Master or Slave with up to
50 Mbit/s.
›The DMA module channels can be configured to transfer data from/to
QSPI FIFOs to/from internal RAM Memory without any CPU intervention.
›This example is based on the Infineon Low Level Drivers to demonstrate
SPI Master Slave Communication with minimum CPU intervention.
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2020-01-17 Copyright © Infineon Technologies AG 2020. All rights reserved.
Hardware setup
This code example has been
developed for the board
KIT_AURIX_TC297_TFT_BC-Step.
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2020-01-17 Copyright © Infineon Technologies AG 2020. All rights reserved.
Hardware Setup
KIT_AURIX_TC297_TFT_BC-
Step
X103 : QSPI3 (Slave)
WIRE
X102 : QSPI2 (Master)
P02.7 : 20
: SCLKI
P15.3 : 32 : SCLKO
P02.4 : 17 : SLSI_A
P15.2 : 31 : SLSO_0
P02.5 : 18 : MRST
P15.4
: 33 : MRST_A
P02.6 : 19 : MTSR_A
P15.5 : 34 : MTSR
KIT_AURIX_TC297_TFT_BC-Step
›Use the stencils as
illustrated. ›Connect following pins
as described and
illustrated using wires.
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2020-01-17 Copyright © Infineon Technologies AG 2020. All rights reserved.
Implementation
Configuring the SPI communication
The configuration of the SPI communication is done through the function initQSPI() in two
different steps:
›QSPI Slave initialization
›QSPI Master initialization
QSPI Slave initialization
›The initialization of the QSPI slave module is done by defining an instance of the
IfxQspi_SpiSlave_Config structure
›The structure is filled with default values by the function
IfxQspi_SpiSlave_initModuleConfig()
›Afterwards, the following parameters are modified to enable the DMA usage, set its
channels, interrupt priorities and IO port pins:
–DMA configuration: dma.useDma,dma.txDmaChannelId,dma.rxDmaChannelId
–Interrupts configuration: base.txPriority,base.rxPriority,base.erPriority,
base.isrProvider
–Pins configuration: pins
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2020-01-17 Copyright © Infineon Technologies AG 2020. All rights reserved.
Implementation
QSPI Slave initialization (Cont.)
›The function IfxQspi_SpiSlave_initModule() is used to initialize the QSPI slave module
›Finally, the buffers used by the QSPI slave are initialized
The functions needed to initialize the QSPI Slave can be found in the iLLD header
IfxQspi_SpiSlave.h.
QSPI Master initialization
›The initialization of the QSPI master module is done by defining an instance of the
IfxQspi_SpiMaster_Config structure
›The structure is filled with default values by the function
IfxQspi_SpiMaster_initModuleConfig()
›Afterwards, the following parameters are modified to enable the DMA usage, set its
channels, interrupt priorities and IO port pins:
–DMA configuration: dma.useDma,dma.txDmaChannelId,dma.rxDmaChannelId
–Interrupts configuration: base.txPriority,base.rxPriority,base.erPriority,
base.isrProvider
–Pins configuration: pins
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2020-01-17 Copyright © Infineon Technologies AG 2020. All rights reserved.
Implementation
QSPI Master initialization (Cont.)
›The function IfxQspi_SpiMaster_initModule() is used to initialize the QSPI
master module
›A QSPI module controls 16 communication channels, which are individually
programmable. In this example, the function initQSPI2MasterChannel() initializes
the channel zero using an instance of the structure
IfxQspi_SpiMaster_ChannelConfig. Afterwards, the slave select channel
number is set through the parameter sls.output and the baud rate is modified via
the parameter base.baudrate
›The function IfxQspi_SpiMaster_initChannel() is used to initialize the QSPI
master channel
›Finally, the buffers used by the QSPI master are initialized
The functions needed to initialize the QSPI Master can be found in the iLLD header
IfxQspi_SpiMaster.h.
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2020-01-17 Copyright © Infineon Technologies AG 2020. All rights reserved.
Implementation
Interrupt Service Routines (ISR):
›The following ISRs are implemented to ensure a proper SPI communication in
DMA mode:
–SPI Master error interrupt ISR_qspi2_Er() ISR calls the function:
–IfxQspi_SpiMaster_isrError()
–SPI Slave error interrupt ISR_qspi3_Er() ISR calls the function:
–IfxQspi_SpiSlave_isrError()
–SPI Master transmit interrupt ISR_dma_ch1() ISR calls the function:
–IfxQspi_SpiMaster_isrDmaTransmit()
–SPI Master receive interrupt ISR_dma_ch2() ISR calls the function:
–IfxQspi_SpiMaster_isrDmaReceive()
–SPI Slave transmit interrupt ISR_dma_ch3() ISR calls the function:
–IfxQspi_SpiSlave_isrDmaTransmit()
–SPI Slave receive interrupt ISR_dma_ch4() ISR calls the function:
–IfxQspi_SpiSlave_isrDmaReceive()
›The functions listed above can be found in the iLLD headers IfxQspi_SpiMaster.h
and IfxQspi_SpiSlave.h
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2020-01-17 Copyright © Infineon Technologies AG 2020. All rights reserved.
Implementation
SPI Master Slave Communication:
The SPI Master Slave communication is established through the following steps:
›Enable SPI Slave for data communication using the function:
IfxQspi_SpiSlave_exchange()
›Enable and Start SPI Master data communication using the function:
IfxQspi_SpiMaster_exchange()
›Poll for SPI slave data reception using the function:
IfxQspi_SpiSlave_getStatus()
›The received and transmitted data are compared byte by byte and the
number of errors are counted
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2020-01-17 Copyright © Infineon Technologies AG 2020. All rights reserved.
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