Intel 845 DESIGN Leitfaden
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Intel®Pentium®4 Processor in
478-pin Package and Intel®845
Chipset Platform for SDR
Design Guide Update
March 2004
Notice: The Intel®845 chipset family may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are
documented in the Specification Update.
Document Number: 250425-003
Preface
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Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for
use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel®845 chipset family may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
www.intel.com
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2002-2004, Intel Corporation
2 Design Guide Update
Preface
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Contents
Preface ............................................................................................................................................ 5
Nomenclature...................................................................................................................... 5
Codes Used in Summary Table .......................................................................................... 6
General Design Considerations ................................................................................................................. 7
Schematic, Layout, and Routing Updates .................................................................................................. 9
Documentation Changes .......................................................................................................................... 11
Design Guide Update 3
Preface
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Revision History
Rev. Draft/Changes Date
-001 Initial Release March 2002
-002 (1) Added Documentation Change #3, Replace Figure 118, Intel®
845 Chipset Platform Using PC133 SDRAM System Memory
Power Delivery Map
(2) Added Documentation Change #4, Added Section 4.6.7,
Electrostatic Discharge Platform Recommendations
(3) Added Documentation Change #5, Change Table 3, System Bus
Routing Summary for the Processor
(4) Added Documentation Change #6, Add Section 13.2, Intel®
Boxed Processor Mechanical Keep-Outs
(5) Added Documentation Change #7, Add Section 15.1.3, Intel®
Boxed Processor Mechanical Keep-Outs
(6) Added Schematic, Layout, and Routing Updates #1, Schematic
change to the 82845 MCH HSWING Circuit
May 2002
-003 (1) Added Documentation Change 8, Revise Section 4.1, Schematic
Checklist, Host Interface, PWRGOOD
March 2004
4 Design Guide Update
Preface
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Preface
This Design Guide Update document is an update to the specifications and information contained
in the Intel®Pentium®4 Processor in 478-pin Package and Intel®845 Chipset Platform for SDR
Design Guide, January 2002. This Design Guide Update may reference other documents listed in
the following Affected Documents/Related Documents table. This document is a compilation of
updates to the general design considerations; schematic, layout, and routing updates; and
documentation changes. This document is intended for hardware system manufacturers and for
software developers of applications, operating systems, and tools. The design guide (and this
design guide update) is primarily targeted at the PC market segment and was first published in
2002. Those using this design guide and update should check for device availability before
designing in any of the components included in this document.
Information types defined in the Nomenclature section of this document are consolidated into the
public design guide update document when the public design guide document is first published.
This design guide update document contains a complete list of all known information types.
Affected Documents
Document Title Document
Number
Intel® Pentium® 4 Processor in 478-pin Package and Intel® 845 Chipset Platform for
SDR Design Guide, January 2002
298354-002
Related Documents
Document Title Document
Number
Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR Datasheet, January
2002
290725-002
Intel® 82801BA (ICH2) I/O Controller Hub Datasheet 290687-002
Nomenclature
General Design Considerations include system level considerations that the system designer
should account for when developing hardware or software products using the Intel® 845 Chipset:
82845 Memory Controller Hub (MCH) for SDR.
Schematic, Layout, and Routing Updates include suggested changes to the current published
schematics or layout, including typos, errors, or omissions from the current published documents.
Documentation Changes include suggested changes to the current published design guide not
including the above.
Design Guide Update 5
Preface
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Codes Used in Summary Table
Doc: Document change or update that will be implemented.
Shaded: This item is either new or modified from the previous version of the document.
NO. Plans GENERAL DESIGN CONSIDERATIONS
There are no General Design Consideration changes in this Design Guide Update revision.
NO. Plans SCHEMATIC, LAYOUT, AND ROUTING UPDATES
1 Doc Schematic change to the 82845 MCH HSWING Circuit
NO. Plans DOCUMENTATION CHANGES
1 Doc Change Section 12.4.2, 3.3V/V5REF Sequencing
2 Doc Change Section 14.8, Power and Ground, V5REF_SUS
3 Doc Replace Figure 118, Intel® 845 Chipset Platform Using PC133 SDRAM System Memory
Power Delivery Map
4 Doc Add Section 4.6.7, Electrostatic Discharge Platform Recommendations
5 Doc Change Table 3, System Bus Routing Summary for the Processor
6 Doc Add Section 13.2, Intel® Boxed Processor Mechanical Keep-Outs
7 Doc Add Section 15.1.3, Intel® Boxed Processor Mechanical Keep-Outs
8 Doc Revise Section 14.1, Schematic Checklist, Host Interface, PWRGOOD
6 Design Guide Update
General Design Considerations
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General Design Considerations
There are no General Design Considerations in this Design Guide Update revision.
Design Guide Update 7
General Design Considerations
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8 Design Guide Update
Schematic, Layout, and Routing Updates
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Schematic, Layout, and Routing Updates
1. Schematic Change to the 82845SDR MCH HSWING Circuit
Reference Appendix A, Customer Reference Board Schematics, of the Intel® Pentium® 4
Processor in 478-Pin Package and Intel® 845 Chipset Platform for SDR Design Guide, 298354-
002, dated January 2002. Sheet 11 of the “Intel® 845 SDR Schematics Rev 1.3” contains a circuit
at grid location C-7. This circuit has a VCCP input and an HSWING output. Capacitor C5D6 is
shown as a series capacitor between VCCP and the HSWING output. This circuit is not correct as
shown.
Capacitor C5D6 is a decoupling capacitor. It should connect the HSWING output of this circuit to
GND so that resistor R5D5 and capacitor C5D6 are in parallel.
Sheets
62,61,60,59,46,18,17,11,10,9,7,6,5
VCCP IN
R5D7
R5D5
C5D6
HSWING OUT
Sheet 9
Design Guide Update 9
Schematic, Layout, and Routing Updates
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10 Design Guide Update
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3
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