Intel Stratix 10 Bedienungsanleitung

Intel® Stratix® 10 Device Security

User Guide

Updated for Intel® Quartus® Prime Design Suite: 19.1

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Contents

1. Intel® Stratix® 10 Device Security Overview...................................................................4

1.1. Intel Stratix 10 Secure Device Manager (SDM).......................................................... 6

1.2. Intel Stratix 10 Base Security..................................................................................7

1.2.1. Side Channel Resistance............................................................................. 7

1.3. Owner Security Keys and Programming.................................................................... 8

1.3.1. eFuse (Volatile or Non-Volatile) AES Root Key................................................ 8

1.3.2. BBRAM (Volatile) AES Root Key....................................................................8

2. Design Authentication.....................................................................................................9

2.1. The Configuration Bitstream ...................................................................................9

2.2. Signature Block................................................................................................... 11

2.2.1. Authentication for HPS Software................................................................ 13

3. Using the Authentication Feature..................................................................................14

3.1. Step 1: Creating the Root Key............................................................................... 15

3.2. Step 2: Creating the Design Signing Key.................................................................15

3.3. Step 3: Appending the Design Signature Key to the Signature Chain...........................16

3.4. Step 4: Signing the Bitstream................................................................................17

3.4.1. Step 4a: Signing the Bitstream Using the Programming File Generator............ 17

3.4.2. Step 4b: Signing the Bitstream Using the quartus_sign Command.................. 19

3.5. Step 5: Programming the Owner Public Root Key for Authentication............................20

3.5.1. Step 5a: Programming the Owner Public Root Key Using the Intel Quartus

Prime Programmer................................................................................... 20

3.5.2. Step 5b: Calculating the Owner Public Root Key Hash................................... 22

4. Co-Signing Device Firmware Overview..........................................................................23

4.1. Using the Co-Signing Feature................................................................................ 23

4.1.1. Prerequisites for Co-Signing Device Firmware.............................................. 24

4.1.2. Generating the Owner Firmware Signing Key............................................... 24

4.1.3. Co-Signing the Firmware ..........................................................................25

4.1.4. Programming the Co-Signed Firmware eFuses .............................................25

4.1.5. Powering On In JTAG Mode After Implementing Co-Signed Firmware...............27

4.1.6. Canceling Intel Firmware ID...................................................................... 27

5. Signing Command Detailed Description........................................................................ 30

5.1. Generate Private PEM Key..................................................................................... 31

5.2. Generate Public PEM Key.......................................................................................31

5.3. Generate Root Signature Chain.............................................................................. 31

5.4. Append Key to Signature Chain..............................................................................31

5.5. Sign the Bitstream............................................................................................... 32

5.6. Calculate Public Root Key Hash from QKY................................................................ 33

6. Encryption and Decryption Overview............................................................................ 34

6.1. Using the Encryption Feature.................................................................................35

6.1.1. Step 1: Preparing the Owner Image and AES Key File................................... 36

6.1.2. Step 2a: Generating Programming Files Using the Programming File

Generator............................................................................................... 36

6.1.3. Step 2b: Generating Programming Files Using the Command Line Interface .... 38

Contents

Intel® Stratix® 10 Device Security User Guide Send Feedback

6.1.4. Step 3a: Specifying Keys and Configuring the Encrypted Image Using the

Intel Quartus Prime Programmer ...............................................................38

6.1.5. Step 3b: Programming the AES Key and Configuring the Encrypted Image

Using the Command Line.......................................................................... 40

7. Using eFuses ................................................................................................................ 41

7.1. Fuse Programming Input Files............................................................................... 43

7.1.1. Fuse File Format...................................................................................... 44

8. Document Revision History for Intel Stratix 10 Device Security User Guide..................45

Contents

Send Feedback Intel® Stratix® 10 Device Security User Guide

1. Intel® Stratix® 10 Device Security Overview

Intel® Stratix® 10 devices provide flexible and robust security features to protect

sensitive data, intellectual property, and the device itself under both remote and

physical attacks.

Intel Stratix 10 devices provide two main categories of security features:

authentication and encryption.

Authentication ensures that both the firmware and the configuration bitstream are

from a trusted source. Authentication is fundamental to Intel Stratix 10 security. You

cannot enable any other Intel Stratix 10 security features without enabling owner

authentication. Integrity checking which is part of authentication prevents accidental

bitstream change, corruption, or malicious attack.

Encryption prevents theft of intellectual property. Encryption protects confidential

information in the owner configuration bitstream.

Here are the specific security features that Intel Stratix 10 devices provide:

Authentication Category

• Elliptic Curve Based Public-Key Authentication: This feature allows the device to

authenticate Intel firmware and the configuration bitstream. Intel Stratix 10

devices always require firmware authentication for all Intel firmware that loads

into silicon. This requirement ensures that Intel is the only source that provides

the primary firmware for the Secure Device Manager (SDM) and most other

firmware that runs on other configuration processors in the Intel Stratix 10 device.

Intel Stratix 10 devices do not require authentication for the owner configuration

bitstream. You enable authentication for your configuration bitstream through

eFuse settings. After you program the hash of the root public key into eFuses, the

Intel Stratix 10 device only accepts an owner configuration bitstream that is

signed with corresponding private signing key.

• Anti-tampering security feature: Anti-tampering addresses physical attacks on

silicon. There are two categories of anti-tampering features: passive and active

anti-tampering.

— The passive anti-tampering feature enforces physical security features using

redundancy and interlocking systems. Passive anti-tampering is always

running on Intel Stratix 10 devices. Passive anti-tampering functions do not

operate in response to a particular function.

— Active anti-tampering responds when the silicon detects physical attacks from

the outside. By default, all active anti-tampering functions are off. When the

active anti-tampering function is on, you can select which detection functions

and responses to enable.

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Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or

other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in

accordance with Intel's standard warranty, but reserves the right to make changes to any products and services

at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Intel. Intel

customers are advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

ISO

9001:2015

Registered

Encryption Category

• Advanced Encryption Standard (AES)-256 encryption: This feature protects the

owner configuration bitstream intellectual property (IP) or confidential data as part

of root security in the owner configuration bitstream. AES-CTR (counter) mode is

the base for bitstream encryption. To reduce AES key exposure from random

attacks, AES decryption only operates on data that has already passed public key

authentication.

• Side channel protection: Side channel protection prevents AES Key and

confidential data under non-intrusive attack. Intel Stratix 10 devices include the

following functions to protect side channel leakage from silicon.

— A key update function protects the AES keys in bitstream decryption.

— The authentication first flow protects against unnecessary key exposure.

— Long route data line scrambling protects against side channel leakage over

data lines.

— A 256-bit wide direct key bus loading limits unauthorized access to keys.

— Key scrambling in the key vault protects key values.

• Multiple AES root key choices: Intel Stratix 10 devices support three different

types of root AES keys: eFuse, BBRAM, and physically unclonable function (PUF).

• Black key provisioning: Key provisioning, especially secret key provisioning, is

costly. In addition, key provisioning is the least secure step in the encryption

process. Black key provisioning creates a direct secure channel between your

custom hardware security module (HSM) and the Intel Stratix 10 device for key

provisioning. Having a secure channel ensures confidential information including

the AES key are provisioned into silicon without exposure to an intermediate party.

As a side benefit, black key provisioning also helps secure the supply chain at

contract manufacturing facilities.

Note: These security features are available in Intel Stratix 10 devices that support advanced

security. The ordering codes for Intel Stratix 10 devices that include advanced security

features includes the AS (Advanced Security) suffix. Please contact your Intel

Programmable Solutions representative to get additional information about Intel

Stratix 10 device security features.

Related Information

Intel Quartus® Prime Pro Edition User Guide Programmer

Describes operation of the Intel Quartus® Prime Pro Edition Programmer, which

allows you to configure Intel FPGA devices, and program CPLD and configuration

devices, via connection with an Intel FPGA download cable.

1. Intel® Stratix® 10 Device Security Overview

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1.1. Intel Stratix 10 Secure Device Manager (SDM)

The Secure Device Manager (SDM) is a triple-redundant processor-based module that

manages the configuration and security features of Intel Stratix 10 devices. The SDM

authenticates and decrypts configuration data.

Figure 1. Secure Device Manager

Configuration

Sector

Configuration

Sector

Configurable Network Interface

SDM Pins

Secure Device Manager

Dual Purpose I/O

Intel Stratix 10 FPGA

Intel Stratix 10 SX Blocks

Intel Stratix 10 GX Blocks

Intel Stratix 10 TX Blocks

Intel Stratix 10 MX Blocks

Additional blocks in the

Intel Stratix 10 device variants:

SX: Includes Hard Processor System

MX: Includes High-Bandwidth Memory

TX: Includes High-Bandwidth XCVRs

GX: General Purpose FPGA

Configuration

Sector

Configuration

Sector

Configuration Network

Local Sector

Manager (LSM)

Local Sector

Manager (LSM)

Local Sector

Manager (LSM)

Local Sector

Manager (LSM)

Authentication includes the following steps:

1. First, the SDM performs an integrity check using SHA-256 or SHA-384. The

integrity check ensures that the bitstream is not corrupted due to an accidental

occurrence such as a bad write to flash.

2. Then, the authentication process guarantees that a trusted source, the device

owner, created the configuration bitstream.

3. If successful, and you have enabled AES Encryption, the SDM then decrypts the

data. The SDM drives the decrypted data on the configuration network to Local

Sector Managers (LSM) on the configuration network. Each LSM parses the sector

configuration block data and configures the logic elements in the sector that it

manages.

Related Information

Intel Stratix 10 Configuration User Guide: Secure Device Manager

1. Intel® Stratix® 10 Device Security Overview

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Intel® Stratix® 10 Device Security User Guide Send Feedback

1.2. Intel Stratix 10 Base Security

To enable base security features, you must program the hash of the owner public root

key eFuse into Intel Stratix 10. As soon as you program the owner root key you have

created an Intel Stratix 10 device with basic security. Your configuration bitstream

must be signed.

Note: The fusing process automatically computes the hash of the owner public root key.

When you program the owner public root key, the programmer automatically

programs the hash value, not the full key.

You can enable the following additional security options to further enhance the

security level:

• Advanced Encryption Standard (AES) Encryption protects your IP and secures your

data. This option includes multiple sub-options relating to side channel mitigation.

• Configuration firmware joint signature capability allows you to sign the version of

configuration firmware to run on your device. At all times, the device only loads

firmware that Intel has authenticated. An eFuse on the Intel Stratix 10 device

enables this feature.

eFuse programming sets a minimum-security strength. All eFuse enforced security

options are permanent. In contrast to permanent security features, Intel Stratix 10

devices include some dynamic security options that you can control without using

eFuses. JTAG Secure is one example of a dynamic security feature. Intel Stratix 10

devices control dynamic security options by setting optional fields in the configuration

bitstream. Intel recommends using the optional fields in the configuration bitstream to

enforce security options when available. The optional fields provide a similar security

level as the eFuse setting with more flexibility.

1.2.1. Side Channel Resistance

Side channel resistance technology helps prevent secret leakage from the

Intel Stratix 10 device. Side channel mitigation is not limited to the AES engine. Any

circuit which could transport secret key material has its associated mitigation. Long

data transmission lines in silicon also implement security control agreement

mitigation.

The following side channel mitigation features are available in Intel Stratix 10 devices:

• AES side channel mitigation

— Key update: Limits to the amount of data encrypted by each key. The default

limit each key can encrypt is 4 KB.

— Authentication first: The device authenticates the bitstream before decrypting

it. Attackers cannot perform differential attacks on the AES before breaking

authentication.

• Datapath random number scrambling

• Physically unclonable function (PUF) enrollment and extraction scrambling

• 256-bit point-to-point Key bus

1. Intel® Stratix® 10 Device Security Overview

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1.3. Owner Security Keys and Programming

Intel Stratix 10 devices support two types of security keys:

• Owner public root key hash: Programming this key enables the base security

features. The Intel Stratix 10 stores the SHA-256 or SHA-384 hash of this key in

eFuses or virtual eFuses. This key authenticates the final owner design signing key

through the public signature chain.

• Owner AES key: This optional key decrypts the encrypted owner image during the

configuration process. You can store the AES key in virtual or physical eFuses, a

BBRAM, or a PUF. You program the AES key using JTAG. The configuration

bitstream specifies the owner AES key location. For extra security, you can

program fuses to enforce eFuse key selection. For example, if your design stores

the AES key in eFuses, you can disable the BBRAM root key fuse for additional

security. Intel Stratix 10 devices support both red key (unencrypted) and black

key (encrypted) programming.

Note: You program or blow eFuses by flowing a large current for a specific amount of time.

This process is irreversible.

1.3.1. eFuse (Volatile or Non-Volatile) AES Root Key

Virtual eFuses are volatile. Physical eFuses are non-volatile. Once you program the

physical eFuse key, you cannot change or reprogram the key. The value stored in

eFuses is a device-unique scrambled version of the original owner key.

The Intel Quartus® Prime Programmer includes a Device security key storage

option. This option is available for Intel Stratix 10 and later devices that include the

SDM when you program a Intel Quartus Prime encryption key .qek.

Note: The current release only support the battery-backed RAM (BBRAM) storage location.

1.3.2. BBRAM (Volatile) AES Root Key

In contrast to eFuse keys, BBRAM keys are reprogrammable. The BBRAM key vault

holds a single key. Programming a new key deletes the previously programmed key.

The BBRAM key vault includes a built-in function to perform periodic key flipping to

prevent key imprinting.

The BBRAM AES key has its own power supply. VCCBAT powers the BBRAM AES key.

The allowed voltage range is 1.2V - 1.8V.

Related Information

Recommended Operating Conditions for VCCBAT in Stratix 10 Device Datasheet

1. Intel® Stratix® 10 Device Security Overview

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2. Design Authentication

For networked systems, every power up or remote system upgrade to an

unauthenticated bitstream is vulnerable to attack. Malicious attacks can occur because

the FPGA does not verify that configuration bitstream is from a trusted source. Intel

Stratix 10 FPGAs include a feature to authenticate the bitstream, guaranteeing that

the bitstream is from a trusted source. Authentication uses signature keys to validate

the content of a bitstream, preventing the Intel Stratix 10 FPGA from configuring with

an unauthorized configuration bitstream.

When you use authentication, your manufacturing process programs the hash digest

of the Elliptic Curve Digital Signature Algorithm (ECDSA) public signature key into

FPGA eFuses. The configuration bitstream contains the public signature key. The SDM

compares the hash digest of configuration bitstream public signature key to the hash

digest stored in eFuses. The SDM only loads the bitstream if the values match.

You can choose either ECDSA256 or ECDSA384. The ECDSA256 and ECDSA384 use

the SHA-256 and SHA-384 cryptographic hash function to create the secure hash.

Intel recommends that you use 384-bit algorithm. The 256-bit algorithm is weaker

than the algorithm and consequently more likely to become vulnerable to attack. Use

the 256-bit algorithm if you have a custom hardware security module (HSM) that does

not accept SHA-384 hashes. SHA-384 generates a bitstream that is larger than

SHA-256. SHA-384 hashes result in longer configuration times.

2.1. The Configuration Bitstream

The figure below shows an Intel Stratix 10 configuration bitstream that includes an

FPGA and HPS. The firmware section is static and is dependent on the Intel Quartus

Prime version.

The SDM always authenticates the firmware configuration bitstream whether you

choose to authenticate the other dynamic sections of the bitstream. To create an

additional level of security, you may request joint signing for the configuration

bitstream by programming the Joint Signature fuse on the device. When the Joint

Signature fuse is programmed, the device checks for an owner signature on the

firmware section of the configuration bitstream. The device only runs firmware with

both signatures.