Intel Core i7 Extreme Edition Bedienungsanleitung

323094

Intel®Core™ i7 Processor with

Intel®QM57 Express Chipset

Development Kit User Guide

December 2009

Revision 001

2 323094 Dev Kit Manual

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*Other names and brands may be claimed as the property of others.

Dev Kit Manual 3 323094

Contents

1About This Manual.............................................................................................. 7

1.1 Content Overview.................................................................................... 7

1.2 Text Conventions .................................................................................... 7

1.3 Glossary of Terms and Acronyms............................................................... 9

1.4 Related Documents................................................................................ 14

1.5 Development kit Technical Support.......................................................... 14

1.5.1 Online Support......................................................................... 14

1.5.2 Additional Technical Support...................................................... 14

2Getting Started ................................................................................................ 15

2.1 Development Kit Contents ...................................................................... 15

2.2 Additional Required Hardware Not Included In This Kit ............................... 16

2.3 Additional Required Software Not Included In This Kit ................................ 16

2.4 Workspace Preparation .......................................................................... 16

2.5 System Setup ....................................................................................... 17

2.6 System Power-Up.................................................................................. 18

2.7 System Power-Down.............................................................................. 18

2.8 System BIOS ........................................................................................ 18

2.8.1 Configuring the BIOS................................................................ 18

2.8.2 Programming BIOS Using a Bootable USB Device ......................... 19

2.9 Instructions to flash BIOS on SPI ............................................................ 20

3Development Board Features ............................................................................. 21

3.1 Block Diagram ...................................................................................... 21

3.2 Mechanical Form Factor.......................................................................... 21

3.3 Development Board Features Table.......................................................... 21

3.4 Driver Key Features ............................................................................... 23

3.5 BIOS Key Features ................................................................................ 24

3.6 System Thermal Management ................................................................. 24

3.7 System Features and Operation .............................................................. 24

3.7.1 Processor ................................................................................ 25

3.7.2 Chipset ................................................................................... 29

3.7.3 Displays.................................................................................. 35

3.7.4 Debugging Interfaces ............................................................... 38

3.7.5 Power Management .................................................................. 38

3.7.6 Power Measurement Support ..................................................... 38

3.7.7 Power Supply Usage and Recommendation.................................. 43

4Development Board Physical Hardware Reference ................................................ 44

4.1 Primary Features ................................................................................... 44

4.2 Connectors ........................................................................................... 47

4.2.1 Back Panel Connectors.............................................................. 48

4.3 Configuration Settings............................................................................ 48

4.4 Power On and Reset Push Buttons ........................................................... 51

4.5 LEDs.................................................................................................... 52

4.6 Other Headers ...................................................................................... 53

4 323094 Dev Kit Manual

4.6.1 H8 Programming Header ........................................................... 53

4.6.2 Expansion Slots and Sockets ..................................................... 53

5Daughter and Plug-in Cards............................................................................... 63

5.1 PCIe* Add-in Card ................................................................................. 63

5.2 PCI Expansion Card ............................................................................... 63

5.3 Port 80-83 Add-in Card .......................................................................... 64

6Heatsink Installation Instructions ....................................................................... 66

Figures

Figure 1. System Block Diagram ........................................................................ 21

Figure 2. VID Override Circuit ............................................................................ 26

Figure 3. Block Diagram of On-board LAN Implementations ................................... 30

Figure 4. BCLK Frequency Select Circuit .............................................................. 34

Figure 5. Platform Clocking Circuit...................................................................... 35

Figure 6. Intel®Core™ i7 Processor Based Low-Power Platform Display Interfaces .. 37

Figure 7. Component Locations –Top View.......................................................... 44

Figure 8. Component Locations –Bottom View..................................................... 45

Figure 9. Back Panel Connector Locations............................................................ 48

Figure 10. PCIe* Add-in Card............................................................................. 63

Figure 11. PCI Expansion Card ........................................................................... 64

Figure 12. Port 80-83 Interposer Card ................................................................ 64

Figure 13. Block Diagram of Port 80-83 Add-in Card ............................................. 65

Figure 14. Disassembled Fan/heatsink Assembly .................................................. 66

Figure 15. Bottom View of the CRB with Backplate in Place.................................... 67

Figure 16. Top View of Board With Pins Installed, Through the Board, And

Into the Backplate (Backplate not visible) ..................................................... 68

Figure 17. Applying Thermal Grease to the Top of Processor Package .................... 69

Figure 18. Squeeze Activation Arm Downward, Toward the Board ......................... 70

Figure 19. Installing Fan/heatsink (Slide the fan/heatsink away from

compression assembly handle) .................................................................... 71

Figure 20. Fan/heatsink Power Plugged Into Board .............................................. 72

Figure 21. Completed Intel®Core™ i7 Processor CRB With Fan/heatsink

Assembly Installed .................................................................................... 73

Tables

Table 1. Text Conventions ................................................................................... 8

Table 2. Terms................................................................................................... 9

Table 3. Acronyms ........................................................................................... 11

Table 4. Related Documents .............................................................................. 14

Table 5. Development Kit Feature Set Summary .................................................. 22

Table 6. Supported DIMM Module Configurations.................................................. 27

Table 7. Hardware Straps for processor PCI Express* Interface Usage .................... 28

Table 8. PCI Express* Ports ............................................................................... 30

Table 9. Selection of I/O Voltage for the Intel®High Definition Audio...................... 31

Table 10. SATA Ports ........................................................................................ 31

Table 11. USB Port Mapping .............................................................................. 32

Table 12. Jumper Setting for SPI Programming .................................................... 33

Table 13. Power Management States .................................................................. 38

Dev Kit Manual 5 323094

Table 14. Digital Multimeter............................................................................... 39

Table 15. Power Measurement Resistor for Power Rails ......................................... 39

Table 16. Component Location .......................................................................... 45

Table 17. Connectors on the motherboard ........................................................... 47

Table 18. Back Panel Connectors........................................................................ 48

Table 19. Configuration Jumper/Switches Settings ............................................... 48

Table 20. Power-on and Reset Push Buttons ........................................................ 52

Table 21. Development lit LEDs.......................................................................... 52

Table 22. H8 Programming jumpers ................................................................... 53

Table 23. Expansion Slots and Sockets ............................................................... 54

Table 24. Fan Connector (J4C1) ......................................................................... 54

Table 25. Front Panel Connector......................................................................... 54

Table 26. eDP Support Connector....................................................................... 55

Table 27. SATA Port 0 „Direct Connect‟ Connector Pinout (J8J1) ............................. 55

Table 28. SATA Ports 1 and 2/eSATA Ports 3 and 4 Pinout (J7G2, J7G1, J6J1, J7J1) . 56

Table 29. SATA Power Connector (J6H1) ............................................................. 56

Table 30. SPI Programming Header (J8E1) .......................................................... 56

Table 31. HAD Header for MDC Interposer (J9E4)................................................. 57

Table 32.HAD Header for MDC Interposer (J9E7).................................................. 57

Table 33. HAD Header for External HDMI Support (J8F1) ...................................... 58

Table 34. LED Header (J8G3)............................................................................. 58

Table 35. Descriptor Security Override (J8F4) ...................................................... 59

Table 36. Controller Link Header (J8G2).............................................................. 59

Table 37. TPM Header/Port 80 Add-in-Card Header (J9A1) .................................... 60

Table 38. LPC Hot Docking (J9E5) ...................................................................... 60

Table 39. LPC Side Band Header (J9G2) .............................................................. 61

Table 40. Jumper settings for Port 80-80 card ..................................................... 65

6 323094 Dev Kit Manual

Revision History

Document

Number

Revision

Number

Description

Revision Date

323094

001

Public release.

December 2009

Dev Kit Manual 7 323094

1About This Manual

This manual describes the use of the Intel®Core™ i7 Processor with Intel®QM57 Express

Chipset Development kit (Development kit). This manual has been written for OEMs, system

evaluators, and embedded system developers. This manual assumes basic familiarity in the

fundamental concepts involved with installing and configuring hardware for a personal

computer system. This document defines all jumpers, headers, LED functions, their locations

on the development kit, and other subsystem features and POST codes. This manual assumes

basic familiarity in the fundamental concepts involved with installing and configuring hardware

for a personal computer system.

For the latest information about the Dev Kit and platform design collateral, please visit:

http://tigris.intel.com/scripts-edk/viewer/UI_CLCatalog.asp?edkId=8381

1.1 Content Overview

This manual is arranged into the following sections:

About This Manual contains a description of conventions used in this manual. The last few

sections explain how to obtain literature and contact customer support.

Getting Started describes the contents of the development kit. This section explains the basics

steps necessary to get the board running. This section also includes information on how to

update the BIOS.

Development Board Features describes details on the hardware features of the development

board. It explains the Power Management and Testability features.

Development Board Physical Hardware Reference provides a list of major board components

and connectors. It gives a description of jumper settings and functions. The chapter also

explains the use of the programming headers.

Daughter and Plug-in Cards contains information on add-in cards available from Intel that can

be used with the development board.

1.2 Text Conventions

Throughout this document:

Intel®Core™ i7-620M Processor, Intel®Core™ i7-610E Processor, Intel®Core™ i7-

620LE Processor, Intel®Core™ i7-620UE Processor, Intel®Core™ i5-520M Processor,

and Intel®Core™ i5-520E Processor, Intel®Celeron®P4500 processor, and Intel®

Celeron®P4505 processor may be referred to as the Processor or CPU.

Intel®QM57 Series Chipset may be referred to as the Chipset or PCH.

The notations listed in Table 1 may be used throughout this manual.

8 323094 Dev Kit Manual

Table 1. Text Conventions

Notation

Definition

The pound symbol (#) appended to a signal name indicates that the signal

is active low. (e.g., PRSNT1#)

Variables

Variables are shown in italics. Variables must be replaced with correct

values.

INSTRUCTIONS

Instruction mnemonics are shown in uppercase. When you are

programming, instructions are not case-sensitive. You may use either

uppercase or lowercase.

Numbers

Hexadecimal numbers are represented by a string of hexadecimal digits

followed by the character H. A zero prefix is added to numbers that begin

with A through F. (For example, FF is shown as 0FFH.) Decimal and binary

numbers are represented by their customary notations. (That is, 255 is a

decimal number and 1111 is a binary number. In some cases, the letter B

is added for clarity.)

Units of Measure

GByte

KByte

K

MByte

MHz

µA

µF

µs

µW

The following abbreviations are used to represent units of measure:

amps, amperes

gigabytes

kilobytes

kilo-ohms

milliamps, mill amperes

megabytes

megahertz

milliseconds

milliwatts

nanoseconds

picofarads

watts

volts

microamps, microamperes

microfarads

microseconds

microwatts

SIGNAL NAMES

Signal names are shown in uppercase. When several signals share a

common name, an individual signal is represented by the signal name

followed by a number, while the group is represented by the signal name

followed by a variable (n). For example, the lower chip-select signals are

named CS0#, CS1#, CS2#, and so on; they are collectively called CSn#.

A pound symbol (#) appended to a signal name identifies an active-low

signal. Port pins are represented by the port abbreviation, a period, and

the pin number (e.g., P1.0).

Dev Kit Manual 9 323094

1.3 Glossary of Terms and Acronyms

Table 2 defines conventions and terminology used throughout this document.

Table 2. Terms

Term/Acronym

Definition

Aggressor

A network that transmits a coupled signal to another network.

Anti-etch

Any plane-split, void or cutout in a VCC or GND plane.

Bus Agent

A component or group of components that, when combined, represent a

single load on the AGTL+ bus.

Crosstalk

The reception on a victim network of a signal imposed by aggressor

network(s) through inductive and capacitive coupling between the

networks.

Backward Crosstalk - Coupling that creates a signal in a victim network

that travels in the opposite direction as the aggressor‟s signal.

Forward Crosstalk - Coupling that creates a signal in a victim network that

travels in the same direction as the aggressor‟s signal.

Even Mode Crosstalk - Coupling from a signal or multiple aggressors when

all the aggressors switch in the same direction that the victim is

switching.

Odd Mode Crosstalk - Coupling from a signal or multiple aggressors when

all the aggressors switch in the opposite direction that the victim is

switching.

Duck Bay 3

PCI Express* interposer card that provides Express-card support

Flight Time

Flight time is a term in the timing equation that includes the signal

propagation delay, any effects the system has on the TCO (time from

clock-in to data-out) of the driver, plus any adjustments to the signal at

the receiver needed to ensure the setup time of the receiver. More

precisely, flight time is defined as:

The time difference between a signal at the input pin of a receiving agent

crossing the switching voltage (adjusted to meet the receiver

manufacturer‟s conditions required for AC timing specifications; i.e.,

ringback, etc.) and the output pin of the driving agent crossing the

switching voltage when the driver is driving a test load used to specify the

driver‟s AC timings.

Maximum and Minimum Flight Time - Flight time variations are caused by

many different parameters. The more obvious causes include variation of

the board dielectric constant, changes in load condition, crosstalk, power

noise, variation in termination resistance, and differences in I/O buffer

performance as a function of temperature, voltage, and manufacturing

process. Some less obvious causes include effects of Simultaneous

Switching Output (SSO) and packaging effects.

Maximum flight time is the largest acceptable flight time a network will

experience under all conditions.

Minimum flight time is the smallest acceptable flight time a network will

experience under all conditions.

Infrared Data

Assoc.

The Infrared Data Association (IrDA) has outlined a specification for serial

communication between two devices via a bi-directional infrared data

10 323094 Dev Kit Manual

Term/Acronym

Definition

port. The Development kit has such a port and it is located on the rear of

the platform between the two USB connectors.

IMVP6.5

The Intel®Mobile Voltage Positioning specification for the Intel®Core™ i5

Processor. It is a DC-DC converter module that supplies the required

voltage and current to a single processor.

Inter-Symbol

Interference

Inter-symbol interference is the effect of a previous signal (or transition)

on the interconnect delay. For example, when a signal is transmitted

down a line and the reflections due to the transition have not completely

dissipated, the following data transition launched onto the bus is affected.

ISI is dependent upon frequency, time delay of the line, and the reflection

coefficient at the driver and receiver. ISI may impact both timing and

signal integrity.

Mott Canyon IV

This Add-in Card enables Intel®High Definition Audio functionality

Network

The network is the trace of a Printed Circuit Board (PCB) that completes

an electrical connection between two or more components.

Overshoot

The maximum voltage observed for a signal at the device pad, measured

with respect to VCC.

Pad

The electrical contact point of a semiconductor die to the package

substrate. A pad is only observable in simulations.

The contact point of a component package to the traces on a substrate,

such as the motherboard. Signal quality and timings may be measured at

the pin.

Power-Good

“Power-Good,” “PWRGOOD,” or “CPUPWRGOOD” (an active high signal)

indicates that all of the system power supplies and clocks are stable.

PWRGOOD should go active at a predetermined time after system

voltages are stable and should go inactive as soon as any of these

voltages fail their specifications.

Ringback

The voltage to which a signal changes after reaching its maximum

absolute value. Ringback may be caused by reflections, driver oscillations,

or other transmission line phenomena.

System Bus

The System Bus is the microprocessor bus of the processor.

Setup Window

The time between the beginning of Setup to Clock (TSU_MIN) and the

arrival of a valid clock edge. This window may be different for each type

of bus agent in the system.

Simultaneous

Switching Output

Simultaneous Switching Output (SSO) effects are differences in electrical

timing parameters and degradation in signal quality caused by multiple

signal outputs simultaneously switching voltage levels in the opposite

direction from a single signal or in the same direction. These are called

odd mode and even mode switching, respectively. This simultaneous

switching of multiple outputs creates higher current swings that may

cause additional propagation delay (“push-out”) or a decrease in

propagation delay (“pull-in”). These SSO effects may impact the setup

and/or hold times and are not always taken into account by simulations.

System timing budgets should include margin for SSO effects.

Stub

The branch from the bus trunk terminating at the pad of an agent.

Trunk

The main connection, excluding interconnect branches, from one end.

System

Management Bus

A two-wire interface through which various system components may

communicate.

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