JVC KD-LX111R Bedienungsanleitung

SERVICE MANUAL

CD RECEIVER

No.49714

Jun. 2002

KD-LX111R

OFF

STDM

ATT

SOURCE

Contents

Safety precaution

Preventing static electricity

Disassembly method

Adjustment method

1-2

1-3

1-4

1-13

Flow of functional

operation unitl TOC read

Maintenance of laser pickup

Replacement of laser pickup

Description of major ICs

1-14

1-16

1-17~31

Area suffix

E ----------- Continental Europe

EX --------------- Central Europe

KD-LX111R

1-17

FAN8037 (IC581) : CD driver

1. Pin layout & Block diagram

2. Pin function

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

T. S . D

STAND BY

ALL MUTE

POWER SAVE

CH2 op-amp input(+)

CH2 op-amp input(-)

CH2 op-amp output

CH3 op-amp input(+)

Ch3 op-amp input(-)

CH3 op-amp output

CH4 op-amp input(+)

CH4 op-amp input(-)

CH4 op-amp output(+)

CH5 motor speed control

CH5 forward input

CH5 reverse input

CH6 motor speed control

CH6 forward input

CH6 reverse input

Signal ground

CH7 forward input

CH7 reverse input

CH7 motor speed control

Stand by

Power save

All mute

Power supply voltage

CH7 drive output(-)

IN2+

IN2-

OUT2

IN3+

IN3-

OUT3

IN4+

IN4-

OUT4

CTL1

FWD1

REV1

CTL2

FWD2

REV2

SGND

FWD3

REV3

CTL3

MUTE

PVCC2

DO7-

No.

Symbol I/O Function

CH7 drive output(+)

CH6 drive output(-)

CH6 drive output(+)

Power ground2

CH5 drive output(-)

CH5 drive output(+)

CH4 drive output(-)

CH4 drive output(+)

CH3 drive output(-)

CH3 drive output(+)

Power ground1

CH2 drive output(-)

CH2 drive output(+)

CH1 drive output(-)

CH1 drive output(+)

Power supply voltage

Regulator feedback input

Regulator output

Regulator reset input

Bias voltage input

Signal supply voltage

CH1 op-amp input(+)

CH1 op-amp input(-)

CH1 op-amp output

DO7+

DO6-

DO6+

PGND2

DO5-

DO5+

DO4-

DO4+

DO3-

DO3+

PGND1

DO2-

DO2+

DO1-

DO1+

PVCC1

REGOX

REGX

RESX

VREF

SVCC

IN1+

IN1-

OUT1

No.

Symbol I/O Function

Description of major ICs

KD-LX111R

1-18

UPD784217AGC168 (IC701) : Main micon

1.Pin layout

2.Pin functions(1/3)

100 ~ 76

26 ~ 50

Pin No.

I/O

Function

CD mechanical switch 2 detection signal input

CD mechanical switch 3 detection signal input

CD mechanical switch 4 detection signal input

Rest switch detection signal input

Motor signal control signal output at loading

Motor signal control signal output at leject

DIMMER pulse control output

POWER ON:H,FLAT PANEL:L

GND

Reset detection teaminal

CD mechanical switch 1 detection signal input

J-BUS int

POWER SAVE2. Operating together with BACKUP.H input:STOP

Pulse signal for CRUISE input(only in 330R)

RDS clock input

RDS data input

Remocon input(111R:READY)

Temperature detection input

Key input 0

Key input 1

Key input 2

Level meter input

MRC output voltage detection

S.QUALITY level input

S.METER level input

GND

Subwoofer volume control analog output

Dot matrix contrast adjustment analog output

J-BUS data input

J-BUS data output

J-BUS clock input and output

H:LX333R L:LX111R

Data output to LCD driver

Clock output to LCD driver

Symbol

SW2

SW3

SW4

RST-SW

LMO

LM1

DIM-OUT

ILLUM1

VDD

VSS

XT2

XT1

RESET

SW1

BUS-INT

PS2

CRUISE

RDS-SCK

RDS DA

REMOCON

AVDD

AVREFO

TEM1

KEY0

KEY1

KEY2

LEVEL

MRC

AVSS

W-VOL

DOT-CNT

AVREF

BUS-SI

BUS-SO

BUS-SCK

STAGE2

LCD-DA

LCD-SCK

KD-LX111R

1-19

2.Pin functions(2/3)

Pin No.

I/O

Function

Chip enable output 1 to LCD driver

Buzzer output

12C communication data input

12C communication data output

12C communication clock output

J-BUSI/O signal terminal

Tray motor negative signal output terminal

Tray motor positive signal output terminal

Motor control signal output in door down

Motor control signal output in door up

Stereo signal input L:Stereo

AF check output AF check:L

Chameleon machanical switch 1 detection signal input

Chameleon machanical switch 2 detection signal input

Chameleon machanical switch 3 detection signal input

Chameleon machanical switch 4 detection signal input

Chameleon machanical switch 5 detection signal input

Rotary volume signal 1 input

Rotary volume signal 2 input

Auto seek/stop selection output SEEK:L STOP:H

FM/AM selection output FM:H AM:L

IC control CE output

IC control data output

IC control clock output

IC control data input

Telephone mute detection input

POWER AMP ON/OFF selection output

GND

Dimmer detection input L:dimmer ON

Power save 1 Operating together with ACC.Power save :L Operating :H

Power ON/OFF selection output Power ON:H

CD power supply control signal output CD:H

Mute output MUTEON:L

Subwoofer cut off frequency control output 1

Subwoofer cut off frequency control output 2

Subwoofer mute output MUTE ON:H

data output terminal

clock signal output terminal

FM band filter selection signal output

CD-DA/CD-RW selection control output CD-RW:L

Reset signal output to LCD driver

Door motor kick signal output

Tray motor kick signal output

Data cmmunication clock output with CDLSI

Data cmmunication clock CE with CDLSI

CDLSI reset signal output

GND

Symbol

LCD-CE1

BUZZER

12C-DAI

12C-DAO

12C-CLK

BUS-I/O

TMO

TM1

DMO

DM1

AFCK

C-SW1

C-SW2

C-SW3

C-SW4

C-SW5

VOL1

VOL2

SEEK/STP

FM/AM

PLL-CE

PLL-DO

PLL-CLK

PLL-DI

TEL-MUTE

AMP-KILL

VSS

DIM -IN

PS1

POWER

CD-ON

MUTE

W-LPF1

W-LPF2

W-MUTE

VDD

VOL-DA

VOL-CLK

CF-SEL

GVSW

LCD RST

DMK

TMK

BUCK

CCE

RST

TEST

KD-LX111R

1-20

2.Pin functions(3/3)

Pin No.

100

I/O

Function

Data communication input and output port 0 with CDLSI

Data communication input and output port 1 with CDLSI

Data communication input and output port 2 with CDLSI

Data communication input and output port 3 with CDLSI

H:not for 8cm DISC L:for 8cm DISC

Symbol

BUSO

BUS1

BUS2

BUS3

DISCSEL

Micro-

controller

interface

Audio output

circuit Digital output

16k

RAM

Address

circuit

1-bit

DAC Servo control

Clock

generator

LPF

PWM D/A

A/D

ROM

CLV servo

Sync signal

protection

EFM

Sub code

detector

Data

slicer

VCO

PLL

TMAX

Digital equalizer

automatic

adjustment circuit

RAM

Correction

circuit

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

BCK

LRCK

AOUT

DOUT

IPF

DD3

SS3

SBOK

CLCK

DATA

SFSY

SBSY

/HSO

UHSO

DD3

PDO

VXDD3

SS3

TEIN

DD3

SS3

DMO

FMO

DD3

SEL

TEBC

RFGC

REF

TRO

FOO

SS3

DD3

DVR

SS3

ZDET

SS5

BUS0

BUS1

BUS2

BUS3

BUCK

/CCE

/RST

DD5

TEZI

TEI

SBAD

FEI

RFRP

RFZI

RFCT

DD3

RFI

SLCO

SS3

VCOF

REF

LPFO

LPFN

TMAX

TC9490FA (IC521) : DSP & DAC

1.Pin layout & Block daiagram

KD-LX111R

1-21

2.Pin function (1/2)

I/O

Function

Bit clock outputpin 32fs, 48fs, or 64fs selectable by command.

L/R channel clock output pin."L" for L channe and "H" for R channel.

Output polarity can be inverted by command.

Audio data output pin. MSB-first or LSB-first selectable by command.

Digital data output pin. Outputs up to double-speed playback.

Correction flag output pin.When set to "H",AOUT output cannot be corrected

by C2 correction processing.

Digital 3.3V power supply voltage pin.

Digital GND pin.

Subcode Q data CRCC result output pin."H" level when result is OK.

Subcode P-W data read clockI/O pin. I/O polarity selectable by command.

Subcode P-W data output pin.

Playback frame sync signal output pin.

Subcode block sync signal output pin. "H" level at S1 when subcode sync is

detected.

Playback speed mode flag output pins.

PLL-only 3.3V power supply voltage pin.

EFM and PLCK phase difference signal output pin.

TMAX detection result output pin.

Inverted input pin for PLL LPF amp.

Output oin for PLL LPF amp.

PLL-only V

REF

pin.

VCO filter pin.

Analog GND pin.

DAC output pin for data slice level generation.

RF signal input pin.Zin selectable by command.

Analog 3.3V power supply voltage pin.

RFRP signal center level input pin.

RFRP signal zero-cross input pin.

RF ripple signal input pin.

Focus error signal input pin.

Sub-beam adder signal input pin.

Tracking error input pin. Inputs when tracking servo is on.

Tracking error signal zero-cross input pin.

Focus equalizer output pin.

Tracking equalizer output pin.

Analog reference power supply voltage pin.

Symbol

BCK

LRCK

AOUT

DOUT

IPF

VDD3

VSS3

SBOK

CLCK

DATA

SFSY

SBSY

/HSO

/UHSO

PVDD3

PDO

TMAX

LPFN

LPFO

PVREF

VCOF

SS3

SLCO

RFI

RFCT

RFZI

RFRP

FEI

SBAD

TEI

TEZI

FOO

TRO

REF

Pin No.

TC9490FA(2/3)

Playback speed/UHSO /HSO

Normal

Double

4 times

---

TMAX OutputTMAX Detection result

Longer than fixed period

Within fixed period

Shorter than fixed period

"PV

DD3

"HIZ"

"AV

SS3"

KD-LX111R

1-22

2.Pin function (2/2)

I/O

Function

RF amplitude adjustment control signal output pin.

Tracking balance control signal output pin.

APC circuit ON/OFF signal output pin. At laser on,high impedance with

UHS="L" ,H output with UHS="H".

Analog 3.3V power supply voltage pin.

Feed equalizer output pin.

Disc equalizer output pin.

Digital GND pin.

Digital 3.3V power supply voltage pin.

Test input pin. Normally,fixed to "L".

System clock oscillator GND pin.

System clock oscilatoe input pin.

System clock oscillator output pin.

System clock oscillator 3.3V power supply voltage pin.

DA converter GND pin.

R-channel data forward output pin.

DA converter 3.3V power supply pin.

Reference voltage pin.

L-channel data forward output pin.

DA converter GND pin.

1 bit DA converter zero data detection flag output pin.

Microcontroller interface GND pin.

Microcontroller interface data I/O pins.

Microcontroller interface clock input pin.

Microcontroller interface chip enable signal input pin.At "L".

Bus0 to BUS3 are active.

Reset signal input pin. At reset,"L".

Microcontroller interface 5V power supply pin.

Symbol

RFGC

TEBC

SEL

DD3

FMO

DMO

SS3

DD3

TESIN

SS3

DD3

SS3

DD3

DVR

SS3

ZDET

SS5

BUS0

BUS1

BUS2

BUS3

BUCK

/CCE

/RST

DD5

Pin No.

TC9490FA(3/3)

+–

A OUT

A IN–

A IN+

VEE

VCC

B OUT

B IN–

B IN+

NJM2100M (IC821) : Operational Amp

1A OUT

2A -IN

3A +IN

5GND

B OUT

B -IN

B +IN

NJM2904M (IC951) : Ope amp

1.Pin layout

KD-LX111R

1-23

BD3860K (IC911):E.vol & Loud

1.Terminal layout

2.Block diagram

3.Pin function

1 11

33 23

6 5 9 40 36 35 343328323130 2919 15 14

39 38 37 25 24 26 23 22 21 20 18 17 16

GND FIL VCC SEL1

0 18 dB

VIN1 LOUD1 HF1 LF1 DET1 TIN1 TNF1 BNF1

OUTF1

OUTR1

OUTR2

OUTF2

BOUT2BNF2TNF2TIN2BBOUT2MIX2VCA2DET2LF2HF2LOUD2VIN2SEL2

BOUT1VCA1 MIX1 BBOUT1

POWER

SUPPLY INPUT

GAIN

INPUT

GAIN

MAIN

VOLUME

0 -40 dB

LOUDNESS

MAIN

VOLUME

0 -40 dB

LOUDNESS

LOW(f=50Hz) 6dB

PROCESS CONTROL +3 to 12dB

(f=10kHz)

LOW(f=50Hz) 6dB

PROCESS CONTROL +3 to 12dB

(f=10kHz)

TREBLE

-14 +14dB

TREBLE

-14 +14dB

BASS

-14 +14dB

BASS

-14 +14dB

FADER

CH1 FRONT

0 -5 dB

FADER

CH2 FRONT

0 -5 dB

FADER

CH1 REAR

0 -5 dB

FADER

CH2 REAR

0 -5 dB

LOGIC

INPUT

SELECTOR

CH2 Input Pin A

CH2 Input Pin B

CH2 Input Pin C

CH2 Input Pin D

1/2 VCC Pin

Ground Pin

Serial Data Receiving Pin

Serial Clock Receiving Pin

Power Supply Pin

CH2 Rear Output Pin

CH2 Front Output Pin

CH1 Rear Output Pin

CH1 Front Output Pin

CH1 Bass Filter Setting Pin

CH2 Bass Filter Setting Pin

CH2 Treble Filter Setting Pin

CH1 Treble Filter Setting Pin

CH2 Treble Input Pin

CH2 BBE II Signal Output Pin

CH2 Output MIX Amplifier

Inverse Input Pin

FIL

GND

VCC

OUTR2

OUTF2

OUTR1

OUTF1

BOUT1

BNF1

BOUT2

BNF2

TNF2

TNF1

TIN2

BBOUT2

MIX2

No. Symbol Function

CH2 High Pass VCA Output Pin

CH2 Low Pass Filter Setting Pin

CH2 High Pass Filter Setting Pin

CH2 High Pass Attack/Release Time Setting Pin

BBE ON/OFF switching time constant pin

CH1 High Pass Attack/Release Time Setting Pin

CH1 treble Input Pin

CH1 BBE II Signal Output Pin

CH1 Output MIX Amplifier Inverse Input Pin

CH1 High Pass VCA Output Pin

CH1 Low Pass Filter Setting Pin

CH1 High Pass Filter Setting Pin

CH1 Loudness Filter Setting Pin

CH1 Main Volume Input Pin

CH2 Loudness Filter setting Pin

CH2 Main Volume Input Pin

CH2 Input Gain Output Pin

CH1 Input Gain output Pin

CH1 Input Pin A

CH1 Input Pin B

CH1 Input Pin C

CH1 Input Pin D

VCA2

LF2

HF2

DET2

DEF

DET1

TIN1

BBOUT1

MIX1

VCA1

LF1

HF1

LOUD1

VIN1

LOUD2

VIN2

SEL2

SEL1

No. Symbol Function

KD-LX111R

1-24

20k 20k

20k

180k

60k

15pF

x0.5

1.75k

240k

15pF

14k 2k

2k 50k

240k

60k

80k

20k

180k

40pF

12k

15k

50 A

10pF

20 A

40k

20k

20k 20k

50k

PEAK

15k

10pF

40k

60 A

1.3V

BOTTOM

PEAK

40k

30k

13GVSW

VRO

FEO

FEN

RFRP

RFRPIN

RFGO

RFGC

AGCIN

RFO

RFN

GND

12 RFDC

TEO

TEN

TEBC

SEL

LDO

MDI

TNI

TPI

FPI

FNI

Vcc

TA2147F-X (IC501) : RF amp.

1.Terminal layout

2.Block diagram

KD-LX111R

1-25

3.Pin function

I/O

Function

3.3V Power supply pin

Main-beam amp input pin

Sub-beam amp input pin

Sub-beam input pin

Monitor photo diode amp input pin

Laser diode amp output pin

APC circuit ON/OFF control signal,laser diode (LDO) control signal input or

bottom/peak detection frequency change pin.

Tracking error balance adjustment signal pin

Adjusts TE signal balance by eliminating carrier component from

PWM signal(3-state output, PWM carrier = 88.2kHz) output from

TC9490F/FA TEBC pin using RC-LPF and inputting DC.

TEBC input voltage:GND~Vcc

Tracking error signal generation amp negative-phase input pin

Tracking error signal generation amp output pin.

Combining TEO signal and RFRP signal with TC9490F/FA configures

tracking search system.

RF signal peak detection output pin

AGC/FE/TE amp gain change pin

Reference voltage (VRO) output pin *VRO = 1/2 Vcc when Vcc = 3.3V

Focus error signal generation amp output pin

Focus error signal generation amp negative-phase input pin

Signal amp output pin for track count

Combining RFRP signal TEO signal with TC9490F/FA configures tracking

search system.

Signal generation amp input pin for track count

RF signal amplitude adjustment amp output pin

RF amplitude adjustment control signal input pin

Adjusts RF signal amplitude by eliminating carrier component from PWM

signal (3-state output, PWM carrier = 88.2kHz) output from TC9490F/FA

RFGC pin using RC-LPF and inputting DC.

*RFGC input voltage : GND-Vcc

RF signal amplitude adjustment amp input pin

RF signal generation amp output pin

RF signal generation amp input pin

GND pin

Symbol

Vcc

FNI

FPI

TPI

TNI

MDI

LDO

SEL

TEBC

TEN

TEO

RFDC

GVSW

VRO

FEO

FEN

RFRP

RFRPIN

RFGO

RFGC

AGCIN

RFO

RFN

GND

Pin No.

LDOSEL

GND OFF

HIZ

Vcc

Connected to Vcc

through 1k resistor

Control signal output

APC

circuit

ModeGVSW

GND

HIZ

Vcc

CD-RW

CD-DA

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