Lauterbach XC800 Bedienungsanleitung
MANUAL
Release 09.2021
XC800 Debugger
XC800 Debugger | 2
©1989-2021 Lauterbach GmbH
XC800 Debugger
TRACE32 Online Help
TRACE32 Directory
TRACE32 Index
TRACE32 Documents ......................................................................................................................
ICD In-Circuit Debugger ................................................................................................................
Processor Architecture Manuals ..............................................................................................
XC800 .......................................................................................................................................
XC800 Debugger ................................................................................................................... 1
Introduction ....................................................................................................................... 4
Brief Overview of Documents for New Users 4
Warning .............................................................................................................................. 5
Quick Start ......................................................................................................................... 6
Troubleshooting ................................................................................................................ 8
SYStem.Up Errors 8
FAQ ..................................................................................................................................... 8
Configuration ..................................................................................................................... 9
XC800 Specific Implementations ..................................................................................... 10
Breakpoints 10
Software Breakpoints 10
On-chip Breakpoints 10
CPU specific SYStem Settings and Restrictions ........................................................... 11
SYStem.state Open system window 11
SYStem.CONFIG Configure debugger according to target topology 11
Daisy-Chain Example 14
TapStates 15
SYStem.CONFIG.CORE Assign core to TRACE32 instance 16
SYStem.CONFIG.state Display target configuration 17
SYStem.CPU Select CPU 17
SYStem.MemAccess Select memory access mode 18
SYStem.Mode Establish communication with the target 19
SYStem.LOCK Tristate the JTAG port 19
System Options ................................................................................................................. 21
SYStem.Option.IMASKASM Disable interrupts while single stepping 21
SYStem.Option.IMASKHLL Disable interrupts while HLL single stepping 21
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SYStem.Option.LittleEndian Treat memory as little endian 21
SYStem.Option.TRAPEN Change the TRAP_EN bit 22
SYStem.JtagClock Define JTAG clock 23
TrOnchip Commands ........................................................................................................ 24
TrOnchip.CONVert Adjust range breakpoint in on-chip resource 24
TrOnchip.RESet Set on-chip trigger to default state 24
TrOnchip.state Display on-chip trigger window 24
TrOnchip.VarCONVert Adjust complex breakpoint in on-chip resource 25
OCDS1 Connector ............................................................................................................. 26
Memory Classes ................................................................................................................ 28
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©1989-2021 Lauterbach GmbH
XC800 Debugger
Version 04-Nov-2021
Introduction
This document describes the processor specific settings and features for TRACE32-ICD for the
Infineon XC800 CPU family.
Please keep in mind that only the Processor Architecture Manual (the document you are reading at the
moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by
Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your
first choice.
Brief Overview of Documents for New Users
Architecture-independent information:
•“Debugger Basics - Training” (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
•“T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances
for different configurations of the debugger. T32Start is only available for Windows.
•“General Commands” (general_ref_<x>.pdf): Alphabetic list of debug commands.
Architecture-specific information:
•“Processor Architecture Manuals”: These manuals describe commands that are specific for the
processor architecture supported by your Debug Cable. To access the manual for your processor
architecture, proceed as follows:
- Choose Help menu > Processor Architecture Manual.
•“OS Awareness Manuals” (rtos_<os>.pdf): TRACE32 PowerView can be extended for operating
system-aware debugging. The appropriate OS Awareness manual informs you how to enable the
OS-aware debugging.
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©1989-2021 Lauterbach GmbH
Warning
WARNING: To prevent debugger and target from damage it is recommended to connect or
disconnect the Debug Cable only while the target power is OFF.
Recommendation for the software start:
1. Disconnect the Debug Cable from the target while the target power is
off.
2. Connect the host system, the TRACE32 hardware and the Debug
Cable.
3. Power ON the TRACE32 hardware.
4. Start the TRACE32 software to load the debugger firmware.
5. Connect the Debug Cable to the target.
6. Switch the target power ON.
7. Configure your debugger e.g. via a start-up script.
Power down:
1. Switch off the target power.
2. Disconnect the Debug Cable from the target.
3. Close the TRACE32 software.
4. Power OFF the TRACE32 hardware.
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©1989-2021 Lauterbach GmbH
Quick Start
Starting up the debugger is done as follows:
Select the device prompt for the ICD Debugger and reset the system.
The device prompt B:: is normally already selected in the TRACE32 command line. If this is not the case,
enter B:: to set the correct device prompt. The RESet command is only necessary if you do not start
directly after booting the TRACE32 development tool.
5. Specify the CPU specific settings.
The default values of all other options are set in such a way that it should be possible to work without
modification. Please consider that this is probably not the best configuration for your target.
6. Set up data for electrical interface.
Use the subcommands of MAP to define inaccessible memory areas. Bus errors can be removed by
executing SYStem.Up. Make sure that there isn’t any TRACE32 window open which accesses to a
inaccessible memory that is not masked out, otherwise the bus error can occur again.
7. Enter debug mode.
This command resets the CPU and enters debug mode. After this command is executed, it is possible
to access memory and registers.
8. Load your application program.
The format of the Data.LOAD command depends on the file format generated by the compiler. This
test discovers a problem with the electrical connection, wrong chip configurations or linker command
file settings.
A detailed description of the Data.LOAD command and all available options is given in the “General
Commands Reference”.
B::
SYStem.CPU <cpu_type>
SYStem.JtagClock <frequency>
SYStem.Up
Data.LOAD.OMF myprogram /Verify ; OMF specifies the format,
; myprogram is the file name)
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©1989-2021 Lauterbach GmbH
The start-up can be automated using the programming language PRACTICE. A typical start sequence for
the XC888-8FF is shown below:
b:: ; Select the ICD device prompt
WinCLEAR ; Clear all windows
SYStem.CPU XC888 ; Select CPU
SYStem.Up ; Reset the target and enter debug mode
Data.LOAD.OMF MYPROG /VERFY ; Load the application, verify the
; process
Go main ; Run and break at main()
Data.List ; Open source window
Register.view /SpotLight ; Open register window
Var.Local ; Open window with local variables
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©1989-2021 Lauterbach GmbH
Troubleshooting
SYStem.Up Errors
The SYStem.Up command is the first command of a debug session where communication with the target is
required. If you receive error messages while executing this command this may have the following reasons.
• The JTAG lines are not connected correctly.
• The target has no power.
• The pull-up resistor between the JTAG[VCCS] pin and the target VCC is too large.
• The target is in reset:
The debugger controls the processor reset and use the RESET line to reset the CPU on every
SYStem.Up. Therefore no external R-C combination or external reset controller is allowed.
• There is logic added to the JTAG state machine:
By default the debugger supports only one processor in one JTAG chain. If the processor is only
one member of a JTAG chain the debugger has to be informed about the target JTAG chain
configuration. Use the SYStem.CONFIG command to specify the position of the device in the
JTAG-chain.
• There are additional loads or capacities on the JTAG lines.
FAQ
Please refer to our Frequently Asked Questions page on the Lauterbach website.
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©1989-2021 Lauterbach GmbH
XC800 Specific Implementations
Breakpoints
There are two types of breakpoints available: Software breakpoints and on-chip breakpoints.
Software Breakpoints
Software breakpoints are the default breakpoints for program breakpoints. A software breakpoint is
implemented by patching a break code into the memory.
There is no restriction in the number of software breakpoints.
On-chip Breakpoints
The resources for the on-chip breakpoints are provided by the CPU.
The following list gives an overview of the on-chip breakpoints for the XC800:
•On-chip breakpoints: Total amount of available on-chip breakpoints.
•Instruction breakpoints: Number of on-chip breakpoints that can be used to set Program
breakpoints into ROM/FLASH/EEPROM.
•Read/Write breakpoints: Number of on-chip breakpoints that can be used as Read or Write
breakpoints.
•Data breakpoint: Number of on-chip data breakpoints that can be used to stop the program
when a specific data value is written to an address or when a specific data value is read from an
address.
On-chip
Breakpoints
Instruction
Breakpoints
Read/Write
Breakpoints
Data
Breakpoint
XC800 4 up to 4
up to 1 range
(2 single needed)
up to 1 single
address read or
address range
up to 1 single
address write or
address range
—
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