MiTAC 8050D Bedienungsanleitung

BY: Grass

Grass.Ren

.Ren

Repair Technology Research Department /EDVD

Mar.2004

SERVICE MANUAL FOR

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SERVICE MANUAL FOR

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1. Hardware Engineering Specification …………………………………………………………………..

1.1 Introduce ………………………………………………………………………………………………

1.2 System Overview ……………………………………………………………………………………….

1.3 System Hardware Parts …………………………………………………………………………………

1.4 Other Functions …………………………………………………………………………………….….

1.5 Power Management …………………………………………………………………………………….

2. System View & Disassembly …………………………………………………………………………..

2.1 System View …………………………………………………………………………………………..

2.2 System Disassembly …………………………………………………………………………………….

3. Definition & Location of Connectors / Switches Setting ………………………………………………

4. Definition & Location of Major Component …………………………………………………………..

5. Pin Description of Major Component…………………………………………………………………..

5.1 Intel Pentium M (Banias) Processor ……………………………………………………………………..

5.2 Intel 855GM/GME North Bridge ………………………………………………………………….…….

5.3 Intel 82801 IDBM I/O Controller Hub 4 Mobile(ICH4-M) South Bridge …………………………………..

6. System Block Diagram ……………………………………………………….……………………….....

7. Maintenance Diagnostics ………………………………………………………………………………..

7.1 Introduction ……………………………………………………………………………………………

7.2 Debug Card …………………………………… ………………………………………………………

7.3 Error code……………………………… ……………………………………………………………..

Contents

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8. Trouble Shooting ……………………………………………………………………………………..….

8.1 No Power ……………………………………………………………………………………………….

8.2 Battery Can not Be Charged ……………………………………………………………………………..

8.3 No Display ………………………………… …………………………………………………………...

8.4 External Monitor No Display …………………………………………………………………………….

8.5 Memory Test Error ……………………………………………………………………………………..

8.6 Keyboard/Touch-pad Test Error ………………………………………………………………………...

8.7 USB Port Test error……………………………………………………………………………………...

8.8 Hard Disk Drive Test Error………………………………………………………………………………

8.9 CD-ROM Test Error …………………………………………………………………………………….

8.10 Audio Test Failure………………………………………………………………………………..….…

8.11 LAN Test Error ………………………………………………………………………………………..

8.12 Modem Test Error…………… …………………………………………………………………..……

8.13 Mini-PCI Test Error……….. ……… ………………………………………………………………....

8.14 Card Bus&Reader Test Error…………………………………………………………………………...

8.15 IEEE1394 Test Failure …………………………………………………………………………………

9. Spare Parts List ………………………………………………………………………………….…..…...

10. System Exploded View ……………………………………………………………………………...…..

11. Circuit Diagram ………………………………………………………………………………………....

12. Reference Material …………………………………………………………………………………..….

Contents

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1.1 Introduce

1. Engineer Hardware Specification

The MiTAC 8050D model is designed for Intel Banias processor with 400MHz FSB with Micro-FCPGA package.

It can support Banias 1.5G ~ 1.9GHz/Dothan 2.0GHz and above.

This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has

standard hardware peripheral interface. The power management complies with Advanced Configuration and

Power Interface (ACPI) 2.0. It also provides easy configuration through CMOS setup, which is built in system

BIOS software and can be pop-up by pressing F2 key at system start up or warm reset. System also provides icon

LEDs to display system status, such as AC Power indicator, Battery Power indicator, Battery status indicator,

HDD,CD-ROM, NUM LOCK, CAP LOCK, SCROLL LOCK, RF on/off Card Reader indicator. It also equipped

with LAN, 56K Fax MODEM, 3 USB port, S-Video and audio line in/out , external microphone function.

The memory subsystem supports two expansion DDR SDRAM slot with unbuffered PC1600/PC2100 DDR-

SDRAM.

The Montara-GME GMCH Host Memory Controller integrates a high performance host interface for Intel Banias

processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, Digital Video port

(DVOB & DVOC) interface, and Intel Hub interface Technology connecting with Intel 82801DBM ICH4-M.

The Intel ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio

Controller with AC97 interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers,

and Intel Hub interface technology.

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The MOBILITY M10 provides one of the fastest and most advanced 2D, 3D, and multimedia graphics

performance for notebooks. It’s architecture introduces the latest achievements in the graphics industry, which

enable the use of the progressive new features in upcoming applications, but without compromising performance.

ATIs support of support of DirectX® 9 features, highly optimized Open GL® support, and flexible memory

configurations allow implementations targeted at the gaming enthusiast, consumer, business and workstation

platforms.

The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides

32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications

and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management

Interface (ACPI).

The VT6307L is a single chip PCI Host Controller for IEEE 1394-1995 Release 1.0 and IEEE 1394a P2000. It

implements the Link and PHY layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0

and 1394a P2000. It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high

performance data transfer via a 32-bit bus master PCEI host bus interface. The VT6307L supports 100, 200 and

400 Mbit/sec transmission via an integrated 2-port PHY. The VT6307L services two types of data packets:

asynchronous and isochronous(real time). The 1394 link core performs arbitration requesting, packet generation

and checking, and bus cycle master operations. It also has root node capability and performs retry operations.

The RICOH R5C592 CardBus/Media Reader controller functions as a single slot PCI to Cardbus bridge and also

PCI interface smart card and MS/SD/MMC flash card reader. The R5C592 provide one Cardbus slot and all reader

interface may operate simultaneously.

The CH7011A is a display controller device which accepts a digital graphics input signal, and encodes and

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transmits data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide

variable voltage data port which supports five different data format including RGB and YcrCb. The TV-Out

processor will perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data

into any of the NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to

enable superior text display. Eight graphics resolutions are supported up to 1024 X 768 with full vertical and

horizontal underscan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create

outstanding video quality. Support is provided for Macrovision and RGB bypass mode which enable driving a

VGA CRT with the input data.

The W83L950D is a high performance micro-controller on-chip supporting functions optimized for embedded

control. These include ROM, RAM, four types of timers, a serial communication interface, optional I²C bus

interface, host interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system

configurations, so that compact, high performance systems can be implemented easily.

A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME,

Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus

mastering IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled

power shutdown.

Following chapters will have more detail description for each individual sub-systems and functions.

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1.2 System Overview

Mobile Pentium-M Processor 1.5G ~ 1.9GHz/Dothan 2.0GHz and above

Thermal spec 35W TDP

Core logic Intel 855GME + ICH4-M chipset

VGA Control ATi M10

System BIOS ST39SF040

DDR RAM : Apacer : 77.11021.460 Samsung 16*16 256MB 1st

Apacer : 77.11021.580 Winbond 16*16 256MB 2nd

A-DATA : 256MB

Video Memory Share memory 32Mb

Clock Generator ICS 950812

TV ATi M10

IEEE1394 VT6307L

LAN RTL8100C

PCMCIA + 4 IN 1 CARD ENE CB710

AC97 CODEC: Advance Logic, Inc, ALC655

Power Amplifier: TI TPA0212

Modem AC97 Link: MDC (Mobile Daughter Card) Askey: V1456VQL-P1(INT)

CPU

Memory

Audio System

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Intel Banias Processors with 478 pins Micro-FCPGA package.

The first Intel mobile processor with the Intel Net Burst micro-architecture which features include hyper-pipelined

technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced dynamic execution,

advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2).

The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications

including 3-D graphics, video decoding/encoding, and speech recognition.

Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four

times per bus clock.

Support Enhanced Intel Speed Step technology, which enables real-time dynamic switching of the voltage and

frequency between two performance modes.

1.3.2 Clock Generator

System frequency synthesizer: ICS950812 Programmable output frequency, divider ratios, output rise/fall time,

output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if

1.3 System Hardware Parts

1.3.1 Intel Banias Processors in Micro-FCPGA Package

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1.3.3 Montara-GME GMCH IGUI 3D Graphic DDR/SDR Chipset

system malfunctions. Programmable watchdog safe frequency. Support I2C Index read/write and block read/write

operations. Use external 14.318MHz crystal.

Montara-GME GMCH IGUI Host Memory Controller integrates a high performance host interface for Intel

Banias processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP

4Xinterface, and Intel®’ I/O Hub architecture INTEL 82801DBM ICH4-M

Montara-GME GMCH Host Interface features the AGTL & AGTL+ compliant bus driver technology with

integrated on-die termination to support Intel Banias processors. Montara-GME GMCH provides a 12-deep In

Provides standard frequencies and additional 5% and 10% over-clocked frequencies

Supports spread spectrum modulation: No spread, Center Spread (±0.35%, ±0.5%,or ±0.75%), or Down

Spread (- 0.5%, -1.0%, or -1.5%)

Offers adjustable PCI early clock via latch inputs

Selectable 1X or 2X strength for REF via I2C interface

Efficient power management scheme through PD#,CPU_STOP# and PCI_STOP#.

Uses external 14.318MHz crystal

Stop clocks and functional control available through

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-Order-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D

Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for

the Intel Banias series based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory

controller to sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as

well as the multi I/O masters. In addition to integrated GUI, Montara-GME GMCH also can support external AGP

slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature Intel®’ I/O Hub

architecture is incorporated to connect Montara-GME GMCH and INTEL 82801DBM ICH4-M together. Intel®’

I/O Hub architecture is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB

bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O

Link layer, the Multi-threaded I/O Link Encoder/Decoder in INTEL 82801DBM ICH4-M to transfer data w/ 533

MB/s bandwidth from/to Multi-threaded I/O Link layer to/from Montara-GME GMCH, and the Multi-threaded

I/O Link Encoder/Decoder in Montara-GME GMCH to transfer data w/ 533 MB/s from/to Multi-threaded I/O

Link layer to/from INTEL 82801DBM ICH4-M.

An Unified Memory Controller supporting DDR266 DRAM is incorporated, delivering a high performance data

transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP

master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining

the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The Montara-GME GMCH

adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by

organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.

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