Motorola M68360QUADS-040 Bedienungsanleitung

MOTOROLA

SIX SIGMA

MICROPROCESSOR & MEMORY

TECHNOLOGIES GROUP

M68360QUADS-040

User’s Manual

ISSUE 1.0 - DRAFT

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M68360QUADS-040 - User’s Manual

Draft 1.0

TABLE OF CONTENTS

1 - GENERAL INFORMATION 7

1.1 INTRODUCTION 7

1.2 RELATED DOCUMENTATION 7

1.3 ABBREVIATIONS USED IN THE DOCUMENT 7

1.4 SPECIFICATIONS 7

1.5 COOLING REQUIREMENTS 8

1.6 FEATURES 9

1.7 HARDWARE BLOCK DIAGRAM 10

2 - Hardware Preparation and Installation 11

2.1 INTRODUCTION 11

2.2 UNPACKING INSTRUCTIONS 11

2.3 HARDWARE PREPARATION 11

2.3.1 ADI Port Address Selection 13

2.3.2 Caches Enable / Disable 14

2.3.3 MMU Enable / Disable 14

2.3.4 Parity Error Interrupt Generation 14

2.3.5 Arbitration Configuration 14

2.3.6 EEST Configuration 14

2.3.7 User Selectable Options 14

2.4 INSTALLATION INSTRUCTIONS 14

2.4.1 +5V Power Supply Connection 15

2.4.2 P7: +12V Power Supply Connection 15

2.4.3 ADI Installation 15

2.4.4 Host computer to M68360QUADS-040 Connection 15

2.4.5 Terminal to M68360QUADS-040 RS-232 Connection 16

3 - OPERATING INSTRUCTIONS 17

3.1 INTRODUCTION 17

3.2 CONTROLS AND INDICATORS 17

3.2.1 SOFT RESET Switch SW1 17

3.2.2 ABORT Switch SW2 17

3.2.3 HARD RESET - Switches SW1 & SW2 17

3.2.4 EEST Configuration Jumpers J1 to J6 17

3.2.4.1 TPEN Jumper - J1 17

3.2.4.2 APORT Jumper - J2 17

3.2.4.3 TPAPCE Jumper - J3 17

3.2.4.4 TPSQEL Jumper - J4 17

3.2.4.5 TPFULDL Jumper - J5 18

3.2.4.6 LOOP - Diagnostic Loopback Jumper - J6 18

3.2.5 Hardware Breakpoint Usage Jumper - J7 18

3.2.6 Parity Error Interrupt Jumper - J8 18

3.2.7 Bus Request Jumper - J9 18

3.2.8 Bus Grant Jumper - J10 18

3.2.9 HALT Indicator - LD10 18

3.2.10 040RUN Indicator - LD8 18

3.2.11 DMARUN Indicator - LD9 19

3.2.12 Ethernet TX Indicator - LD3 19

3.2.13 Ethernet RX Indicator - LD2 19

3.2.14 Ethernet CLSN Indicator LD4 19

3.2.15 Ethernet LIL Indicator - LD5 19

3.2.16 Ethernet PLR Indicator - LD6 19

3.2.17 Ethernet JABB Indicator - LD1 19

3.2.18 POWER Indicator - LD7 19

3.3 MEMORY MAP 19

3.3.1 Main Memory Map 20

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M68360QUADS-040 - User’s Manual

Draft 1.0

TABLE OF CONTENTS

3.4 Programming the slave QUICC 21

3.4.1 Module Base Address Register 21

3.4.2 Module Configuration Register 21

3.4.3 CLKO Control Register 21

3.4.4 PLL Control Register 21

3.4.5 Port E Pin Assignment Register 21

3.4.6 System Protection Control 21

3.4.7 Global Memory Register 22

3.4.8 Base Register 0 and Option Register 0 22

3.4.9 Base Register 1 and Option Register 1 22

3.4.10 Base Register 2 and Option Register 2 23

3.4.11 Base Register 3 and Option Register 3 23

3.4.12 Base Register 4 and Option Register 4 23

3.4.13 Base Register 5 and Option Register 5 24

3.4.14 Base Register 6 and Option Register 6 24

3.4.15 Base Register 7 and Option Register 7 24

3.4.16 Port A Open Drain Register 24

3.4.17 Port A Data Register 24

3.4.18 Port A Data Direction Register 24

3.4.19 Port A Pin Assignment Register 24

3.4.20 Port B Open Drain Register 24

3.4.21 Port B Data Register 24

3.4.22 Port B Data Direction Register 25

3.4.23 Port B Pin Assignment Register 25

3.4.24 Port C Data Register 25

3.4.25 Port C Data Direction Register 25

3.4.26 Port C Pin Assignment Register 25

3.4.27 Port C Special Options Register 25

4 - FUNCTIONAL DESCRIPTION 26

4.1 INTRODUCTION 26

4.2 Master MC68EC040 26

4.2.1 RESET for the 68EC040 & the QUICC 26

4.2.2 Utilizing the MC68EC040 Data Cache 27

4.3 Interrupts on the M68360QUADS-040 27

4.3.1 ABORT Push-button 27

4.3.2 Host - NMI 28

4.3.3 Hardware-Breakpoint Interrupt 28

4.3.4 Parity Error Interrupt 28

4.3.5 Host Request / Acknowledge Interrupt 28

4.4 Bus Arbitration 28

4.5 System Utilities 29

4.5.1 Breakpoints Generator 29

4.5.2 Bus Monitor 29

4.5.3 Spurious Interrupt Monitor 30

4.5.4 software Watch-Dog 30

4.5.5 Periodic Interval Timer - PIT 30

4.6 Clock Generator 30

4.7 Flash PROM 30

4.8 Bursting SRAM 30

4.9 EEPROM 31

4.10 DRAM 31

4.11 Slave QUICC 31

4.11.1 DRAM Controller 32

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M68360QUADS-040 - User’s Manual

Draft 1.0

TABLE OF CONTENTS

4.11.2 Chip Select TA~ and DSACK~ Generator 32

4.11.3 ADI Port 32

4.11.3.1 ADI Port Signal Description 33

4.11.4 RS-232 Serial Port 34

4.11.4.1 RS-232 Port Signal Description 35

4.11.5 M68360QUADS-040 Status Register 35

4.11.5.1 Status Register Bits Description 35

4.11.6 Ethernet Controller 36

4.11.6.1 Ethernet AUI Ports Signal Description 36

4.11.6.2 Ethernet Twisted-Pair Port Signal Description 37

4.11.7 Serial EEPROM 37

4.11.8 Slave QUICC General Purpose I/O Pins 37

4.11.8.1 Slave QUICC Port A 37

4.11.8.2 Slave QUICC Port B 38

4.11.8.3 Slave QUICC Port C 39

4.11.8.4 Slave QUICC Port E 40

5 - SUPPORT INFORMATION 41

5.1 INTRODUCTION 41

5.2 INTERCONNECT SIGNALS 41

5.2.1 Connector P1 Interconnect Signals 41

5.2.2 Connector P2 Interconnect Signals 42

5.2.3 Connector P3 Interconnect Signals 42

5.2.4 Connector P4 Interconnect Signals 43

5.2.5 Connector P5 Interconnect Signals 43

5.2.6 Connector P6 Interconnect Signals 44

5.2.7 Connector P7 Interconnect Signals 44

5.2.8 Connector P8 Interconnect Signals 44

5.2.9 Connector P9 Interconnect Signals 45

5.2.10 Connector P10 Interconnect Signals 47

5.2.11 Connector P11 Interconnect Signals 47

5.3 M68360QUADS-040 Parts List 47

A.1 INTRODUCTION 51

A.2 IBM-PC/XT/AT to M68360QUADS-040 Interface 51

A.2.1 ADI Installation in IBM-PC/XT/AT 51

A.3 SUN-4 to M68360QUADS-040 Interface 52

A.3.1 ADI Installation in the SUN-4 53

APPENDIX B - ADI PORT HANDSHAKE DESCRIPTION 55

B.1 INTRODUCTION 55

B.2 ADI Port Concept and Operation Description 55

B.3 Handshake Description 55

B.3.1 Write Cycle from Host to M68360QUADS-040 56

B.3.2 Write Cycle from M68360QUADS-040 to Host 57

B.3.3 M68360QUADS-040 Interrupt to the Host 58

B.3.4 Host Interrupt to the M68360QUADS-040 59

B.3.5 Host Reset to the M68360QUADS-040 59

B.3.6 Addressing All M68360QUADS-040 59

APPENDIX C - PALS’ EQUATIONS 60

C.1 U10 - Indicators Logic 60

C.2 U11 - Reset & Abort Generator 61

C.3 U12 - ADI Controller 64

C.4 U23 - Core Disable Logic 65

C.5 U32 - Bursting Sram Controller 68

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M68360QUADS-040 - User’s Manual

Draft 1.0

LIST OF FIGURES

FIGURE 2-1 M68360QUADS Location diagram 12

FIGURE 2-2 Configuration Dip-Switch - DSW1 13

FIGURE 2-3 P6: +5V Power Connector 15

FIGURE 2-4 P6: +12V Power Connector 15

FIGURE 2-5 P1 - ADI Port Connector 16

FIGURE 2-6 P2 - RS-232 Serial Port Connector 16

FIGURE 4-1 Arbitration Scheme: 29

FIGURE 4-2 ADI Port Connector 33

FIGURE 4-3 RS-232 Serial Port Connector 35

FIGURE 4-4 Status Register 35

FIGURE 4-5 Ethernet AUI Port Connector 36

FIGURE 4-6 Ethernet Twisted-Pair Port Connector 37

FIGURE A-1 Physical Location of jumper JG1 and JG2 52

FIGURE A-2 JG1 Configuration Options 52

FIGURE A-3 ADI board for SBus 53

FIGURE B-1 Host Computer (ADI) to M68360QUADS-040 Connection 56

FIGURE B-2 Host Write to M68360QUADS-040 57

FIGURE B-3 M68360QUADS-040 Write Cycle to Host 58

FIGURE B-4 M68360QUADS-040 Interrupt to Host 59

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M68360QUADS-040 User’s Manual

Draft 1.0

LIST OF TABLES

TABLE 1-1. M68360QUADS-040 Specifications 1

TABLE 3-1. EC040 Cycle Types and Responding Devices 13

TABLE 3-2 M68360QUADS-040 Main Memory Map 14

TABLE 4-1. DRAM SIMM Types 27

TABLE 4-2 Port A Pins Description 34

TABLE 4-3 Port B Pins Description 35

TABLE 4-4 Port C Pins Description 36

TABLE 5-1 Connector P1 Interconnect Signals 37

TABLE 5-2 Connector P2 Interconnect Signals 38

TABLE 5-3 Connector P3 Interconnect Signals 38

TABLE 5-4 Connector P8 Interconnect Signals 39

TABLE 5-5 Connector P5 Interconnect Signals 39

TABLE 5-6 Connector P6 Interconnect Signals 40

TABLE 5-7 Connector P7 Interconnect Signals 40

TABLE 5-8 Connector P8 Interconnect Signals 40

TABLE 5-9 Connector P9 Interconnect Signals 41

TABLE 5-10 Parts List 43

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M68360QUADS-040 Hardware User’s Manual GENERAL INFORMATION

1 - GENERAL INFORMATION

1.1 INTRODUCTION

This document describes the evaluation board for the MC68EC040 - MC68360 combination called the

M68360QUADS-040. This board is constructed with an MC68EC040 as the master processor and a

MC68360 (QUICC) as a slave in MC68EC040 companion mode. The purpose of this board is to evaluate

the performance of the above combination, rather than serve as a development system. .

1.2 RELATED DOCUMENTATION

• MC68360 User’s Manual.

• MC68EC040 User’s Manual.

• MC68LC040 User’s Manual.

• ADI board specification.

1.3 ABBREVIATIONS USED IN THE DOCUMENT

• QUADS - Application Development System for the QUICC device.

• ADI - Application Development Interface.

• UART - Universal Asynchronous Receiver/Transmitter.

• SIMM - Single In-line Memory Module.

• AUI - Attachment Unit Interface.

• SPI - Serial Peripheral Interface

• NMI - Non Maskable Interrupt

• EEST - Enhanced Ethernet Serial Transceiver the MC68160

• SIA - Serial Interface Adapter, the Am7992

• TP - Twisted Pair

• nsec - nano second

1.4 SPECIFICATIONS

The M68360QUADS-040 specifications are given in TABLE 1-1. Paragraph 1.5 details the cooling

requirements.

TABLE 1-1. M68360QUADS-040 Specifications

CHARACTERISTICS SPECIFICATIONS

Power requirements (no other boards attached) +5Vdc @ 3.5 A (typical), 5 A (maximum)

+12Vdc - Determined by the Ethernet network

Microprocessor XC68EC/LC040FE33

@ 25 MHz

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M68360QUADS-040 Hardware User’s Manual GENERAL INFORMATION

1.5 COOLING REQUIREMENTS

The M68360QUADS-040 is specified, designed, and tested to operate reliably with an ambient air

temperature range from 0

C to 30

C. This, due to the overheating problems of the XC68EC040 as the

68EC040

must

have a heat-sink attached to it for proper operation at room

temperature. Therefore, the

ambient temperature of operation for the M68360QUADS-040

should never exceed 30

a. The 12V supply is not used on the board, it is connected only to the Ethernet AUI connectors P3 & P5 to be supplied

to the network. Therefore, the power consumption of that supply is independent of the M68360QUADS-040.

b. 33 MHz components are used to get better s.u. timing between the QUICC & the EC040.

c. Since A28 to A31 of the slave QUICC are used as Write-Enable signals, the on-board addressing space is reduced

to 256 MBytes.

1. If no heat sink is attached to the 68EC040, maximum ambient temperature allowed @ 25 Mhz is -4

C !!!

Addressing

Total address range:

on-board -

Off-board -

Flash Memory

Dynamic RAM

EEPROM

256 MBytes

4 GigaBytes

512 KByte, 32 bits wide expandable to 2 MBytes

1 MByte, 36 bits wide SIMM (32 bit data, 4 bit parity)

option to use higher density SIMM, up to 8 MByte

256 Byte, serial EEPROM

Operating temperature 0

C - 30

Storage temperature -25

C to 85

Relative humidity 5% to 90% (non-condensing)

Dimensions:

Height

Depth

Thickness

9.173 inches (233 mm)

6.3 inches (160 mm)

0.063 inches (1.6 mm)

TABLE 1-1. M68360QUADS-040 Specifications

CHARACTERISTICS SPECIFICATIONS

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M68360QUADS-040 Hardware User’s Manual GENERAL INFORMATION

1.6 FEATURES

Following are the main features of the M68360QUADS-040:

❏

Master MC68EC040FE33 with 32-bit address bus, 32 bit data bus, instruction and data caches.

❏

Supports also MC68LC040.

❏

1 Mbyte Dynamic RAM, 60 nsec access time, 36 bits wide (data and parity) SIMM, accessed with

3,2,2,2 clock cycles. Support for dram SIMMs upto 8 Mbyte with automatic size and speed

detection.

❏

512 Kbyte Flash PROM, On-board (5V) programmable, individual sector protection, 32 bits wide,

120 nsec access time, support is given up to 2 Mbyte.

❏

128K byte synchronous bursting sram, 36 bits wide, 12 nsec access time. Accessed with 3,1,1,1

clock cycles. Option for additional 128K Byte identical bank.

❏

256 byte serial EEPROM, accessed by the SPI port.

❏

Application Development Interface (ADI) port via 37 pin D-type connector.

❏

Serial RS-232 port for terminal or host computer connection via 9 pin Dtype connector.

❏

Two

Ethernet ports:

1. The first using Motorola’s MC68160 (EEST) with both AUI and TP connectors.

2. The second using AMD’s Am7992 (SIA) with AUI connector.

❏

SCC2 (connected to the second Ethernet port) may be used for other purpose, by removing the

SIA from its socket.

❏

Expansion and Logic Analyzer connectors for both slave QUICC and MC68EC040.

❏

Slave QUICC (core disabled in 68EC040 companion mode) providing the following functions:

1. DRAM Controller

2. Chip Select, TA~ and DSACK~ generator.

3. Parallel port (ADI) controller.

4. UART for terminal or host computer connection.

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M68360QUADS-040 Hardware User’s Manual GENERAL INFORMATION

5. Dual-port Ethernet controller.

❏

VMEbus double-height board dimensions

❏

SOFT-RESET, HARD-RESET and ABORT switches.

❏

Status LEDs for power, EC040 run, DMA run, HALT and Ethernet signals.

❏

Single +5Vdc power supply.

1.7 HARDWARE BLOCK DIAGRAM

1 MByte DRAM

256 Byte

EEPROM ADI Port RS-232 Port

Expansion Connectors

Logic Analyzer Connectors

MC68EC/LC040

(master)

QUICC

(slave)

Ethernet Port

EEST

MC68160

512 KByte

Flash-PROM

AUI Connector

Ethernet Port T.P

RJ-45 Connector

(32 bits wide)

(Serial)

(36 bits wide SIMM)

with parity

256 K Byte

Burst SRAM

(36 bit wide)

Staus Register

SIA

AM7992

Ethernet Port

AUI Connector

RESET,

Interrupt &

Indications

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