Motorola MB68k-100 Bedienungsanleitung

Rev. A

Grant K.

68000 Motherboard User’s Manual Rev. A

Page 2 of 54

TABLE OF CONTENTS

1INTRODUCTION .......................................................... 4

2DESIGN MOTIVATION .................................................. 4

3DESIGN INSPIRATION ................................................. 4

4WHAT IS A COMPUTER?............................................... 7

5THE MB68K-100 COMPUTER .......................................13

5.1 MB68k-100 Specification ........................................................13

5.2 What’s What and Where Is It..................................................15

6ARCHITECTURAL OVERVIEW ........................................15

6.1 Basic Block Level Description .................................................16

6.2 Glimpse of the 68000..............................................................18

6.3 Bus Architecture of the 68000 ................................................18

6.4 Bus Control Signal Timing .......................................................19

6.4.1 Regular Bus Cycle Termination.............................................19

6.4.2 Bus Termination into a 6800 Bus Cycle .................................22

7CIRCUIT DESCRIPTION...............................................22

7.1 Power Input ...........................................................................22

7.1.1 Voltage Regulation ..............................................................23

7.1.2 Active Rev ersed Conn ection Protection ...............................23

7.1.3 Discrete Voltage Supervisor ................................................23

7.2 The 68000 Microprocessor ......................................................24

7.3 The ‘Pintercept’ Headers ........................................................24

7.4 Indicators ..............................................................................24

7.5 The System Clock....................................................................25

7.6 External Run Control ..............................................................27

7.7 Reset Pulse Generator ............................................................27

7.8 The Start Vector Selector (SVS) ...............................................28

7.9 Address Space Mapping ..........................................................29

7.10 Data Strobed Flow Logic .......................................................30

7.11 Bus Cycle Termination ..........................................................30

7.11.1 Bus Termination with Auto /DTACK .....................................31

7.11.2 Bus Termination with /VPA.................................................31

7.11.3 Bus Termination with /BERR ...............................................31

7.11.4 Wait State Generator .........................................................32

7.12 On-Board Peripherals ...........................................................32

7.12.1 Interrupt Enable Register ..................................................33

7.12.2 The Clock Synchronization Register ...................................33

7.12.2.1 On-Board Interrupt Logic Level..................................................... 34

7.12.2.2 The Hardware Entropy Generator .................................................. 34

7.12.2.3 On-Board Digital Input Interface .................................................. 36

68000 Motherboard User’s Manual Rev. A

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7.12.3 On-Board Output Latch.......................................................37

7.13 Interrupt Logic.....................................................................37

7.14 On-Board Memory Banks 0/1 ................................................38

7.15 Stack Interface ....................................................................39

7.15.1 Stack Interface Connectors ...............................................39

7.15.2 Mounting Holes ..................................................................41

7.16 Quick Jumper Reference .......................................................43

8THE SOFTER SIDE ......................................................46

8.1 Software Development Tools ..................................................46

8.1.1 m68k-elf .............................................................................46

8.1.2 EASy68K ..............................................................................47

8.2 MB68k-100 Software Examples ..............................................47

8.3 Software Notes on the MB68k-100 .........................................50

9GETTING STARTED......................................................51

10 TROUBLESHOOTING ..................................................52

11 DESIGN ERRATA AND COMMENTARY ............................ 52

12 PROJECT DOCUMENT COMPENDIUM ............................ 54

13 DOCUMENT REVISION HISTORY ..................................54

68000 Motherboard User’s Manual Rev. A

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1Introduction

This project was born of no less than a childhood dream. Granted this dream had long

been somewhat vague, abstract and surviving well below the threshold of any actual

attention. But the robust desire to develop a 68000 based computer had maintained an

ever-present persistence within my hobbyist heart. And finally events have coalesced

into its fruition.

The MB68k-100 single board computer offers a platform of approachable

experimentation around Motorola’s famed 68000 microprocessor. Whether inspired by

the straightforward elegance of this particular processor at its core or by a more general

interest in computer architecture overall, the MB68k-100’s design philosophy is one to

emphasize clear understanding of the system at every level. With its discrete circuit

design, commented assembly language software examples and rich engineering and

process documentation, the project is intended to offer more than direct utility as an

embedded computer. It is meant as a launching pad, bringing to fruition future

technophile dreams.

2Design Motivation

As microprocessor technology has advanced over the past decades, an evolving spectrum

of processors has emerged into the marketplace. Examples from the early days of the

technology were stiflingly simple and fraught with debilitating resource limitations and

programming bottlenecks. In contrast, the more contemporary end of this spectrum

presents the highly integrated and massively sophisticated architectures of more recent

years, where the designer grapples with hundreds of pages of product documentation and

hundreds of tiny pins to connect. But along this gradient of microprocessor technology

stands Motorola’s 68000. With an architecture that captures the straightforward

computer designs of its past, this processor is accessible to circuitry that is easily

imagined and built. Yet the 68000 is also a pioneering design in its space, offering a

clear demonstration of the future elegance of orthogonal architecture and spacious

hardware resources. The 68000 is a link, carrying the best features of both old and new

eras of processor technology.

3Design Inspiration

In an environment of routine obsolesce, the 68000’s continuing 30 year production life

span speaks to the strength of its design. Its portfolio has ranged from advancing the

state-of-the-art upon its 1979 marketplace introduction through to its present day legacy

applications. Its reign includes a generation of top-of-the-line computers and

workstations of the early 1980’s. From there, it evolved to a commanding presence in the

embedded domain of the late 80’s though to the mid 1990’s. Beyond that, its sales

continue today, buried amongst the existing infrastructure of the modern world. And its

68000 Motherboard User’s Manual Rev. A

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contemporary incarnations, including the ColdFire and CPU32 families, maintain the

bloodline with a sustaining market share into the future.

Through its life, the 68000 has enjoyed many notable design wins. Among computers, it

was the processor of the original Macintosh systems, the Atari ST and the Commodore

Amiga, among others. Its presence was also known among UNIX workstations,

including the original Sun Microsystems and SGI systems. And it was also the heart of

renowned game consoles, such as the Sega Genesis and Neo Geo systems, as well as

many stand-alone arcade games. It found a home in an array of computer peripherals,

networking equipment and other high-end gadgetry. My own childhood laser printer

succumbed to the screwdriver, yielding a traditional 64-pin PDIP Motorola 68000 at its

core. This processor defined a generation of computing in each market it touched.

From its original design philosophy born

within Motorola of the mid to late 1970’s,

this processor was crafted with an eye

toward the future. The processor design

was conceived under no burden of

confining software backward compatibility.

This forward-looking mindset enabled the

design engineers to “break away from the

past,” as the processor’s User’s Manual

cover art asserts. The first generation

sports a 32-bit architecture, masquerading

in 16-bit hardware. Although later

descendants expanded to true 32-bit form,

the 68000’s 32-bit data and address

registers are siphoned to the outside world

through a 16-bit data bus and 24-bit address

bus. These copious data and address

registers, provide a spacious backdrop to

efficient and elegant software development.

To further this elegance, the instruction set

of the 68000 was designed to be orthogonal, with a highly regular structure. The

instructions had nearly identical access to all addressing modes, moving beyond the

dedicated use of specific registers for specific functions. The 68000 internally features

two parallel 16-bit Arithmetic Logic Units for the fast calculation of addresses. From this

emerges the brilliant selection of available addressing modes, including the pre-

decrement and post-increment capabilities. The dazzling number of address modes takes

getting used to, when approaching with a background either in the primitive 8-bit devices

preceding the 68000 or the frugal RISC designs of today.

The generous selection of 14 addressing modes and impressive count of 56 instruction

types owes thanks to the 68000’s 16-bit data bus. This bus width enables a base op code

of 16-bits, rendering wide flexibility in defining the instruction’s operation. Processor

68000 Motherboard User’s Manual Rev. A

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instructions could include additional 16-bit data fetches beyond that to further extend the

operation. For speed, the 68000 employs a Prefetch Queue, where future memory reads

are anticipated and read while the bus would otherwise be idle. This improves

performance in that data may already be available in the processor when the advancing

program operation needs it. And code execution departs from typical technology of the

day in the 68000. It executes code in one of two modes: User or Supervisor. Supervisor

mode allows access to additional operations that are prohibited in User mode. This

enforces a greater degree of security in the code execution, and also maintains separate

User and Supervisor stacks to keep the stacks from having to bare each other’s weight.

Seven levels of interrupts are recognized by the processor, where only higher levels of

priority are permitted to capture current execution. And showing true chivalry for its

power, the 68000 also offers bus arbitration, relinquishing bus mastership to share the

system with other devices upon request.

The 68000’s sophisticated design was born of its advanced implementation in silicon. A

relatively late arrival to the 16-bit processor field, Motorola’s 68000 design was able to

leverage an increased level of integration on silicon. Constructed in superior HMOS

(High Density, Short Channel MOS) technology, the pull-up device in each gate’s output

stage is a heavily doped depletion-mode field effect transistor (FET). This FET initially

operates largely as a current source rather than a simple resistor, allowing for a faster 0-

to-1 transition. This capability in turn translates to faster overall operation. And this

technology, with its 3.5µm feature size, also allowed a higher number of transistors to be

incorporated into the design.

Within its rumored 68,000 transistors, the 68000’s architecture receives additional benefit

from the in-depth analysis by Motorola engineering to tailor an instruction set for

optimum utility. The processor was designed with software in mind. Studying not only

the occurrence of instructions listed within software code but the frequency that they

occur in actual code execution, Motorola engineers included single instructions that fully

embody frequent functionality. An example of this is the Test Condition, Decrement and

Branch family of instructions that tests a condition, and only when false decrements a

counter. Then, only if that counter is not counted down to -1, execution takes the

specified branch. This convoluted function is useful in implementing conditional

software loops where the number of iterations is to be limited. Another example of this

highly-integrated function is the ability within the addressing mode to advance an address

need within software operations on a range of memory to include a separate instruction to

advance that pointer.

68000 Motherboard User’s Manual Rev. A

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Many earlier microprocessor

designs implemented their

instructions as sequences

defined directly in digital logic.

The 68000 offers a much richer

functionality within its

instructions through the use of

microcoding. Microcoding

defines the internal sequence to

carry out the instructions. It

does this through the use of

low-level programming

operating within the

microprocessor logic. Like the

drum pegs scrolling through a

music box, this microcoded

program controls the timing

and sequencing of various

parts of the internal

microprocessor logic to

execute the instruction. And

this idea extends further into

the use of nanocoding since

many instructions share

common functions.

Nanocoding implements a

deeper level of execution for

common sequences that appear

within the encoding of different instructions. A picture of the processor die is broken

down in Figure 1, indicating the function of each circuit section. Among the sections are

microcode and nanocode ROMs, control logic and, situated along the bottom, the data

Arithmetic Logic Unit and two address Arithmetic Logic Units.

The power and grace of the 68000 leaves a deep impression on the evolution of computer

and microprocessor technology. And in doing so, it leaves an impression on those with

interest in detailed hardware and software design. As both a historical milestone and a

strong example of approachable modern computing, the 68000 drives continued authority

decades after its inception.

4What is a computer?

Computers are programmable data processing devices. Central to their function is their

ability to move data internally, and much of the computer’s design is dedicated to this

purpose. Data in a digital computer is represented by binary digits, abbreviated as “bits.”

These bits can possess two possible states, either 0 or 1. This differs from the familiar,

base 10 numeral system, where each digit may be one of ten possibilities. The binary

Figure 1: 68000 Die Function Blocks

Source- BYTE Publications Inc.,

Design Philosophy Behind Motorola’s MC68000,

April 1983

68000 Motherboard User’s Manual Rev. A

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numeral system is base 2, meaning that only these two digits are available. In base 2 the

significance of each digit’s place along a binary number differs by a factor of 2. When

written, binary numbers are expressed with a trailing subscript 2. Like in the base 10

system, the number 12in binary represents a one. This is the ones place in the number,

20. But binary 102represents 2 or 21, whereas in base 10 system 1010 represents the

number ten or 101. Binary 1002represents 4 or 22. And 1112is a 7, 22+21+20.

Another useful numeral system is base 16, known as hexadecimal. Hexadecimal simply

offers the advantage of grouping multiple binary digits together. Since the sixteen

possible combinations of four binary digits may be more concisely represented as a single

hexadecimal digit, hexadecimal is the preferred numeral system for its compactness.

Each hexadecimal digit represents four binary digits, and therefore two hexadecimal

digits represent a single 8-bit byte.

Table 1: Numeral Systems

Base

(Dec)

(Bin)

000002

000012

000102

000112

001002

001012

001102

001112

010002

010012

011112

100002

(Hex)

0016

0116

0216

0316

0416

0516

0616

0716

0816

0916

0F16

1016

As this relates to the computer, these binary digits physically correspond to the voltages

present on the signals within the computer. The digit 1 is typically represented by a high

voltage, while 0 is a low voltage. A succession of numbers over time in a digital system

appears as a signal waveform on the wire, with a separate parallel wire for each digit’s

place.

All data stored and processed in a computer can be thought of as numbers, encoded

through these voltage states. Whatever medium the data represents, it is a number

defined by parallel binary states to the computer. An image, for example, is defined

numerically as an array of values specifying how much red, green and blue to display at

each pixel location. Sound data numerically represents the amount to deflect a speaker

over time, which in turn creates corresponding sound waves. Text is defined numerically

by mapping the alphabet of possible characters to numerical codes. The message text

data is then broken into a string of characters, and the character at each position in that

string is defined by its numerical code. Using the ASCII coding standard as an example,

if 1 is added to the text data for the letter ‘A,’ it becomes a ‘B.’ If 32 is added to ‘A,’ it

becomes ‘a.’ To a computer, the world resolves to nothing more than numbers. These

numbers, though, have different meanings depending on which input or output device

they are associated. But within the computer, the numbers are simply electrical states of

the circuitry, carrying digital information.

68000 Motherboard User’s Manual Rev. A

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Table 2: Extended ASCII Code Table

Table 3: ASCII Code Example

Character

ASCII Code

(Hexadecimal)

The hardware in the computer design is responsible for the routing of the digital

information to perform the computer’s operation. For example, the computer may be

controlling multiple elements of a digital light bar output according to the states set on a

series of digital inputs. Each light would be lit according to the pattern provided on the

digital input. In this case the processor reads the input and temporarily stores the

corresponding number. It then writes that number from the temporary storage to the

output circuit. In effect, the computer receives the number presented at the input and

transfers it to the driver circuit for the output.

In this light bar example, shown in Figure 2 below, the read operation consists of the

microprocessor first specifying that it wants to communicate with the digital input circuit.

It does this through its address bus. The address bus is a group of separate parallel wires

that carry the binary digits of the address. And as the name suggests, the address is a

number that uniquely specifies the device with which the processor requests to

communicate. Each device available to the processor has its own unique address. The

processor also sets the Read/Write, R/W!, signal. The state of this signal indicates

whether the operation being prepared is to be a Read or a Write. These terms are defined

in the sense of the processor: the Read reads data from the addressed device into the

processor, and conversely the Write writes data from the processor to the addressed

device. With the digital input circuit addressed and direction specified as Read, the

processor next issues the Address Strobe. This signal indicates to the system’s external

logic that the processor has finished setting up the signals for the operation, and the logic

may now begin serving the processor’s request. The system’s external decoding logic

then processes the request and signals to the addressed device that it is selected. That

device then recognizes in a Read cycle that it must report its data to the processor. The

processor and addressable device share another group of parallel connections for this

purpose, the Data Bus. After the data is established on the Data Bus by the device being

read, the external logic finally informs the microprocessor that its data is ready by

sending an acknowledgment signal to the processor. The processor then reads the data

from the Data Bus and moves on to the next operation.

68000 Motherboard User’s Manual Rev. A

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Figure 2: Data Flow Diagrams, Read

The mechanics of the Write operation, shown in Figure 3 below, closely follow the Read.

The target device is specified by its address. But the Read/Write line here indicates a

Write operation is to be executed. The Data Bus this time is driven by the processor with

the data to be written to target. The target device is selected by the decoding logic based

on its address, and it reads the data from the processor. The cycle is then closed with the

processor receiving the acknowledge signal that the Write operation is complete. In this

example, the light bar output driver is updated by the processor. Through these steps, the

input data is transferred to the light bar output.

Figure 3: Data Flow Diagrams, Write

The devices within the computer are organized under the control of the microprocessor.

The processor addresses the device required for the current operation, completes the data

transaction with that device and then continues to the next operation. The sequence of

operations that the microprocessor follows is the software program. The program is

comprised of a series of steps that coordinate the computer’s operation. These steps are

selected from among the set of basic functions that are directly executed by the processor.

Examples of these fundamental operations include reading data from memory or an input

device, doing arithmetic operations on data, making decisions on which part of the

program to execute next, and writing data to memory or output devices, to name a few.

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