NEC UPD75P3116 Bedienungsanleitung

1994

DATA SHEET

The

PD75P3116 replaces the

PD753108’s internal mask ROM with a one-time PROM, and features expanded

ROM capacity.

Because the

PD75P3116 supports programming by users, it is suitable for use in evaluation of systems in the

development stage using the

PD753104, 753106, or 753108, and for use in small-scale production.

Detailed information about functions is provided in the following User’s Manual. Be sure to read it before

designing:

PD753108 User’s Manual: U10890E

FEATURES

Compatible with

PD753108

Memory capacity:

• PROM: 16384 ×8 bits

• RAM: 512 ×4 bits

Can be operated in same power supply voltage range as the mask version

PD753108

• VDD = 1.8 to 5.5 V

On-chip LCD controller/driver

QTOPTM microcontroller

Remark QTOP microcontrollers are microcontrollers with on-chip one-time PROM that are totally supported by NEC.

This support includes writing application programs, marking, screening, and verification.

ORDERING INFORMATION

Part Number Package

PD75P3116GC-AB8 64-pin plastic QFP (14 ×14)

PD75P3116GK-8A8 64-pin plastic LQFP (12 ×12)

PD75P3116GC-8BS 64-pin plastic LQFP (14 ×14)

Caution This device does not provide an internal pull-up resistor connection function by means of mask

option.

PD75P3116

MOS INTEGRATED CIRCUIT

4-BIT SINGLE-CHIP MICROCONTROLLER

The mark shows major revised points.

Document No. U11369EJ3V0DS00 (3rd edition)

Date Published March 2002 N CP(K)

Printed in Japan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

PD75P3116

2Data Sheet U11369EJ3V0DS

FUNCTION OUTLINE

Item Function

Instruction execution time • 0.95, 1.91, 3.81, or 15.3

s (main system clock: @ 4.19 MHz)

• 0.67, 1.33, 2.67, or 10.7

s (main system clock: @ 6.0 MHz)

• 122

s (subsystem clock: @ 32.768 kHz)

Internal memory PROM 16384 ×8 bits

RAM 512 ×4 bits

General-purpose registers • 4-bit manipulation: 8 ×4 banks

• 8-bit manipulation: 4 ×4 banks

I/O ports CMOS input 8 Internal pull-up resistor connection can be specified by software setting: 7

CMOS I/O 20

Internal pull-up resistor connection can be specified by software setting: 12

Shared with segment pins: 8

N-ch open-drain I/O 4 13 V withstanding voltage

Total 32

LCD controller/driver • Segment number selection: 16/20/24 segments (switchable to CMOS I/O ports

in a batch of 4 pins, max. 8 pins)

• Display mode selection: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias),

1/3 duty (1/3 bias), 1/4 duty (1/3 bias)

Timers 5 channels: • 8-bit timer/event counter: 3 channels

(Can be used as 16-bit timer/event counter, carrier generator,

and timer with gate)

• Basic interval timer/watchdog timer: 1 channel

• Watch timer: 1 channel

Serial interface • 3-wire serial I/O mode ··· MSB/LSB first switchable

• 2-wire serial I/O mode

• SBI mode

Bit sequential buffer (BSB) 16 bits

Clock output (PCL) Φ, 524, 262, and 65.5 kHz (main system clock: @ 4.19 MHz)

Φ, 750, 375, and 93.8 kHz (main system clock: @ 6.0 MHz)

Buzzer output (BUZ) • 2,4,and32 kHz(

mainsystem clock:@ 4.19MHz orsubsystem clock:@ 32.768kHz

)

• 2.93, 5.86, 46.9 kHz (main system clock: @ 6.0 MHz)

Vectored interrupts • External: 3

• Internal: 5

Test inputs • External: 1

• Internal: 1

System clock oscillator • Ceramic/crystal oscillator for main system clock

• Crystal oscillator for subsystem clock

Standby function STOP/HALT mode

Power supply voltage VDD = 1.8 to 5.5 V

Package • 64-pin plastic QFP (14 ×14)

• 64-pin plastic LQFP (12 ×12)

• 64-pin plastic LQFP (14 ×14)

PD75P3116

Data Sheet U11369EJ3V0DS

CONTENTS

1. PIN CONFIGURATION (TOP VIEW)................................................................................................. 4

2. BLOCK DIAGRAM ............................................................................................................................ 6

3. PIN FUNCTIONS ............................................................................................................................... 7

3.1 Port Pins ................................................................................................................................................... 7

3.2 Non-Port Pins ........................................................................................................................................... 9

3.3 Pin I/O Circuits ......................................................................................................................................... 11

3.4 Recommended Connection of Unused Pins ......................................................................................... 13

4. Mk I AND Mk II MODE SELECTION FUNCTION ............................................................................. 14

4.1 Differences Between Mk I Mode and Mk II Mode................................................................................... 14

4.2 Setting of Stack Bank Selection (SBS) Register ................................................................................... 15

5. DIFFERENCES BETWEEN

PD75P3116 AND

PD753104, 753106, 753108 ............................... 16

6. MEMORY CONFIGURATION ........................................................................................................... 17

7. INSTRUCTION SET .......................................................................................................................... 19

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 28

8.1 Operation Modes for Program Memory Write/Verify ............................................................................ 28

8.2 Program Memory Write Procedure ......................................................................................................... 29

8.3 Program Memory Read Procedure ......................................................................................................... 30

8.4 One-Time PROM Screening .................................................................................................................... 31

9. ELECTRICAL SPECIFICATIONS .....................................................................................................32

10. CHARACTERISTIC CURVES (REFERENCE VALUES).................................................................. 47

11. PACKAGE DRAWINGS ................................................................................................................... 49

12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 52

APPENDIX A. LIST OF

PD75308B, 753108, AND 75P3116 FUNCTIONS......................................... 54

APPENDIX B. DEVELOPMENT TOOLS................................................................................................ 56

APPENDIX C. RELATED DOCUMENTS ............................................................................................... 65

PD75P3116

4Data Sheet U11369EJ3V0DS

1. PIN CONFIGURATION (TOP VIEW)

• 64-pin plastic QFP (14 ×14):

PD75P3116GC-AB8

• 64-pin plastic LQFP (12 ×12):

PD75P3116GK-8A8

• 64-pin plastic LQFP (14 ×14):

PD75P3116GC-8BS

Note Always connect the VPP pin directly to VDD during normal operation.

48 S12

47 S13

46 S14

45 S15

44 P93/S16

43 P92/S17

42 P91/S18

41 P90/S19

40 P83/S20

39 P82/S21

38 P81/S22

37 P80/S23

36 P23/BUZ

35 P22/PCL/PTO2

34 P21/PTO1

33 P20/PTO0

COM3

COM2

COM1

COM0

S10

S11

BIAS 2

VLC0 3

VLC1 4

VLC2 5

P30/LCDCL/MD0 6

P31/SYNC/MD1 7

P32/MD2 8

P33/MD3 9

Vss 10

P50/D4 11

P51/D5 12

P52/D6 13

P53/D7 14

P60/KR0/D0 15

P61/KR1/D1 16

P62/KR2/D2 17

P63/KR3/D3

RESET

XT1

XT2

VPP

VDD

P00/INT4

P01/SCK

P02/SO/SB0

P03/SI/SB1

P10/INT0

P11/INT1

P12/INT2/TI1/TI2

P13/TI0

Note

PD75P3116

Data Sheet U11369EJ3V0DS

PIN IDENTIFICATIONS

P00 to P03: Port 0 COM0 to COM3: Common output 0 to 3

P10 to P13: Port 1 VLC0 to VLC2: LCD power supply 0 to 2

P20 to P23: Port 2 BIAS: LCD power supply bias control

P30 to P33: Port 3 LCDCL: LCD clock

P50 to P53: Port 5 SYNC: LCD synchronization

P60 to P63: Port 6 TI0 to TI2: Timer input 0 to 2

P80 to P83: Port 8 PTO0 to PTO2: Programmable timer output 0 to 2

P90 to P93: Port 9 BUZ: Buzzer clock

KR0 to KR3: Key return 0 to 3 PCL: Programmable clock

SCK: Serial clock INT0, 1, 4: External vectored interrupt 0, 1, 4

SI: Serial input INT2: External test input 2

SO: Serial output X1, X2: Main system clock oscillation 1, 2

SB0, SB1: Serial data bus 0, 1 XT1, XT2: Subsystem clock oscillation 1, 2

RESET: Reset VPP: Programming power supply

MD0 to MD3: Mode selection 0 to 3 VDD: Positive power supply

D0 to D7: Data bus 0 to 7 Vss: Ground

S0 to S23: Segment output 0 to 23

PD75P3116

6Data Sheet U11369EJ3V0DS

2. BLOCK DIAGRAM

P20 to P23

P00 to P03

S0 to S1516

COM0 to COM34

BIAS

LCD

RESETVss

CPU clock Φ

Standby

control

X2X1 XT2XT1

System clock

generator

Main Sub

Clock

divider

Clock

output

control

fx/2

PCL/PTO2/P22

General-

purpose

Data

memory

(RAM)

512 ×4 bits

Bank

SBS

SP (8)

ALU

Program

counter (14)

Program

memory

(PROM)

16384 ×8 bits Decode

and

control

P10 to P13

P30/MD0 to

P33/MD3

P50/D4 to

P53/D7

P60/D0 to

P63/D3

P80 to P83

Port 0

Port 1

Port 2

Port 3

Port 5

Port 6

Port 8

Port 9 P90 to P93

LCD

controller/driver

4S16/P93 to

S19/P90

4S20/P83 to

S23/P80

LC0

LC1

LC2

SYNC/P31

LCDCL/P30

Clocked

serial

interface

SI/SB1/P03

INTCSI

Interrupt

control

INT0/P10

SO/SB0/P02

SCK/P01

TOUT0

INT1/P11

INT4/P00

INT2/P12/TI1/TI2

P60/KR0 to

P63/KR3

Bit sequential

buffer (16)

INT1

8-bit

timer/event

counter #1

8-bit

timer/event

counter #2

Cascaded

16-bit

timer/

event

counter

INTT2

INTT1

TI1/TI2/

P12/INT2

PTO1/P21

TOUT0

PTO2/

PCL/P22

INTT0 TOUT0

8-bit

timer/event

counter #0

TI0/P13

PTO0/P20

Basic

interval

timer/

watchdog

timer

INTBT

BUZ/P23 Watch

timer

INTW f

LCD

PD75P3116

Data Sheet U11369EJ3V0DS

3. PIN FUNCTIONS

3.1 Port Pins (1/2)

Pin Name I/O Alternate Function 8-Bit Status I/O Circuit

Function I/O After Reset TypeNote 1

P00 Input INT4 4-bit input port (Port 0) — Input

Connection of an internal pull-up resistor can be

P01 SCK specified by a software setting in 3-bit units. <F>-A

P02 SO/SB0 <F>-B

P03 SI/SB1 <M>-C

P10 Input INT0 4-bit input port (Port 1) — Input -C

Connection of an internal pull-up resistor can be

P11 INT1 specified by a software setting in 4-bit units.

P10/INT0 can be used to select a noise eliminator.

P12 TI1/TI2/INT2

P13 TI0

P20 I/O PTO0 4-bit I/O port (Port 2) — Input E-B

Connection of an internal pull-up resistor can be

P21 PTO1 specified by a software setting in 4-bit units.

P22 PCL/PTO2

P23 BUZ

P30 I/O LCDCL/MD0 Programmable 4-bit I/O port (Port 3) — Input E-B

Input and output can be specified in 1-bit units.

P31 SYNC/MD1 Connection of an internal pull-up resistor can be

specified by a software setting in 4-bit units.

P32 MD2

P33 MD3

P50Note 2 I/O D4 N-ch open-drain 4-bit I/O port (Port 5) — High M-E

When set to open-drain, the withstanding voltage impedance

P51Note 2 D5 is 13 V.

P52Note 2 D6

P53Note 2 D7

Notes 1. Circuit types enclosed in angle brackets indicate Schmitt-triggered input.

2. The low-level input leakage current increases when input instructions or bit manipulation instructions are

executed.

PD75P3116

8Data Sheet U11369EJ3V0DS

3.1 Port Pins (2/2)

Pin Name I/O Alternate Function 8-Bit Status I/O Circuit

Function I/O After Reset TypeNote 1

P60 I/O KR0/D0 Programmable 4-bit I/O port (Port 6) — Input <F>-A

Input and output can be specified in 1-bit units.

P61 KR1/D1 Connection of an internal pull-up resistor can be

specified by a software setting in 4-bit units.

P62 KR2/D2

P63 KR3/D3

P80 I/O S23 4-bit I/O port (Port 8) √Input H

Connection of an internal pull-up resistor can be

P81 S22 specified by a software setting in 4-bit unitsNote 2.

P82 S21

P83 S20

P90 I/O S19 Programmable 4-bit I/O port (Port 9) Input H

Connection of an internal pull-up resistor can be

P91 S18 specified by a software setting in 4-bit unitsNote 2.

P92 S17

P93 S16

Notes 1. Circuit types enclosed in angle brackets indicate Schmitt-triggered input.

2. Do not connect an internal pull-up resistor by software when these pins are used as segment signal outputs.

PD75P3116

Data Sheet U11369EJ3V0DS

3.2 Non-Port Pins (1/2)

Pin Name I/O Alternate Function Status I/O Circuit

Function After Reset TypeNote 1

TI0 Input P13 External event pulse input to timer/event counter Input -C

TI1 P12/INT2/TI2

TI2 P12/INT2/TI1

PTO0 Output P20 Timer/event counter output Input E-B

PTO1 P21

PTO2 P22/PCL

PCL P22/PTO2 Clock output

BUZ P23 Frequency output (for buzzer or system clock trimming)

SCK I/O P01 Serial clock I/O Input <F>-A

SO/SB0 P02 Serial data output <F>-B

Serial data bus I/O

SI/SB1 P03 Serial data input <M>-C

Serial data bus I/O

INT4 Input P00 Edge detection vectored interrupt input

(valid for detecting both rising and falling edges)

INT0 Input P10 Edge detection vectored interrupt

With noise eliminator/

Input -C

input (detection edge is selectable) asynchronous is

INT0/P10 can be used to select a selectable

INT1 P11 noise eliminator. Asynchronous

INT2 Input P12/TI1/TI2 Rising edge detection testable input Asynchronous

KR0 to KR3 I/O P60 to P63 Parallel falling edge detection testable input Input <F>-A

X1 Input — Ceramic/crystal resonator connection for main system — —

clock oscillation. If using an external clock, input the signal

X2 — to X1 and input the inverted signal to X2.

XT1 Input — Crystal resonator connection for subsystem clock oscillation. — —

If using an external clock, input the signal to XT1 and input

XT2 — the inverted signal to XT2. XT1 can be used as a 1-bit (test)

input.

RESET Input — System reset input (low-level active) —

MD0 to MD3 Input P30 to P33 Mode selection for program memory (PROM) write/verify Input E-B

D0 to D3 I/O

P60/KR0 to P63/KR3

Data bus for program memory (PROM) write/verify Input <F>-A

D4 to D7 P50 to P53 M-E

VPPNote 2 — — Programmable power supply voltage applied for program — —

memory (PROM) write/verify.

During normal operation, connect directly to VDD.

Apply +12.5 V for PROM write/verify.

VDD — — Positive power supply — —

Vss — — Ground potential — —

Notes 1. Circuit types enclosed in angle brackets indicate Schmitt-triggered input.

2. The VPP pin does not operate correctly when it is not connected to the VDD pin during normal operation.

PD75P3116

10 Data Sheet U11369EJ3V0DS

3.2 Non-Port Pins (2/2)

Pin Name I/O Alternate Function Status I/O Circuit

Function After Reset Type

S0 to S15

Output — Segment signal output Note 1 G-A

S16 to S19

Output P93 to P90 Segment signal output Input H

S20 to S23

Output P83 to P80 Segment signal output Input H

COM0 to COM3

Output — Common signal output Note 1 G-B

VLC0 to VLC2 — — Power supply for driving LCD — —

BIAS Output — Output for external split resistor cut Note 2 —

LCDCLNote 3 Output P30/MD0 Clock output for driving external expansion driver Input E-B

SYNCNote 3 Output P31/MD1 Clock output for synchronization of external expansion driver Input E-B

Notes 1. VLCX (X = 0, 1, 2) is selected as the input source for the display outputs as shown below.

S0 to S23: VLC1, COM0 to COM2: VLC2, COM3: VLC0

2. When the split resistor is incorporated: Low level

When the split resistor is not incorporated: High impedance

3. These pins are provided for future system expansion. Currently, only P30 and P31 are used.

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