NXP Semiconductors I.MX 8M Plus Bedienungsanleitung

i.MX 8M Plus Hardware Developer’s Guide

NXP Semiconductors Document identifier: IMX8MPHDG

User's Guide Rev. 0, 03/2021

Chapter 1

Overview

This document aims to help hardware engineers design and test the i.MX 8M Plus series processors. It provides examples on

board layout and design checklists to ensure first-pass success, and solutions to avoid board bring-up problems.

Engineers should understand board layouts and board hardware terminology.

This guide is released with relevant device-specific hardware documentation, such as datasheets, reference manuals, and

application notes. All these documents are available on www.nxp.com/imx8mplusevk.

1.1 Device supported

This document supports the i.MX 8M Plus (15 x 15 mm package).

1.2 Essential references

This guide is supplementary to the i.MX 8M Plus series chip reference manuals and data sheets. For reflow profile and thermal

limits during soldering, see General Soldering Temperature Process Guidelines (document AN3300). These documents are

available on www.nxp.com/i.MX8MPLUS.

1.3 Supplementary references

1.3.1 General information

The following documents introduces the Arm® processor architecture and computer architecture.

• For information about the Arm Cortex-A53 processor, see www.arm.com/products/processors/cortex-a/cortex-a53-

processor.php

• For information about the Arm Cortex-M7 processor, see https://www.arm.com/products/processors/cortex-m/cortex-m7-

processor.php

• Computer Architecture - A Quantitative Approach (Fourth Edition) - John L. Hennessy and David A. Patterson

• Computer Organization and Design - The Hardware/Software Interface (Second Edition) - David A. Patterson and John L.

Hennessy

The following documentation introduces the high-speed board design:

• Right the First Time- A Practical Handbook on High Speed PCB and System Design - Volumes I & II - Lee W. Ritchey

(Speeding Edge) - ISBN 0-9741936- 0-72

• Signal and Power Integrity Simplified (2nd Edition) - Eric Bogatin (Prentice Hall)- ISBN 0-13-703502-0

• High Speed Digital Design- A Handbook of Black Magic - Howard W. Johnson & Martin Graham (Prentice Hall) - ISBN

0-13-395724-1

• High Speed Signal Propagation- Advanced Black Magic - Howard W. Johnson & Martin Graham - (Prentice Hall) - ISBN

0-13-084408-X

• High Speed Digital System Design- A handbook of Interconnect Theory and Practice - Hall, Hall and McCall (Wiley

Interscience 2000) - ISBN 0-36090-2

• Signal Integrity Issues and Printed Circuit Design - Doug Brooks (Prentice Hall) ISBN 0-13-141884-X

• PCB Design for Real-World EMI Control - Bruce R. Archambeault (Kluwer Academic Publishers Group) - ISBN

1-4020-7130-2

• Digital Design for Interference Specifications - A Practical Handbook for EMI Suppression -David L. Terrell & R. Kenneth

Keenan (Newnes Publishing) - ISBN 0-7506-7282-X

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• Electromagnetic Compatibility Engineering - Henry Ott (1st Edition - John Wiley and Sons) - ISBN 0-471-85068-3

• Introduction to Electromagnetic Compatibility - Clayton R. Paul (John Wiley and Sons) - ISBN 978-0-470-18930-6

• Grounding & Shielding Techniques - Ralph Morrison (5th Edition - John Wiley & Sons) - ISBN 0-471-24518-6

• EMC for Product Engineers - Tim Williams (Newnes Publishing) - ISBN 0-7506- 2466-3

1.4 Related documentation

Additional literature will be published in the future.

For the list of current documents, see i.MX8MPLUS and AN4579.

1.5 Conventions

Table 1 lists the notational conventions used in this document.

Table 1. Conventions used in the document

Conventions Description

Courier Used to indicate commands, command parameters, code examples, and file and directory names.

Italics

Used to indicates command or function parameters.

Bold Function names are written in bold.

cleared/set When a bit takes the value zero, it means to be cleared; when it takes a value of one, it means to be set.

mnemonics Instruction mnemonics are shown in lowercase bold. Book titles in text are set in italics.

sig_name Internal signals are written in all lowercase.

nnnn nnnnh

Denotes hexadecimal number

0b Denotes binary number

rA, rB Instruction syntax used to identify a source GPR

rD Instruction syntax used to identify a destination GPR

REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets. For

example, MSR[LE] refers to the little-endian mode enable bit in the machine state register.

An italicized

indicates an alphanumeric variable.

n, m

An italicized

indicates a numeric variable.

In this document, notation for all logical, bit-wise, arithmetic, comparison, and assignment operations follow C

Language conventions.

1.6 Acronyms and abbreviations

Table 2 defines the acronyms and abbreviations used in this document.

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Table 2. Definitions and acronyms

Acronym Definition

ARM Advanced RISC Machines processor architecture

BGA Ball Grid Array package

BOM Bill of Materials

BSDL Boundary Scan Description Language

CAN Flexible Controller Area Network peripheral

CCM Clock Controller Module

CSI MIPI Camera Serial Interface

DDR Dual Data Rate DRAM

DDR4 DDR4 DRAM

DDRC DDR Controller

DFP Downstream Facing Port (USB Type-C)

DRP Dual Role Port (USB Type-C)

ECSPI Enhanced Configurable SPI peripheral

EIM External Interface Module

ENET 10/100/1000 Mbps Ethernet MAC peripheral

EPIT Enhanced Periodic Interrupt Timer peripheral

ESR Equivalent Series Resistance

GND Ground

GPC General Power Controller

GPIO General Purpose Input/Output

I2C Inter-integrated Circuit interface

IBIS Input output Buffer Information Specification

IOMUX i.MX 8M Plus chip-level I/O multiplexing

JTAG Joint Test Action Group

KPP Keypad Port Peripheral

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Table 2. Definitions and acronyms (continued)

Acronym Definition

LDB LVDS Display Bridge

LDO Low Drop-Out regulator

LPCG Low Power Clock Gating

LPDDR4 Low Power DDR4 DRAM

LVDS Low-Voltage Differential Signaling

ODT On-Die Termination

OTP One-Time Programmable

PCB Printed Circuit Board

PCIe PCI Express

PCISig Peripheral Component Interconnect Special Interest Group

PDN Power Distribution Network

PMIC Power Management Integrated Circuit

POR Power-On Reset

PTH Plated Through Hole PCB (that is, no microvias)

RGMII Reduced Gigabit Media Independent Interface (Ethernet)

RMII Reduced Media Independent Interface (Ethernet)

ROM Read-Only Memory

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Chapter 2

i.MX 8M Plus design checklist

This document provides a design checklist for the i.MX 8M Plus (15 x 15 mm package) processor. The design checklist tables

recommend optimal design and provide explanations to help users understand better. All supplemental tables referenced by the

checklist appear in sections following the design checklist tables.

2.1 Design checklist table

Table 3. LPDDR4 recommendations (i.MX 8M Plus)

Check box Recommendations Explanation/Supplemental recommendations

1. Connect the DRAM_ZN ball on the processor (ball

R1) to a 240 Ω, 1% resistor to GND.

This is a reference used during DRAM output

buffer driver calibration.

2. The ZQ0 and ZQ1 balls on the LPDDR4 device

should be connected through 240Ω, 1% resistors to the

LPDDR4 VDD2 rail.

—

3. Place a 10 kΩ, 5% resistor to ground on the DRAM

reset signal.

This will ensure adherence to the JEDEC

specification until the control is configured and

starts driving the DDR.

4. The ODT_CA balls on the LPDDR4 device should be

connected directly to the LPDDR4 VDD2 rail.

LPDDR4 ODT on the i.MX 8M Plus is command-

based, making processor ODT_CA output

balls unnecessary.

5. The architecture for each chip inside the DRAM

package must be x 16.

The processor does not support byte mode

specified in JESD209-4B.

6. The processor ball MTEST (ball P2), should be left

unconnected.

These are observability ports for manufacturing

and are not used otherwise.

7. The VREF pin on the processor (ball R2) can be left

unconnected.

The VREF signal for LPDDR4 is generated

internally by the processor.

8. It is strongly suggested to use LPDDR4 if lower

power consumption is required since DLL-off mode is

not supported.

The LPDDR4 can operate at low frequency

without DLL-off mode.

Table 4. DDR4 recommendations (i.MX 8M Plus)

Check box Recommendations Explanation/Supplemental recommendations

1. Connect the ZQ(DRAM_ZN) ball on the processor

(ball R1) to individual 240 Ω, 1% resistors to GND.

This is a reference used during DRAM output

buffer driver calibration.

2. The ZQ ball on each DDR4 device should be

connected through individual 240 Ω, 1% resistors to

GND.

—

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Table 4. DDR4 recommendations (i.MX 8M Plus) (continued)

Check box Recommendations Explanation/Supplemental recommendations

3. Place a 10 kΩ, 5% resistor to ground on the DRAM

reset signal.

This will ensure adherence to the JEDEC

specification until the control is configured and

starts driving the DDR.

4. The processor ball MTEST (ball P2), should be left

unconnected.

These are observability ports for manufacturing

and are not used otherwise.

5. If boundary scan mode of the DDR4 DRAM device

is to be used to test connectivity with the i.MX 8M

Plus, TEN pin of the DRAM device should be routed

to a test point and pulled to GND through a resistor.

Otherwise it can be directly connected to GND. See

Testing DDR4 connectivity using boundary scan for

details about the limitations of the DRAM_RESET_N

signal in the boundary scan mode.

TEN=HIGH makes the DDR4 DRAM device enter

boundary scan mode(connectivity test mode). For

normal operation, TEN must be LOW.

6. DLL-off mode is not supported, which means DDR4

cannot run in low frequency, such as 100 MTS.

The power consumption for low power mode

in DDR4 system will be higher compared with

LPDDR4 system.

Refer to i.MX 8M Plus data sheet for supported DDR chip selects and bus width configurations.

NOTE

Table 5. I2C recommendations

Check box Recommendations Explanation/Supplemental recommendations

1. Verify the target I2C interface clock rates

The I2C bus can only be operated as fast as the

slowest peripheral on the bus. If faster operation

is required, move the slow devices to another

I2C port.

2. Verify that there are no I2C address conflicts on any

of the I2C buses utilized

There are multiple I2C ports available on

chip, so if a conflict exists, move one of the

conflicting devices to a different I2C bus. If it

is impossible, use a I2C bus switch (NXP part

number PCA9646).

3. Do not place more than one set of pull-up resistors

on the I2C lines.

This could result in excessive loading and

potential incorrect operation. Choose the pull-

up value commensurate with the bus speed

being used.

4. Ensure that the VCC rail powering the i.MX 8M Plus

I2C interface balls matches the supply voltage used for

the pull-up resistors and the slave I2C devices.

Prevent device damage or incorrect operation due

to voltage mismatch.

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Table 6. JTAG recommendations

Check box Recommendations Explanation/Supplemental recommendations

1. Do not use external pullup or pulldown resistors on

JTAG_TDO.

JTAG_TDO is configured with an on-chip

keeper circuit and the floating condition is

actively eliminated.

2. Follow the recommendations for external pull-up and

pull-down resistors given in Table 15.

—

3. For normal operation, JTAG_MOD (ball G20) should

be pulled down using a 10KOhm resistor. To enter

boundary-scan mode, this pin should be pulled up

to NVCC_JTAG using a 2.2KOhm resistor. Please

reference “COMPLIANCE_PATTERNS” in the chip

BSDL file.

—

Table 7. Reset and ON/OFF recommendations

Check box Recommendations Explanation/Supplemental recommendations

1. The POR_B input must be asserted at powered

up and remain asserted until the last power rail for

devices required for system boot are at their working

voltage. This functionality is controlled by the PMIC

(PCA9450CHN) on EVK.

POR_B is driven by the PMIC. If a reset button is

used, it should be connected to the PMIC_RST_B

pin of the PMIC instead of directly connected

to POR_B pin of the CPU. When POR_B is

asserted (low) on the i.MX 8M Plus, the output

PMIC_ON_REQ remains asserted (high).

2. For portable applications, the ONOFF pin may be

connected to an ON/OFF SPST push-button switch to

ground. An external pull-up resistor is required on this

pin.

A brief connection to GND in OFF mode

causes the internal power management state

machine to change state to ON. In ON mode,

a brief connection to GND generates an interrupt

(intended to initiate a software-controllable power-

down). The connection to GND for approximate 5

seconds or more causes a forced OFF.

3. Connect GPIO1_IO02( WDOG_B, ball B6) to

external PMIC or reset IC to repower the system

except SNVS is strongly recommended.

i.MX8M Plus cannot be reset by internal reset

source in idle mode, repower is preferred. Some

peripherals like SD3.0, QSPI also need repower

during system reset.

4. GPIO1_IO02( WDOG_B, ball B6) is used as Cold

Reset. If using a PMIC other than PCA9450, an

external pull-up resistor (100 Kohm) might be required

to support boundary-scan mode.

In boundary-scan mode, WDOG_B is floating.

Without the external 100 Kohm pull up, WDOG_B

might repeatedly reset the system when entering

boundary-scan mode. The PCA9450 disables

WDOG_B reset by default, so will not be impacted.

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Table 8. PCIe recommendations

Check box Recommendations Explanation/Supplemental recommendations

1. Use an appropriate external PCIe reference clock

generator.

The NXP EVK board design uses an IDT

9FGV0241 device. However, NXP does not

recommend one supplier over another, and does

not suggest that this is the only clock generator

supplier. The device used should support all the

specs (jitter, accuracy, etc.).

2. The differential transmitters from the processor must

be AC coupled. It is recommended to use a 0.1 μF cap

on both the PCIE_TXP and PCIE_TXN outputs.

PCIe specification compliance requires AC

coupling at each transmitter. The receiver must be

DC coupled.

3. The PCIEx_RESREF ball (ball F16) should be

connected to the ground through a 8.2 K Ω, 1%

resistor.

—

Table 9. USB recommendations

Check box Recommendations Explanation/Supplemental recommendations

1. Connect a 200 Ω, 1% resistor to the ground on the

USBx_TXRTUNE ball (ball F10 and F12).

—

2. Route all USB differential signals with 90 Ω

differential impedance. —

3. ESD protection should be implemented at the

connector pins. Choose a low capacitance device

recommended for high-speed interfaces.

This will prevent potential damages to board

components from ESD.

4. USB1_DNU, USB2_DNU are not functional,

recommend to use common GPIO if USB identification

is needed.

—

5. If USB connector is MicroAB or MicroB,

USBx_VBUS must not connect directly to the 5 V

VBUS voltage of connector; Instead, this pin must be

isloated with an external 30 K 1% resistor.

—

6. PCB trace length of the USB3.0 TX/RX signals

should not exceed 6 inches in order for the eye

diagram to meet compliance test requirement.

—

Table 10. FlexSPI recommendations

Check box Recommendations Explanation/Supplemental recommendations

1. Read strobe(DQS) pad should be floated or with

a 10-18pF cap load to compensate SIO/SCK

pins load for high speed running, if the memory

device does not provide DQS.

There are three modes for the internal sample

clock for FlexSPI read data:

Dummy read strobe generated by

FlexSPI controller and looped back

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Table 10. FlexSPI recommendations

Check box Recommendations Explanation/Supplemental recommendations

internally(FlexSPIn_MCR0[RXCLKSRC] = 0x0),

can only reach 66Mhz operation frequency;

Dummy read strobe generated by FlexSPI

controller and looped back through the DQS

pad(FlexSPIn_MCR0[RXCLKSRC] = 0x1), can

reach 133Mhz operation frequency. In this mode,

this pin can be floated or put some cap loads on

board level to compensate SIO/SCK pins load;

Read strobe provided by memory device and input

from DQS pad(FlexSPIn_MCR0[RXCLKSRC] =

0x3), can reach 133Mhz operation frequency.

Table 11. Oscillator/Crystal recommendations

Check box Recommendations Explanation/Supplemental recommendations

1. Connect a 24 MHz crystal and a 510K Ω resistor

between 24M_XTALI and 24M_XTALO (balls G25 and

G26).

This crystal should have ESR not greater than 60

Ω, and be rated for a drive level of at least 100

µW. Follow the manufacturer’s recommendation

for loading capacitance. Use short traces between

the crystal and the processor, with a ground

plane under the crystal, load capacitors, and

associated traces.

2. Connect a 32.768 KHz crystal and a 4.7M Ω

feedback resistor (must install) between RTC_XTALI

and RTC_XTALO (balls J25 and J26). Alternatively, an

external 32.768 KHz clock can be fed into RTC_XTALI

to provide the RTC clock for the i.MX 8M Plus. See

item #3.

This crystal should have ESR not greater than 70

kΩ, and be rated for a drive level of at least 0.5

µW. Follow the manufacturer’s recommendation

for loading capacitance. Use short traces between

the crystal and the processor, with a ground

plane under the crystal, load capacitors, and

associated traces.

3. If using external 32.768 KHz clock rather than

a crystal to provide the RTC clock, it should be

connected to RTC_XTALI pin. The RTC_XTALO pin

should be connected to NVCC_SNVS_1P8 through a

100Kohm resistor.

The voltage level of this driving clock should

not exceed the voltage of the NVCC_SNVS_1P8

rail, or damage/malfunction may occur. The

RTC signal should not be driven if the

NVCC_SNVS_1P8 supply is OFF. For RTC

VIL and VIH voltage levels, see the latest

i.MX 8M Plus data sheet available at

www.nxp.com/i.MX8MPLUS.

Table 12. i.MX 8M Plus power/decoupling recommendations

Check box Recommendations Explanation/Supplemental recommendations

1. Comply with the power-up sequence guidelines

as described in the data sheet to guarantee reliable

operations of the device.

Any deviation from these sequences may result in

the following situations:

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