NXP Semiconductors A3M36SL039I Bedienungsanleitung

NXP reserves the right to change the detail specifications as may be required to permit improvements

in the design of its products.

The A3M36SL039 is a fully integrated Doherty power amplifier module

designed for wireless infrastructure applications that demand high

performance in the smallest footprint. Ideal for applications in massive MIMO

systems, outdoor small cells and low power remote radio heads. The field-

proven LDMOS power amplifiers are designed for TDD and FDD LTE

systems. The module integrates an autobias feature with the option to

overwrite production settings. Autobias automatically sets and regulates

transistor bias over temperature upon power up. An integrated sensor for

monitoring temperature is also present. Communications to the module can

be accomplished via either I2C or SPI.

3400–3800 MHz

Typical LTE Performance: Pout = 8 W Avg., VDD = 29 Vdc, 1 × 20 MHz LTE,

Input Signal PAR = 8 dB @ 0.01% Probability on CCDF.1

Carrier Center

Frequency

Gain

(dB)

ACPR

(dBc)

PAE

(%)

3410 MHz 29.5 –28.6 36.7

3600 MHz 29.8 –30.9 38.3

3790 MHz 29.4 –29.1 36.4

1. All data measured with device soldered in NXP reference circuit.

Features

• Advanced high performance in-package Doherty

• Fully matched (50 ohm input/output, DC blocked)

• Designed for low complexity analog or digital linearization systems

• Autobias on power up

• Temperature sensing

• Digital interface (I2C or SPI)

• Embedded registers and DACs for setting bias conditions

• Tx Enable control pin for TDD operation

A3M36SL039I

A3M36SL039S

3400–3800 MHz, 29 dB,

8 W Avg. Airfast Power

Amplifier Module with

Autobias Control

10 mm × 8 mm Module

A3M36SL039

Airfast Power Amplifier Module with Autobias Control

Rev. 0

—

December 2021

Data Sheet: Technical Data

A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021

Data Sheet: Technical Data 2/ 33

Contents

1Pinout configuration and function ..................3

1.1 Pin connections...............................................3

1.2 Functional pin description................................4

2Electrical characteristics..................................4

2.1 Ratings ............................................................4

2.1.1 Maximum ratings.............................................4

2.1.2 Lifetime............................................................5

2.1.3 ESD protection characteristics ........................5

2.1.4 Moisture sensitivity level..................................5

2.2 Operating characteristics.................................5

2.2.1 Nominal DAC settings .....................................5

2.2.2 Functional tests ...............................................6

2.2.3 Wideband ruggedness ....................................6

2.2.4 Typical performance........................................6

3Register map and OTP memory.......................7

3.1 One-time programmable memory....................7

3.2Register map...................................................7

4Power supply sequence .................................10

5Autobias functionality ....................................11

5.1 General overview ..........................................11

5.2 Operational overview.....................................11

5.3 Tx enable control...........................................12

5.4 Sense_DAC ..................................................12

5.5 VGS_DAC .....................................................13

5.6 Engineering Mode (EM) ................................13

6Ordering information ......................................13

7Component layout and parts list ................... 14

7.1 Component layout......................................... 14

7.2 Component designations and values ............ 15

8Temperature sensor .......................................15

9Communication interfaces............................. 16

9.1 SPI ................................................................ 16

9.1.1 SPI timing diagram........................................ 16

9.1.2 SPI instruction set definition.......................... 16

9.2 I2C ................................................................. 17

9.2.1 I2C addressing............................................... 17

9.2.2 I2C instruction set .......................................... 18

9.2.3 I2C Device ID Read instruction...................... 19

9.3 I2C electrical specification and timing for I/O

stages and bus lines ..................................... 20

9.3.1 I2C SCLK and SDA characteristics................ 21

9.3.2 I2C bus electrical characteristics ................... 22

10 Design considerations ...................................22

10.1 Power on sequence ...................................... 22

10.2 Programming guidelines to avoid hardware

failure or damage .......................................... 23

10.3 Group programming ...................................... 23

11 Product marking .............................................25

12 Package information.......................................26

13 Product software and tools............................32

14 Failure analysis...............................................32

15 Revision history.............................................. 32

Pinout configuration and function

A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021

Data Sheet: Technical Data 3/ 33

1 Pinout configuration and function

1.1 Pin connections

Figure 1. Pin connections

Electrical characteristics

A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021

Data Sheet: Technical Data 4/ 33

1.2 Functional pin description

Table 1. Functional pin description

Pin Number Pin Function Pin Description

1 VDC2 Carrier Drain Supply, Stage 2

2 VDC1 Carrier Drain Supply, Stage 1

3, 5, 6, 8, 14, 17, 22, 23, 25, 26, 27, 28, 29,

30, 31, 32, 33, 34, 35, 36, 37, 38

GND Ground

4, 18, 21 N.C. No Connection

7 RFin RF Input Signal @ 50 Ohm

9 A1 I2C Address A1 (tri-state, tie to 5 V, tie to ground or leave

floating)

10 A0 I2C Address A0 (tri-state, tie to 5 V, tie to ground or leave

floating)

11 SCLK SPI/I2C Serial Clock Signal (1.8 V JEDEC compatible)

12 SDA SPI/I2C Serial Data Signal (1.8 V JEDEC compatible)

13 CS_B Chip Selection Bar for SPI (1.8 V JEDEC compatible)

15 Tx_EN PA Enable Signal (1.8 V JEDEC compatible)

16 VCC_+5V 5 V VCC Power Source for Autobias Chip

19 VDP1 Peaking Drain Supply, Stage 1

20 VDP2 Peaking Drain Supply, Stage 2

24 RFout RF Output Signal @ 50 Ohm

2 Electrical characteristics

2.1 Ratings

2.1.1 Maximum ratings

Table 2. Maximum ratings

Rating Symbol Value Unit

Operating Voltage Range VCC_+5V 4.75 to 5.25 Vdc

Operating Voltage Range VDD 24 to 30 Vdc

Operating Voltage Range A1, A0 4.75 to 5.25 Vdc

Operating Voltage Range CS_B,

SDA,

SCLK,

Tx_EN

1.65 to 1.95 Vdc

Storage Temperature Range Tstg –65 to +150 °C

Case Operating Temperature TC 125 °C

Peak Input Power

(3500 MHz, Pulsed CW, 10 µsec(on), 10% Duty Cycle)

Pin 25 dBm

Electrical characteristics

A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021

Data Sheet: Technical Data 5/ 33

2.1.2 Lifetime

Table 3. Lifetime

Characteristic Symbol Value Unit

Mean Time to Failure

Case Temperature 125°C, Internal Sense Temperature 108°C, 8 W Avg.,

75% Duty Cycle, 30 Vdc

MTTF >10 Years

2.1.3 ESD protection characteristics

Table 4. Lifetime ESD protection characteristics

Test Methodology Class

Human Body Model (per JS-001-2017) 3A

Charge Device Model (per JS-002-2014) C3

2.1.4 Moisture sensitivity level

Table 5. Moisture sensitivity level

Test Methodology Rating Package Peak Temperature Unit

Per JESD22-A113, IPC/JEDEC J-STD-020 3 260 °C

2.2 Operating characteristics

2.2.1 Nominal DAC settings

Table 6. Nominal DAC settings1

Characteristic Symbol Typ Unit

Gate Quiescent DAC

(VDS = 29 Vdc, A_SENSE_DAC = 30, A_VGS1_DAC = 4)

IDQ1C 25.4 mA

Gate Quiescent DAC

(VDS = 29 Vdc, A_SENSE_DAC = 30, A_VGS2_DAC = 30)

IDQ2C 72.5 mA

Gate Quiescent DAC

(VDS = 29 Vdc, B_SENSE_DAC = 34, B_VGS1_DAC = 57)

IDQ1P0.6 mA

Gate Quiescent DAC

(VDS = 29 Vdc, B_SENSE_DAC = 34, B_VGS2_DAC = 67)

IDQ2P 0.8 mA

1. Each side of device measured separately.

Electrical characteristics

A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021

Data Sheet: Technical Data 6/ 33

2.2.2 Functional tests

Table 7. Functional tests

Characteristic

Symbol

Min

Typ

Max

Unit

Functional Tests — 3400 MHz1(In NXP Doherty Production ATE2Test Fixture, 50 ohm system) VDD = 29 Vdc, Nominal

DAC Settings, Tx_EN = High, Pout = 8 W Avg., 1-tone CW, f = 3400 MHz.

Gain

26.7

29.1

—

Drain Efficiency

29.0

36.9

—

Pout @ 3 dB Compression Point P3dB 46.8 47.9 — dBm

Functional Tests — 3800 MHz1(In NXP Doherty Production ATE2Test Fixture, 50 ohm system) VDD = 29 Vdc, Nominal

DAC Settings, Tx_EN = High, Pout = 8 W Avg., 1-tone CW, f = 3800 MHz.

Gain

26.3

28.2

—

Drain Efficiency ηD 28.0 34.3 — %

Pout @ 3 dB Compression Point P3dB 46.3 47.4 — dBm

2.2.3 Wideband ruggedness

Table 8. Wideband ruggedness

Characteristic

Symbol

Min

Typ

Max

Unit

Wideband Ruggedness

3 (In NXP Doherty Power Amplifier Module Reference Circuit, 50 ohm system) Nominal DAC

Settings, Tx_EN = High, f = 3600 MHz, Additive White Gaussian Noise (AWGN) with 10 dB PAR

ISBW of 400 MHz at 30 Vdc, 3 dB Input Overdrive from 8 W

Avg. Modulated Output Power

No Device Degradation

2.2.4 Typical performance

Table 9. Typical performance

Characteristic

Symbol

Min

Typ

Max

Unit

Typical Performance

3 (In NXP Doherty Power Amplifier Module Reference Circuit, 50 ohm system) VDD = 29Vdc, Nominal

DAC Settings, Tx_EN = High, Pout = 8 W Avg., 3600 MHz

VBW Resonance Point, 2-tone, 1 MHz Tone Spacing

(IMD Third Order Intermodulation Inflection Point)

VBWres — 400 — MHz

1-carrier 20 MHz LTE, 8 dB Input Signal PAR

Gain

—

29.8

—

Power Added Efficiency PAE — 38.3 — %

Adjacent Channel Power Ratio ACPR — –30.9 — dBc

Adjacent Channel Power Ratio ALT1 — –39.4 — dBc

Adjacent Channel Power Ratio

ALT2

—

–49.1

—

dBc

Gain Flatness

—

0.5

—

Fast CW, 27 ms Sweep

Pout @ 3 dB Compression Point P3dB — 47.8 — dBm

AM/PM @ P3dB

—

–18

—

Gain Variation @ Avg. Power over Temperature

(–40

C to +105

ΔG

—

0.036

—

dB/

P3dB Variation over Temperature

(–40°C to +105°C)

P3dB — 0.008 — dB/°C

1. Part input and output matched to 50 ohms.

2. ATE is a socketed test environment.

3. All data measured in fixture with device soldered in NXP reference circuit.

4. Gain flatness = Max(G(fLow to fHigh)) – Min(G(fLow to fHigh))

A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021

Data Sheet: Technical Data 7/ 33

3 Register map and OTP memory

3.1 One-time programmable memory

The A3M36SL039 contains a one-time programmable (OTP) memory array that is used to store register values for the

integrated autobias controller. The data sheet IDQ target values are determined and programmed into the OTP memory during

NXP’s production testing. When programmed, the OTP memory is used to store these values for automatic loading into

autobias registers at power on or reset. These values can be overwritten using the Engineering Mode (EM) sequence;

however, the overwritten values do not persist after a power cycle or a reset.

The OTP memory can be programmed only by NXP during the manufacturing process and cannot be changed by the user.

The values in OTP memory have been selected to allow the device to operate in a wide variety of applications.

3.2 Register map

There are nine 8-bit user accessible registers available in the A3M36SL039. The register mapping is listed in Table 10.

Address 0 RW register is designed to control soft reset, refresh OTP and read the chip version. Address 1−6 registers are RW

and/or OTP controlled and provide settings for the two RF transistor group DACs. Address 15 is read only for temperature

sense functionality. Address 17 is a virtual write only register for enabling Engineering Mode.

A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021

Data Sheet: Technical Data 8/ 33

Table 10. Register map

Address

(in Decimal)

Attribute

Name

Valuebit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0 RW System_Reg N/A Soft

Reset

Refresh

OTP

N/A Chip Version [3:0] (Read

only)

8'b0000_0001

1 OTP

COPY

(RW)

A_Sense_DAC Reserved Group A Sense DAC OTP value

2 OTP

COPY

(RW)

A_VGS1_DAC Group A VGS1DAC OTP value

3 OTP

COPY

(RW)

A_VGS2_DAC Group A VGS2DAC OTP value

4 OTP

COPY

(RW)

B_Sense_DAC Reserved Group B Sense DAC OTP value

5 OTP

COPY

(RW)

B_VGS3_DAC Group B VGS3DAC OTP value

6 OTP

COPY

(RW)

B_VGS4_DAC Group B VGS4DAC OTP value

7–14 — — Reserved —

15 RO Temp_ADC Temperature Sensor [7:0] —

16 — — Reserved —

17 Virtual W

only

EM_Passcode Engineering Mode (EM) passcode 8'hE3 —

Read Only register (RO)

Read Write register (RW)

Read Write register with OTP overwrite at Startup (RW)

Reserved non-accessible register

Write Only register

A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021

Data Sheet: Technical Data 9/ 33

Table 11. Register overview and bit description

Address

Name Bit Bit Descriptions

Power

On/Reset

Value1

Overwritten

by OTP Attribute

Mode

0 System_Reg 7 Not available N/A N/A N/A N/A

6 Soft Reset. A 1 written to this register

will perform a reset of all registers to

their default values. A 0 should be

written after the reset operation is

completed.

0 No RW

5 Refresh OTP. A 1 written to this

in OTP into registers identified in the

"Overwritten by OTP" column. A 0

should be written after the reset

operation is completed.

0 No

4 Not available N/A N/A N/A

0–3 Chip version bits. Inserted by NXP to

provide revision information. Cannot

be changed.

N/A No R

1 A_Sense_DAC 6–7 Not available N/A N/A N/A

0–5 Sense DAC A 6-bit logic value for

carrier amplifiers. DAC A sets the

reference voltage to compare to the

VDS across the reference device.

Minimum typical value is 6'b001000

and maximum value is 6'b111111.

Recommendation is that the value in

this register be set higher than

6'b010000.

6'h20 Yes RW2Yes

2 A_VGS1_DAC 0–7 Sets 8-bit DAC logic value for carrier

amplifier driver stage. 8'h00 sets

gate to equal ceiling voltage. 8'hFF

reduces gate voltage by a max

value.

8'h80

3 A_VGS2_DAC 0–7 Sets 8-bit DAC logic value for carrier

amplifier final stage. 8'h00 sets gate

to equal ceiling voltage. 8'hFF

reduces gate voltage by a max

value.

8'h80

(continued)

Power supply sequence

A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021

Data Sheet: Technical Data 10 / 33

Table 11. Register overview and bit description (continued)

Address

Name Bit Bit Descriptions

Power

On/Reset

Value1

Overwritten

by OTP Attribute

Mode

4 B_Sense_DAC 6–7 Not available N/A N/A N/A No

0–5 Sense DAC B 6-bit logic value for

peaking amplifiers. DAC B sets the

reference voltage to compare to the

VDS across the reference device.

Minimum typical value is 6'b001000

and maximum value is 6'b111111.

Recommendation is that the value in

this register be set higher than

6'b010000.

6'h20 Yes RW2Yes

5 B_VGS3_DAC 0–7 Sets 8-bit DAC logic value for

peaking driver stage. 8'h00 sets gate

to equal ceiling voltage. 8'hFF

reduces gate voltage by a max

value.

8'h80

6 B_VGS4_DAC 0–7 Sets 8-bit DAC logic value for

peaking final stage. 8'h00 sets gate

to equal ceiling voltage. 8'hFF

reduces gate voltage by a max

value.

8'h80

7–14 Reserved N/A Not available N/A N/A N/A No

15 Temp_ADC 0–7 Temperature sensor 8-bit DAC

value. 8'h00 is lowest temperature,

8'hFF is highest temperature.

8'h00 No R No

16 Reserved N/A Not available N/A N/A N/A No

17 EM_Passcode 0–7 Engineering Mode (EM). By writing

8'hE3 to this register the user can

enter engineering mode. EM can be

cleared by writing any other code to

this register. In EM registers

identified in EM mode column can be

changed.

N/A No W Yes

1. At power on or reset, OTP values set by NXP are automatically loaded into registers indicated with a “Yes” in the

“Overwritten by OTP” column. For these registers, values shown in the “Power On/Reset Value column” will be loaded

only if OTP has not been programmed to prevent damage to the device.

2. Register can be read at any time. Can write to register only when in Engineering Mode (EM).

4 Power supply sequence

Power Up Sequence

1. VCC_+5V: 5 V power up

2. SPI/I2C interface is active

3. VDP1,VDP2,VDC1,VDC2 power up

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