NXP Semiconductors Kinetis KE1xZ256 Bedienungsanleitung

Kinetis KE1xZ256 Sub-Family

Reference Manual

Supports: MKE15Z256VLL7, MKE15Z256VLH7; MKE15Z128VLL7,

MKE15Z128VLH7; MKE14Z256VLL7, MKE14Z256VLH7;

MKE14Z128VLL7, MKE14Z128VLH7.

Document Number: KE1xZP100M72SF0RM

Rev. 3, 07/2018

Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018

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Contents

Section number Title Page

Chapter 1

About This Manual

1.1 Audience....................................................................................................................................................................... 43

1.2 Organization..................................................................................................................................................................43

1.3 Module descriptions......................................................................................................................................................43

1.3.1 Example: chip-specific information that supersedes content in the same chapter.........................................44

1.3.2 Example: chip-specific information that refers to a different chapter........................................................... 45

1.4 Register descriptions.....................................................................................................................................................46

1.5 Conventions.................................................................................................................................................................. 47

1.5.1 Numbering systems........................................................................................................................................47

1.5.2 Typographic notation..................................................................................................................................... 47

1.5.3 Special terms..................................................................................................................................................48

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................49

2.2 Block Diagram..............................................................................................................................................................49

2.3 Module Functional Categories......................................................................................................................................50

Chapter 3

Core Overview

3.1 ARM Cortex-M0+ ....................................................................................................................................................... 53

3.2 Core Buses and Interfaces.............................................................................................................................................54

3.3 Core Component Configuration....................................................................................................................................55

3.4 SysTick Clock Configuration....................................................................................................................................... 55

Chapter 4

Interrupts

4.1 Introduction...................................................................................................................................................................57

4.2 NVIC configuration...................................................................................................................................................... 57

4.2.1 Interrupt priority levels.................................................................................................................................. 57

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4.2.2 Non-maskable interrupt..................................................................................................................................58

4.3 Interrupt channel assignments.......................................................................................................................................58

4.3.1 Determining the bitfield and register location for configuring a particular interrupt.................................... 60

Chapter 5

System Integration Module (SIM)

5.1 Introduction...................................................................................................................................................................63

5.1.1 Features.......................................................................................................................................................... 63

5.2 Memory map and register definition.............................................................................................................................63

5.2.1 Chip Control register (SIM_CHIPCTL)........................................................................................................ 64

5.2.2 FTM Option Register 0 (SIM_FTMOPT0)................................................................................................... 66

5.2.3 ADC Options Register (SIM_ADCOPT)...................................................................................................... 67

5.2.4 FTM Option Register 1 (SIM_FTMOPT1)................................................................................................... 69

5.2.5 System Device Identification Register (SIM_SDID).....................................................................................71

5.2.6 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 72

5.2.7 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 74

5.2.8 Unique Identification Register High (SIM_UIDH)....................................................................................... 75

5.2.9 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................75

5.2.10 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 76

5.2.11 Unique Identification Register Low (SIM_UIDL)........................................................................................ 76

5.2.12 Miscellaneous Control register (SIM_MISCTRL)........................................................................................ 77

Chapter 6

Memory-Mapped Divide and Square Root (MMDVSQ)

6.1 Chip-specific Information for this Module...................................................................................................................79

6.2 Introduction...................................................................................................................................................................79

6.2.1 Features.......................................................................................................................................................... 79

6.2.2 Block diagram................................................................................................................................................80

6.2.3 Modes of operation........................................................................................................................................ 82

6.3 External signal description............................................................................................................................................83

6.4 Memory map and register definition.............................................................................................................................83

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6.4.1 Dividend Register (MMDVSQ_DEND)........................................................................................................84

6.4.2 Divisor Register (MMDVSQ_DSOR)...........................................................................................................84

6.4.3 Control/Status Register (MMDVSQ_CSR)...................................................................................................86

6.4.4 Result Register (MMDVSQ_RES)................................................................................................................ 89

6.4.5 Radicand Register (MMDVSQ_RCND)....................................................................................................... 89

6.5 Functional description...................................................................................................................................................90

6.5.1 Algorithms..................................................................................................................................................... 90

6.5.2 Execution times..............................................................................................................................................93

6.5.3 Software interface.......................................................................................................................................... 95

Chapter 7

Miscellaneous Control Module (MCM)

7.1 Chip-specific Information for this Module...................................................................................................................97

7.2 Introduction...................................................................................................................................................................98

7.2.1 Features.......................................................................................................................................................... 98

7.3 Memory map/register descriptions............................................................................................................................... 98

7.3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................99

7.3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 99

7.3.3 Platform Control Register (MCM_PLACR)..................................................................................................100

7.3.4 Compute Operation Control Register (MCM_CPO)..................................................................................... 103

Chapter 8

Bit Manipulation Engine (BME)

8.1 Chip-specific Information for this Module...................................................................................................................105

8.2 Introduction...................................................................................................................................................................105

8.2.1 Overview........................................................................................................................................................106

8.2.2 Features.......................................................................................................................................................... 107

8.2.3 Modes of operation........................................................................................................................................ 107

8.3 Memory map and register definition.............................................................................................................................107

8.4 Functional description...................................................................................................................................................108

8.4.1 BME decorated stores.................................................................................................................................... 108

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8.4.2 BME decorated loads.....................................................................................................................................115

8.4.3 Additional details on decorated addresses and GPIO accesses......................................................................121

8.5 Application information................................................................................................................................................122

Chapter 9

Crossbar Switch Lite (AXBS-Lite)

9.1 Chip-specific Information for this Module...................................................................................................................125

9.2 Introduction...................................................................................................................................................................126

9.2.1 Features.......................................................................................................................................................... 126

9.3 Memory Map / Register Definition...............................................................................................................................127

9.4 Functional Description..................................................................................................................................................127

9.4.1 General operation...........................................................................................................................................127

9.4.2 Arbitration......................................................................................................................................................128

9.5 Initialization/application information........................................................................................................................... 129

Chapter 10

Peripheral Bridge (AIPS-Lite)

10.1 Chip-specific information for this module....................................................................................................................131

10.1.1 Instantiation Information................................................................................................................................131

10.2 Introduction...................................................................................................................................................................132

10.2.1 Features.......................................................................................................................................................... 132

10.2.2 General operation...........................................................................................................................................133

10.3 Memory map/register definition................................................................................................................................... 133

10.4 Functional description...................................................................................................................................................133

10.4.1 Access support............................................................................................................................................... 133

Chapter 11

Trigger MUX Control (TRGMUX)

11.1 Chip-specific information for this module....................................................................................................................135

11.1.1 Module Interconnectivity...............................................................................................................................135

11.2 Introduction...................................................................................................................................................................140

11.2.1 Features.......................................................................................................................................................... 140

11.3 Functional description...................................................................................................................................................140

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11.4 Memory map and register definition.............................................................................................................................140

11.4.1 TRGMUX1 Register Descriptions.................................................................................................................140

11.4.2 TRGMUX0 Register Descriptions.................................................................................................................145

11.5 Usage Guide..................................................................................................................................................................176

11.5.1 ADC Trigger Source...................................................................................................................................... 176

11.5.2 CMP Window/Sample Input .........................................................................................................................177

11.5.3 FTM Fault Detection Input / Hardware Triggers and Synchronization.........................................................177

Chapter 12

Direct Memory Access Multiplexer (DMAMUX)

12.1 Chip-specific information for this module....................................................................................................................179

12.1.1 DMAMUX request sources........................................................................................................................... 179

12.1.2 DMA trigger sources......................................................................................................................................181

12.2 Introduction...................................................................................................................................................................181

12.2.1 Overview........................................................................................................................................................181

12.2.2 Features.......................................................................................................................................................... 182

12.2.3 Modes of operation........................................................................................................................................ 182

12.3 External signal description............................................................................................................................................183

12.4 Memory map/register definition................................................................................................................................... 183

12.4.1 Channel Configuration register (DMAMUX_CHCFGn).............................................................................. 184

12.5 Functional description...................................................................................................................................................185

12.5.1 DMA channels with periodic triggering capability........................................................................................185

12.5.2 DMA channels with no triggering capability.................................................................................................187

12.5.3 Always-enabled DMA sources...................................................................................................................... 187

12.6 Initialization/application information........................................................................................................................... 189

12.6.1 Reset...............................................................................................................................................................189

12.6.2 Enabling and configuring sources..................................................................................................................189

Chapter 13

Enhanced Direct Memory Access (eDMA)

13.1 Introduction...................................................................................................................................................................193

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13.1.1 eDMA system block diagram........................................................................................................................ 193

13.1.2 Block parts..................................................................................................................................................... 194

13.1.3 Features.......................................................................................................................................................... 195

13.2 Modes of operation....................................................................................................................................................... 196

13.3 Memory map/register definition................................................................................................................................... 197

13.3.1 TCD memory................................................................................................................................................. 197

13.3.2 TCD initialization.......................................................................................................................................... 197

13.3.3 TCD structure.................................................................................................................................................197

13.3.4 Reserved memory and bit fields.....................................................................................................................198

13.3.5 Control Register (DMA_CR).........................................................................................................................204

13.3.6 Error Status Register (DMA_ES).................................................................................................................. 207

13.3.7 Enable Request Register (DMA_ERQ)......................................................................................................... 209

13.3.8 Enable Error Interrupt Register (DMA_EEI).................................................................................................211

13.3.9 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................... 212

13.3.10 Set Enable Error Interrupt Register (DMA_SEEI)........................................................................................ 213

13.3.11 Clear Enable Request Register (DMA_CERQ).............................................................................................214

13.3.12 Set Enable Request Register (DMA_SERQ).................................................................................................215

13.3.13 Clear DONE Status Bit Register (DMA_CDNE)..........................................................................................216

13.3.14 Set START Bit Register (DMA_SSRT)........................................................................................................ 217

13.3.15 Clear Error Register (DMA_CERR)..............................................................................................................218

13.3.16 Clear Interrupt Request Register (DMA_CINT)........................................................................................... 219

13.3.17 Interrupt Request Register (DMA_INT)........................................................................................................220

13.3.18 Error Register (DMA_ERR).......................................................................................................................... 221

13.3.19 Hardware Request Status Register (DMA_HRS).......................................................................................... 223

13.3.20 Enable Asynchronous Request in Stop Register (DMA_EARS)...................................................................225

13.3.21 Channel n Priority Register (DMA_DCHPRIn)............................................................................................ 226

13.3.22 TCD Source Address (DMA_TCDn_SADDR).............................................................................................227

13.3.23 TCD Signed Source Address Offset (DMA_TCDn_SOFF)..........................................................................227

13.3.24 TCD Transfer Attributes (DMA_TCDn_ATTR)...........................................................................................228

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13.3.25 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................... 229

13.3.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)

(DMA_TCDn_NBYTES_MLOFFNO).........................................................................................................229

13.3.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)

(DMA_TCDn_NBYTES_MLOFFYES)....................................................................................................... 231

13.3.28 TCD Last Source Address Adjustment (DMA_TCDn_SLAST)...................................................................232

13.3.29 TCD Destination Address (DMA_TCDn_DADDR).....................................................................................232

13.3.30 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)..................................................................233

13.3.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_CITER_ELINKYES).............................................................................................................233

13.3.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_CITER_ELINKNO).............................................................................................................. 235

13.3.33 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)............ 236

13.3.34 TCD Control and Status (DMA_TCDn_CSR).............................................................................................. 236

13.3.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_BITER_ELINKYES).............................................................................................................239

13.3.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_BITER_ELINKNO).............................................................................................................. 240

13.4 Functional description...................................................................................................................................................241

13.4.1 eDMA basic data flow................................................................................................................................... 241

13.4.2 Fault reporting and handling..........................................................................................................................244

13.4.3 Channel preemption....................................................................................................................................... 246

13.4.4 Performance................................................................................................................................................... 246

13.5 Initialization/application information........................................................................................................................... 251

13.5.1 eDMA initialization....................................................................................................................................... 251

13.5.2 Programming errors....................................................................................................................................... 253

13.5.3 Arbitration mode considerations....................................................................................................................253

13.5.4 Performing DMA transfers............................................................................................................................ 254

13.5.5 Monitoring transfer descriptor status............................................................................................................. 258

13.5.6 Channel Linking.............................................................................................................................................260

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13.5.7 Dynamic programming.................................................................................................................................. 261

13.5.8 Suspend/resume a DMA channel with active hardware service requests......................................................264

13.6 Usage Guide..................................................................................................................................................................266

Chapter 14

Memory and memory map

14.1 Introduction...................................................................................................................................................................267

14.2 Flash memory............................................................................................................................................................... 269

14.2.1 Flash memory types....................................................................................................................................... 269

14.2.2 Flash Memory Sizes.......................................................................................................................................269

14.3 SRAM memory.............................................................................................................................................................270

14.3.1 SRAM sizes....................................................................................................................................................270

14.3.2 SRAM retention in low power modes............................................................................................................270

14.4 System memory map.....................................................................................................................................................270

14.4.1 Aliased bit-band regions................................................................................................................................ 272

14.4.2 Bit Manipulation Engine................................................................................................................................273

14.5 Peripheral memory map................................................................................................................................................273

14.5.1 Peripheral Bridge (AIPS-Lite) Memory Map................................................................................................ 274

14.6 Private Peripheral Bus (PPB) memory map..................................................................................................................277

Chapter 15

Flash Acceleration Unit (FAU)

15.1 Flash Acceleration Unit (FAU).....................................................................................................................................279

15.1.1 Introduction....................................................................................................................................................279

15.1.2 Modes of operation........................................................................................................................................ 279

15.1.3 External signal description.............................................................................................................................279

15.1.4 Memory map and register descriptions..........................................................................................................279

15.1.5 Functional description....................................................................................................................................280

15.2 Usage Guide..................................................................................................................................................................280

15.2.1 FAU Features................................................................................................................................................. 281

15.2.2 FAU Configuration........................................................................................................................................ 281

Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018

10 NXP Semiconductors

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