NXP Semiconductors MPC5777C Bedienungsanleitung

MPC5777C Clock Calculator Guide

How to use MPC5777C tool to easily calculate device

frequency domains

by: NXP Semiconductors

1.Introduction

NXP’s MPC5777C is a dual-core 32-bit microcontroller

dedicated to high-performance powertrain applications.

The MCU supports ASIL-D automotive safety rating

and runs on two e200z7 Power Architecture cores. The

MPC5777C features two versions, a standard version

whose core runs up to 264 MHz and a performance

version that supports up to 300 MHz. This application

note will refer to these versions as

“MPC5777C_264MHz” and “MPC5777C_300MHz”,

respectively, for version-specific information; general

content that applies to both versions will refer to the

device as simply “MPC5777C”.

The MPC5777C supports an 8-44 MHz external

oscillator (XOSC), a 16 MHz internal RC oscillator

(IRC), and two phase locked loops (PLL).

MPC5777C_264MHz’s two PLLs support 200 MHz

and 264 MHz, respectively; MPC5777C_300MHz’s

respective PLLs can run up to 240 MHz and 300 MHz.

The IRC is selected out of reset so increasing the

operating frequency from 16 MHz requires additional

configuration. The MPC5777C Clock Calculator is

meant to complement the reference manual. It seeks to

simplify the clock configuration process by providing a

graphical, interactive tool to help the user find the

NXP Semiconductors

Document Number: AN12176

Application Notes

Rev. 1

12/2018

Contents

1. Introduction........................................................................1

2. Clock calculator design...................................................... 2

2.1. Tree......................................................................... 4

2.2. Device Select .......................................................... 7

2.3. Oscillator control .................................................... 8

2.4. Peripheral domains ................................................. 8

2.5. FlexCAN clocking and MCAN clocking................ 9

2.6. LFAST clocking ................................................... 10

2.7. PLLx..................................................................... 12

2.8. Reference tables (pll0_phi, pll0_phi1, and pll1_phi)12

2.9. Summary............................................................... 13

2.10. Limits.................................................................... 16

3. Clock tool example use case: Configure eMIOS to 60 MHz

PLL1 with MPC5777C_264MHz .................................... 17

3.1. Select the Device .................................................. 18

3.2. Configure PER_CLK............................................ 19

3.3. Observe the registers............................................. 29

3.4. Copy the code ....................................................... 30

4. Conclusion....................................................................... 30

5. Revision History .............................................................. 30

Clock calculator design

MPC5777C Clock Calculator Guide, Rev. 1, 12/2018

2NXP Semiconductors

correct register settings in order to achieve the desired clock frequencies.

Accompanying this application note is the clock calculator itself. You can download it from

MPC5777C clock calculator.

The clock calculator makes use of macros to perform functions like resetting the spreadsheet to initial

values, configuring all clock frequencies to the fastest allowable settings, and copying generated code.

Macros must be enabled in the user’s MS Excel settings to access these features. If macros are turned

off, however, the tool will still be able to calculate clock frequencies, but the aforementioned features

will be disabled. To turn on macros in MS Excel 2016, go to the Developer tab on the top toolbar and

click on Macro Security. A popup window will appear. In it, select Enable all macros.

Figure 1. Enable macros

2.Clock calculator design

The MPC5777C clock calculator takes the form of an interactive Microsoft Excel spreadsheet organized

into multiple tabs as shown in the following figure.

Figure 2. MPC5777C Clock calculator setup

Clock sources (e.g. oscillators and PLLs) propagate to the various clock domains from which the MCU

modules take their clocks. Most cells representing clock domain frequencies are not to be modified

manually. The user is meant to enter frequencies to the few select clock sources and all clock domain

frequencies derive from these sources. Several clock domain inputs are meant to be modified manually

as they represent external clocks that are driven into a pin. There are also input cells that set muxes and

clock dividers. All cells that take entries have blue borders instead of black, as shown in the figure

below.

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MPC5777C Clock Calculator Guide, Rev. 1, 12/2018

NXP Semiconductors 3

Figure 3. Input cells vs. Output cells

There are limits to what frequencies can be entered to the input frequency cells. Values that are out of

range will be rejected and the user will receive an error message. Invalid clock domain frequencies that

arise from valid input values and legal, but improper, dividers will be shaded in red, as will be explained

in greater depth later in this application note.

Frequency values are linked across tabs, so PER_CLK in the Tree tab will always be the same as

PER_CLK in the Peripheral Domains tab. Hyperlinks are provided to duplicate domain names to link

back to their points of origin. For example, PER_CLK originates in Tree. So clicking the PER_CLK

textbox in Peripheral Domains will take the user to PER_CLK in Tree. Textboxes that are links, when

hovered over, will cause the mouse cursor to turn into a hand icon and a pop-up to appear, showing the

destination address, as shown in the following figure.

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4NXP Semiconductors

Figure 4. Clicking on a link

The following subsections will explain in depth the purpose of each tab.

2.1. Tree

Tree is the centerpiece of the tool. This tab is the starting point for all clock frequency calculations. It is

organized to resemble the MPC5777C clock tree as presented in the following figure.

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NXP Semiconductors 5

Figure 5. MPC5777C Reference manual clock Tree

Figure 6 shows, in part, the diagram’s clock tool counterpart. The difference between the two is that the

latter is interactive.

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6NXP Semiconductors

Figure 6. Clock calculator Tree

The flow of the diagram generally goes from left to right. On the left are the MPC5777C clock sources

and on the right are the clock domains. MCU modules run on one or more of these clock domains.

Clock domain frequency values are displayed in the outlined cells next to their labels. Most cells are not

meant to be written to; their values are dependent on the frequencies of preceding steps in the clock tree.

Take FM_PER_CLK, for example: its value is sourced from either the system clock, which in turn

comes from either the IRC, XOSC, PLL0_PHI, or PLL1_PHI. Now look at the XOSC block. XOSC

depends on the settings from the Oscillator Control tab. So all clock domains ultimately derive from a

few select inputs. The IRC is always on at 16 MHz, PLL0_PHI and PLL1_PHI are configured in the

PLL0 and PLL1 tab, respectively. The system clock selects from these four clock sources by selecting

the value of the System Clock Selector block. Then finally the selected signal is divided by the

FM_PER_CLK prescaler value. It is important to note, though, that the user input for the divider field is

not the desired divider, but the bitfield value that one would have to enter to achieve the desired divider.

Some divider blocks like FM_PER_CLK’s, provide a dropdown list with textbox description

underneath. Others support too many input values to be put into a list. The user must provide the proper

bitfield value, not the desired divisor. That is why such blocks are labelled something like

“/(1+(0…63))” rather than simply “/1…64”. The user provides a value between 0 and 63, to which the

hardware automatically adds 1 to calculate a divider that is between 1 and 64.

Tree also features two buttons, Reset and Max. They only function when macros are enabled. Clicking

on these buttons with macros disabled will return an error. If macros are enabled, the Reset button will

set all blocks to their reset value, as described in the reference manual. The Max button sets all blocks in

this tool to values that configure the system and auxiliary clock domains to their respective maximum

allowable frequencies. Below is a screenshot of the buttons.

Clock calculator design

MPC5777C Clock Calculator Guide, Rev. 1, 12/2018

NXP Semiconductors 7

Figure 7. Buttons

2.2. Device select

The Device Select tab allows user to choose between MPC5777C_264MHz and MPC5777C_300MHz.

This changes the hardware specification table used by the MPC5777C Clock Calculator. For example,

if MPC5777C_300MHz is selected, PLL1_PHI will shade red starting at 300 MHz rather than 264 MHz.

The structure of the tool remains unchanged, though, since the two MPC5777C versions share the same

architecture, but with different operating speeds.

Figure 8. Device select

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8NXP Semiconductors

2.3. Oscillator control

Oscillator Control controls the generation of the external oscillator (XOSC) frequency. MPC5777C

supports two ways of XOSC generation. The chip has two external oscillator pins, XTAL and EXTAL.

An 8-44 MHz external oscillator can be connected to both pins. This external oscillator is also referred

to simply as XTAL. If the XOSC Enable/Select block selects XTAL, XOSC will derive its frequency from

the external oscillator (XTAL) block. Alternatively, a waveform can be driven directly to the EXTAL

pin, also known as bypass mode. This signal is also referred to simply as EXTAL. When the XOSC

Enable/Select block selects EXTAL, XOSC will derive its frequency from the EXTAL pin. Shown below

is a screenshot of oscillator control.

Figure 9. Oscillator control

2.4. Peripheral domains

Peripheral Domains is an in-depth diagram of MPC5777C modules. Where Tree leaves off at the clock

domain level, Peripheral Domains picks up and progresses to the module level, as shown in the figure

below.

Clock calculator design

MPC5777C Clock Calculator Guide, Rev. 1, 12/2018

NXP Semiconductors 9

Figure 10.Peripheral domains

The clock domains are color-coded. Black lines are reserved for clock domains that only a few modules

use. For example, many modules’ BIU clocks are filtered through a Halt block. The output of each Halt

block is colored black, since each only goes to at most a few modules. As a rule of thumb, clock

domains are represented with black lines if all modules using it can fit within a single window without

having to scroll. The frequencies on this tab are not meant to be modified and are dependent on

frequency values in the Tree tab.

2.5. FlexCAN clocking and MCAN clocking

Some modules have so many clock configuration possibilities that they warrant their own dedicated

sections, lest Peripheral Domains becomes too complicated. FlexCAN and MCAN uses their protocol

clocks to generate can message time segments. Domains still hosts FlexCAN and MCAN blocks that

show their input clocks and are hyperlinked to FlexCAN Clocking and MCAN Clocking, respectively,

as shown in the below figure.

Clock calculator design

MPC5777C Clock Calculator Guide, Rev. 1, 12/2018

10 NXP Semiconductors

Figure 11.FlexCAN in Peripheral domains

FlexCAN clocking and MCAN clocking provides options to configure the bit time segments, as shown in

the figure below. The column on the right-hand side of the diagram shows the breakdown, in

nanoseconds, of a CAN bit time, as configured by the FlexCAN or MCAN.

Figure 12.FlexCAN clocking

2.6. LFAST clocking

The LFAST is the third module that has its own tab. It is a versatile, but intricate module that hosts its

own PLL which generates multiple phases and generates a signal within specification only if its inputs

are certain frequencies. These intricacies make it necessary to give LFAST its own dedicated tab.

LFAST clocking presents a block diagram of the module with various clocks going into it. It also

supports LFAST_PLL configuration to increase the LFAST frequency up to 480 MHz. The LFAST also

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