Philips TDA8002C Bedienungsanleitung

DATA SHEET

Product speciﬁcation

Supersedes data of 1999 Feb 24

File under Integrated Circuits, IC02

1999 Oct 12

INTEGRATED CIRCUITS

TDA8002C

IC card interface

1999 Oct 12 2

Philips Semiconductors Product speciﬁcation

IC card interface TDA8002C

FEATURES

•Single supply voltage interface (3.3 or 5 V environment)

•Low-power sleep mode

•Three specific protected half-duplex bidirectional

buffered I/O lines

•VCC regulation 5 V ±5% or 3 V ±5%, ICC <55mAfor

DD = 3.0 to 6.5 V, with controlled rise and fall times

•Thermal and short-circuit protections with current

limitations

•Automatic ISO 7816 activation and deactivation

sequences

•Enhanced ESD protections on card side (>6 kV)

•Clock generation for the card up to 12 MHz with

synchronous frequency changes

•Clock generation up to 20 MHz (external clock)

•Synchronous and asynchronous cards (memory and

smart cards)

•ISO 7816, GSM11.11 compatibility and EMV

(Europay, MasterCardand Visa) compliant

•Step-up converter for VCC generation

•Supplysupervisorforspikeseliminationand emergency

deactivation

•Chip select input for easy use of several TDA8002Cs in

parallel.

APPLICATIONS

IC card readers for:

•GSM applications

•Banking

•Electronic payment

•Identification

•Pay TV

•Road tolling.

GENERAL DESCRIPTION

The TDA8002C is a complete low-power analog interface

forasynchronousandsynchronouscards.Itcanbeplaced

between the card and the microcontroller. It performs all

supply, protection and control functions. It is directly

compatible with ISO 7816, GSM11.11 and EMV

specifications.

ORDERING INFORMATION

TYPE NUMBER PACKAGE

MARKING NAME DESCRIPTION VERSION

TDA8002CT/A/C1 TDA8002CT/A SO28 plastic small outline package; 28 leads; body width

7.5 mm SOT136-1

TDA8002CT/B/C1 TDA8002CT/B

TDA8002CT/C/C1 TDA8002CT/C

TDA8002CG/C1 TDA8002C LQFP32 plastic low proﬁle quad ﬂat package; 32 leads;

body 5 ×5×1.4 mm SOT401-1

1999 Oct 12 3

Philips Semiconductors Product speciﬁcation

IC card interface TDA8002C

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDD supply voltage 3.0 −6.5 V

IDD(lp) supply current low-power −−150 µA

IDD(idle) supply current Idle mode; fCLKOUT = 10 MHz −−5mA

DD(active) supply current active mode; VCC(O) =5V;

CLKOUT =10MHz

CLK = LOW; ICC = 100 µA−−8mA

CLK = 5 MHz; ICC =10mA −−50 mA

fCLK = 5 MHz; ICC =55mA −−140 mA

active mode; VCC(O) =3V;

CLKOUT =10MHz

CLK = LOW; ICC = 100 µA−−8mA

CLK = 5 MHz; ICC =10mA −−50 mA

fCLK = 5 MHz; ICC =55mA −−140 mA

Card supply

VCC(O) output voltage active mode for VCC =5V

CC < 55 mA; DC load 4.6 −5.4 V

ICC = 40 nAs; AC load 4.6 −5.4 V

active mode for VCC =3V

CC < 55 mA; DC load 2.76 −3.24 V

ICC = 40 nAs; AC load 2.76 −3.24 V

General

fCLK card clock frequency 0 −12 MHz

tde deactivation sequence duration 60 80 100 µs

Ptot continuous total power dissipation

TDA8002CT/x Tamb =−25 to +85 °C−−0.56 W

TDA8002CG Tamb =−25 to +85 °C−−0.46 W

Tamb ambient temperature −25 −+85 °C

1999 Oct 12 4

Philips Semiconductors Product speciﬁcation

IC card interface TDA8002C

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

FCE246

100 nF 100 nF 470 nF

470 nF

100

nF 100

I/O

TRANSCEIVER

I/O

TRANSCEIVER

I/O

TRANSCEIVER

THERMAL

PROTECTION

VCC

GENERATOR

RST

BUFFER

CLOCK

BUFFER

SEQUENCER

CLOCK

CIRCUITRY

LATCH

OSCILLATOR

INTERNAL OSCILLATOR

2.5 MHz

STEP-UP CONVERTER

INTERNAL

REFERENCE

VOLTAGE SENSE

SUPPLY

EN2

PVCC

EN5

EN4

EN3

CLK

EN1 CLKUP

ALARM

Vref

VDDD

VDDA

14 12

S1 S2

VUP

AGND

23 VCC

22 RST

18 PRES

21 CLK

AUX1

AUX2

I/O

10 29

DGND1 DGND2

I/OUC

AUX2UC

AUX1UC

XTAL2

XTAL1

CLKOUT

STROBE

CLKSEL

CLKDIV2

CLKDIV1

MODE

CMDVCC

RSTIN

OFF

CV/TV

ALARM

TDA8002CG

1999 Oct 12 5

Philips Semiconductors Product speciﬁcation

IC card interface TDA8002C

PINNING

SYMBOL PIN I/O DESCRIPTION

TYPE

CT/A TYPE

CT/B TYPE

CT/C TYPE

XTAL1 1 1 1 30 I crystal connection or input for external clock

XTAL2 2 2 2 31 O crystal connection

I/OUC 3 3 3 32 I/O data I/O line to and from microcontroller

AUX1UC 4441I/Oauxiliary line 1 to and from microcontroller for synchronous

applications

AUX2UC 5 −−2 I/O auxiliary line 2 to and from microcontroller for synchronous

applications

CS −5 5 3 I chip select control input for enabling pins I/OUC, AUX1UC,

AUX2UC, CLKSEL, CLKDIV1, CLKDIV2, STROBE, CV/TV,

CMDVCC, RSTIN, OFF and MODE; note 1

ALARM 6664Oopen drain PMOS reset output for microcontroller (active

HIGH)

CLKSEL 7775Icontrol input signal for CLK (LOW = XTAL oscillator;

HIGH = STROBE input)

CLKDIV1 8886Icontrol input with CLKDIV2 for choosing CLK frequency

CLKDIV2 9997Icontrol input with CLKDIV1 for choosing CLK frequency

STROBE 10 10 10 8 I external clock input for synchronous applications

CLKOUT 11 11 11 9 O clock output (see Table 1)

DGND1 12 12 12 10 supply digital ground 1

AGND 13 13 13 11 supply analog ground

S2 14 14 14 12 I/O capacitance connection for voltage doubler

VDDA 15 15 15 13 supply analog supply voltage

S1 16 16 16 14 I/O capacitance connection for voltage doubler

VUP 17 17 17 15 I/O output of voltage doubler

I/O 18 18 18 16 I/O data I/O line to and from card

AUX2 19 −−17 I/O auxiliary I/O line to and from card

PRES 20 19 19 18 I card input presence contact (active LOW)

PRES −20 −−I active HIGH card input presence contact

CV/TV −−20 19 I card voltage selection input line (high = 5 V, low = 3 V); note 1

AUX1 21 21 21 20 I/O auxiliary I/O line to and from card

CLK 22 22 22 21 O clock to card output (C3I) (see Table 1)

RST 23 23 23 22 O card reset output (C2I)

VCC 24 24 24 23 O supply for card (C1I)

CMDVCC 25 25 25 24 I start activation sequence input from microcontroller (active

LOW)

RSTIN 26 26 26 25 I card reset input from microcontroller

OFF 27 27 27 26 O open-drain NMOS interrupt output to microcontroller (active

LOW)

1999 Oct 12 6

Philips Semiconductors Product speciﬁcation

IC card interface TDA8002C

Note

1. A pull-up resistor of 100 kΩconnected to VDD is integrated.

MODE 28 28 28 27 I operating mode selection input (HIGH = normal; LOW = sleep)

VDDD −−−28 supply digital supply voltage

DGND2 −−−29 supply digital ground 2

SYMBOL PIN I/O DESCRIPTION

TYPE

CT/A TYPE

CT/B TYPE

CT/C TYPE

Fig.2 Pin configuration (TDA8002CT/A).

handbook, halfpage

XTAL1

XTAL2

I/OUC

AUX1UC

AUX2UC

ALARM

CLKSEL

CLKDIV1

CLKDIV2

STROBE

CLKOUT

DGND1

AGND

MODE

RSTIN

RST

CLK

VCC

AUX1

AUX2

I/O

VUP

VDDA

1514

TDA8002CT/A

FCE247

OFF

CMDVCC

PRES

Fig.3 Pin configuration (TDA8002CT/B).

handbook, halfpage

XTAL1

XTAL2

I/OUC

AUX1UC

ALARM

CLKSEL

CLKDIV1

CLKDIV2

STROBE

CLKOUT

DGND1

AGND

MODE

RSTIN

RST

CLK

VCC

AUX1

I/O

VUP

VDDA

1514

TDA8002CT/B

FCE248

OFF

CMDVCC

PRES

1999 Oct 12 7

Philips Semiconductors Product speciﬁcation

IC card interface TDA8002C

Fig.4 Pin configuration (TDA8002CT/C).

handbook, halfpage

XTAL1

XTAL2

I/OUC

AUX1UC

ALARM

CLKSEL

CLKDIV1

CLKDIV2

STROBE

CLKOUT

DGND1

AGND

MODE

RSTIN

RST

CLK

VCC

AUX1

I/O

VUP

VDDA

1514

TDA8002CT/C

FCE249

OFF

CMDVCC

CV/TV

PRES

Fig.4 Pin configuration (TDA8002CT/C).

Fig.5 Pin configuration (TDA8002CG).

handbook, full pagewidth

TDA8002CG

FCE250

AUX1UC

STROBE

CLKOUT

VDDD

I/OUC

DGND2

AUX2

XTAL2

XTAL1

I/O

AUX2UC

ALARM

CLKSEL

CLKDIV1

CLKDIV2

DGND1

AGND

VUP

VDDA

RST

CLK

VCC

AUX1

CMDVCC

CV/TV

PRES

MODE

RSTIN

OFF

1999 Oct 12 8

Philips Semiconductors Product speciﬁcation

IC card interface TDA8002C

FUNCTIONAL DESCRIPTION

Power supply

The supply pins for the chip are VDDA, VDDD, AGND,

DGND1 and DGND2. VDDA and VDDD (i.e. VDD) should be

in the range of 3.0 to 6.5 V. All card contacts remain

inactive during power-up or power-down.

On power-up, the logic is reset by an internal signal.

The sequencer is not activated until VDD reaches

Vth2 +V

hys2 (see Fig.6). When VDD falls below Vth2, an

automatic deactivation sequence of the contacts is

performed.

Chip selection

The chip select pin (CS) allows the use of several

TDA8002Cs in parallel.

When CS is HIGH, the pins RSTN, CMDVCC, MODE,

CV/TV, CLKDIV1, CLKDIV2, CLKSEL and STROBE

control the chip, pins I/OUC, AUX1UC and AUX2UC are

the copy of I/O, AUX1 and AUX2 when enabled (with

integrated 20 kΩpull-up resistors connected to VDD) and

OFF is enabled.

When CS goes LOW, the levels on pins RSTIN,

CMDVCC, MODE, CV/TV, CLKDIV1, CLKDIV2 and

STROBE are internally latched, I/OUC, AUX1UC and

AUX2UC go to high-impedance with respect to I/O, AUX1

and AUX2 (with integrated 100 kΩpull-up resistors

connected to VDD) and OFF is high-impedance.

Supply voltage supervisor (VDD)

This block surveys the VDD supply. A defined retriggerable

pulse of 10 ms minimum (tW) is delivered on the ALARM

output during power-up or power-down of VDD (see Fig.6).

This signal is also used for eliminating the spikes on card

contacts during power-up or power-down.

When VDD reaches Vth2 +V

hys2, an internal delay (tW) is

started. The ALARM output is active until this delay has

expired. When VDD falls below Vth2, ALARM is activated

and a deactivation sequence of the contacts is performed.

Clock circuitry

The TDA8002C supports both synchronous and

asynchronouscards. There are three methods toclock the

circuitry:

•Apply a clock signal to pin STROBE

•Use of an internal RC oscillator

•Use of a quartz oscillator which should be connected

between pins XTAL1 and XTAL2 or an external clock

applied on XTAL1.

When CLKSEL is HIGH, the clock should be applied to the

STROBE pin. When CLKSEL is LOW, the internal

oscillators is used.

When an internal clock is used, the clock output is

availableon pin CLKOUT. The RC oscillator isselected by

making CLKDIV1 HIGH and CLKDIV2 LOW. The clock

output to the card is available on pin CLK. The frequency

of the card clock can be the input frequency divided by

2 or 4, STOP low or 1.25 MHz, depending on the states of

CLKDIV1 or CLKDIV2 (see Table 1).

When STROBE is used for entering the clock to a

synchronous card, STROBE should remain stable during

activation sequence otherwise the first pulse may be

omitted.

Do not change CLKSEL during activation. When in

low-power (sleep) mode, the internal oscillator frequency

which is available on pin CLKOUT is lowered to

approximately 16 kHz for power economy purposes.

1999 Oct 12 9

Philips Semiconductors Product speciﬁcation

IC card interface TDA8002C

Fig.6 ALARM as a function of VDD (tWpulse width minimum of 10 ms).

handbook, full pagewidth

FCE272

VDD

tWtW

Vth2 + Vhys2

Vth2

ALARM

Fig.7 Chip select.

handbook, full pagewidth

tDZ

tSL

INPUTS

FCE245

tSI

tIS tDI

tID

OFF, I/OUC

AUX1UC, AUX2UC

1999 Oct 12 10

Philips Semiconductors Product speciﬁcation

IC card interface TDA8002C

Table 1 Clock circuitry deﬁnition

Notes

1. X = don’t care.

2. In low-power mode.

3. fint = 32 kHz in low-power mode.

MODE CLKSEL CLKDIV1 CLKDIV2 FREQUENCYOF

CLK FREQUENCYOF

CLKOUT

HIGH LOW HIGH LOW 1⁄2fint 1⁄2fint

HIGH LOW LOW LOW 1⁄4fxtal fxtal

HIGH LOW LOW HIGH 1⁄2fxtal fxtal

HIGH LOW HIGH HIGH STOP low fxtal

HIGH HIGH X(1) X(1) STROBE fxtal

LOW(2) X(1) X(1) X(1) STOP low 1⁄2fint(3)

I/O circuitry

The three I/O transceivers are identical. The state is HIGH

forallI/O pins(i.e.I/O,I/OUC,AUX1,AUX1UC,AUX2and

AUX2UC). Pin I/O is referenced to VCC and pin I/OUC to

VDD, thus ensuring proper operation in the event that

VCC ≠VDD.

The first side on which a falling edge is detected becomes

a master (input). An anti-latch circuitry first disables the

detection of the falling edge on the other side, which

becomes slave (output), see Fig.8.

After a delay time td(between 50 and 400 ns), the logic 0

present on the master side is transferred on the slave side.

When the input is back to HIGH level, a current booster is

turned on during the delay tdon the output side and then

both sides are back to their idle state, ready to detect the

next logic 0 on any side.

In the event of a conflict, both lines may remain LOW until

the software enables the lines to be HIGH. The anti-latch

circuitry ensures that the lines do not remain LOW if both

sides return HIGH, regardless of the prior conditions.

The maximum frequency on the lines is approximately

200 kHz.

When CS is HIGH, I/OUC, AUX1UC and AUX2UC are

internally pulled-up to VDD with 20 kΩresistors. When

CS is LOW, I/OUC, AUX1UC and AUX2UC are

permanently HIGH (with integrated 100 kΩpull-up

resistors connected to VDD).

Fig.8 Master and slave signals.

handbook, full pagewidth

MGD703

I/O

I/OUC

conflict idle

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