Philips Triple high-speed Analog-to-Digital Converter 110 Msps... Bedienungsanleitung

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Rev. 03 — 21 July 2000 Product speciﬁcation

1. General description

The TDA8752B is a triple 8-bit ADC with controllable ampliﬁers and clamps for the

digitizing of large bandwidth RGB signals.

The clamp level, the gain and all other settings are controlled via a serial interface

(either I2C-bus or 3-wire serial bus, selected via a logic input).

The IC also includes a PLL that can be locked to the horizontal line frequency and

generates the ADC clock. The PLL jitter is minimized for high resolution PC graphics

applications. An external clock can also be input to the ADC.

It is possible to set the TDA8752B serial bus address to four different values, when

several TDA8752B ICs are used in a system, by means of the I2C-bus interface (for

example, two ICs used in an odd/even conﬁguration).

2. Features

■Triple 8-bit ADC

■Sampling rate up to 110 Msps

■IC controllable via a serial interface, which can be either I2C-bus or 3-wire serial

bus, selected via a TTL input pin

■IC analog voltage input from 0.4 to 1.2 V (p-p) to produce a full-scale ADC input of

1 V (p-p)

■Three clamps for programming a clamping code between −63.5 and +64 in steps

of 1⁄2LSB for RGB signals, and from +120 to +136 in steps of 1⁄2LSB for YUV

signals

■Three controllable ampliﬁers: gain controlled via the serial interface to produce a

full-scale resolution of 1⁄2LSB peak-to-peak

■Ampliﬁer bandwidth of 250 MHz

■Low gain variation with temperature

■PLL controllable via the serial interface to generate the ADC clock which can be

locked to a line frequency of 15 to 280 kHz

■Integrated PLL divider

■Programmable phase clock adjustment cells

■Internal voltage regulators

■TTL compatible digital inputs and outputs

■Chip enable high-impedance ADC output

Philips Semiconductors TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product speciﬁcation Rev. 03 — 21 July 2000 2 of 38

■Power-down mode

■Possibility to use up to four ICs in the same system when using the I2C-bus

interface, or more when using the 3-wire serial bus interface

■1.1 W power dissipation.

3. Applications

■RGB high-speed digitizing

■LCD panels drive

■LCD projection systems

■VGA and higher resolutions

■Using two ICs in parallel, a higher display resolution can be obtained: 200 MHz

pixel frequency.

4. Quick reference data

Table 1: Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

VCCA analog supply voltage for R, G and B channels 4.75 5.0 5.25 V

VDDD logic supply voltage for I2C-bus and 3-wire

serial bus 4.75 5.0 5.25 V

VCCD digital supply voltage 4.75 5.0 5.25 V

VCCO output stages supply voltage for R, G and B channels 4.75 5.0 5.25 V

VCCA(PLL) analog PLL supply voltage 4.75 5.0 5.25 V

VCCO(PLL) output PLL supply voltage 4.75 5.0 5.25 V

ICCA analog supply current −120 −mA

IDDD logic supply current for I2C-bus and 3-wire −1.0 −mA

ICCD digital supply current −40 −mA

ICCO output stages supply current fclk = 110 MHz; ramp input −26 −mA

ICCA(PLL) analog PLL supply current −28 −mA

ICCO(PLL) output PLL supply current −5−mA

fclk clock frequency −−110 MHz

fref(PLL) PLL reference clock

frequency 15 −280 kHz

fVCO VCO output clock frequency 12 −110 MHz

INL DC integral non-linearity from analog input to digital

output; full-scale; ramp

input; fclk = 110 MHz

−±0.5 ±1.5 LSB

DNL DC differential non-linearity from analog input to digital

output; full-scale; ramp

input; fclk = 110 MHz

−±0.5 ±1.0 LSB

∆Gamp/∆T ampliﬁer gain stability as a

function of temperature Vref = 2.5 V with

100 ppm/°C maximum −−200 ppm/°C

B ampliﬁer bandwidth −3 dB; Tamb =25°C 250 −−MHz

tset settling time of the ADC block

plus AGC input signal settling

time <1 ns; Tamb =25°C−−6ns

Philips Semiconductors TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product speciﬁcation Rev. 03 — 21 July 2000 3 of 38

5. Ordering information

DRPLL PLL divider ratio 100 −4095

Ptot total power dissipation fclk = 110 MHz; ramp input −1.1 −W

jPLL(rms) maximum PLL phase jitter

(RMS value) fref = 66.67 kHz;

fclk = 110 MHz −112 −ps

Table 1: Quick reference data

…continued

Symbol Parameter Conditions Min Typ Max Unit

Table 2: Ordering information

Type number Package Sampling

frequency (MHz)

Name Description Version

TDA8752BH/8 QFP100 plastic quad ﬂat package; 100 leads (lead length

1.95 mm); body 14 ×20 ×2.8 mm SOT317-2 110

Philips Semiconductors TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product speciﬁcation Rev. 03 — 21 July 2000 4 of 38

6. Block diagram

Fig 1. Block diagram.

FCE467

SERIAL

INTERFACE

C-BUS

3-WIRE

C/3W

C-bus; 1-bit

(Hlevel)

REGULATOR

PLL

PWDWN CP CZ

CKREF

COAST

INV

CKEXT

CKREFO

CKAO

CKBO

CKADCO

B0 to B7

BOR

R0 to R7

G0 to G7

BBOT

BCLP

RBOT

RCLP

GBOT

GCLP

DEC2DEC1HSYNCn.c.

HSYNCI

ADD2

BIN

BGAINC

BAGC

GAGC

Vref

RDEC

RIN

RGAINC

RAGC

GDEC

GIN

GGAINC

BDEC

ADD1

SEN

SCL

SDA

DIS

BLUE CHANNEL

GREEN CHANNEL

TDA8752B

RED CHANNEL

ADC

GOR

ROR

MUX

CLAMP

OUTPUTS

VCCA(R)

VCCA(G)

VCCA(B)

VDDD

AGNDG

VCCO(G)

VCCO(B)

VCCO(R)

VCCD

VCCA(PLL)

VCCO(PLL)

CLP

AGNDR

VSSD

AGNDB

OGNDG

OGNDR

AGNDPLL

OGNDB

DGND

OGNDPLL

TDO

TCK 35

1, 5, 30, 31, 43 , 44

50, 51, 100 4 2 88 97 98

71 to 78

61 to 68

49, 52 to 58

Philips Semiconductors TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product speciﬁcation Rev. 03 — 21 July 2000 5 of 38

Fig 2. Red channel diagram.

150

kΩ

RIN

VCCAR

RCLP

CLP RAGC

CLKADC

Vref

3 kΩ

45 kΩDAC

DAC

ROR

R0 to R7

RBOT

RGAINC

HSYNCI

ADC

D ≥ R

I2C-BUS

FCE468

OUTPUTS

MUX AGC

CLAMP

CONTROL

FINE GAIN ADJUST

I2C-bus:5 bits (Fr) I2C-bus: 7 bits (Cr)

I2C-bus:8 bits (Or)

COARSE GAIN ADJUST

Philips Semiconductors TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product speciﬁcation Rev. 03 — 21 July 2000 6 of 38

Fig 3. PLL diagram.

FCE465

PHASE

FREQUENCY

DETECTOR

C-bus; 5 bits

(Ip, Up, Do)

C-bus; 1 bit

(Vlevel)

C-bus;12 bits (Di) I

C-bus;

1 bit (Ckb)

phase selector A

C-bus;

5 bits (Pa) I

C-bus;

1 bit (Cka)

C-bus;

1 bit (Ckab)

edge selector

C-bus;

1 bit

(Edge) CLKADC

C-bus;

2 bits (Vco)

loop filter

C-bus;

3 bits (Z)

12 to

100 MHz

DIV N (100 to 4095)

0°/180°

MUX

SYNCHRO

MUX

NCKBO

CZ CP

COAST CKEXT INV

VCO CKADCO

CKAO

CKREFO

CKREF

phase selector B

C-bus;5 bits (Pb)

CKBO

Philips Semiconductors TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product speciﬁcation Rev. 03 — 21 July 2000 7 of 38

7. Pinning information

7.1 Pinning

Fig 4. Pin conﬁguration.

5130

n.c.

AGNDB

BIN

VCCA(B)

BDEC

BCLP

BGAINC

BBOT

BAGC

AGNDG

GIN

VCCA(G)

GDEC

GCLP

GGAINC

GBOT

GAGC

AGNDR

RIN

VCCA(R)

RDEC

RCLP

RGAINC

RBOT

RAGC

n.c.

DEC1

Vref

DEC2

n.c.

VCCO(B)

OGNDG

VCCO(G)

OGNDR

VCCO(R)

CKREFO

100

n.c.

VCCA(PLL)

AGNDPLL

VCCD

CKREF

COAST

CKEXT

INV

HSYNC

CLP

PWDWN

DGND

VCCO(PLL)

CKADCO

CKBO

OGNDPLL

CKAO

n.c.

I2C/3W

ADD1

ADD2

TCK

TDO

DIS

SEN

SDA

VDDD

VSSD

SCL

n.c.

ROR

GOR

BOR

OGNDB

n.c.

FCE469

TDA8752BH

Philips Semiconductors TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product speciﬁcation Rev. 03 — 21 July 2000 8 of 38

7.2 Pin description

Table 3: Pin description

Symbol Pin Description

n.c. 1 not connected

DEC2 2 main regulator decoupling input 2

Vref 3 gain stabilizer voltage reference input

DEC1 4 main regulator decoupling input 1

n.c. 5 not connected

RAGC 6 red channel AGC output

RBOT 7 red channel ladder decoupling input (BOT)

RGAINC 8 red channel gain capacitor input

RCLP 9 red channel gain clamp capacitor input

RDEC 10 red channel gain regulator decoupling input

VCCA(R) 11 red channel gain analog power supply

RIN 12 red channel gain analog input

AGNDR13 red channel gain analog ground

GAGC 14 green channel AGC output

GBOT 15 green channel ladder decoupling input (BOT)

GGAINC 16 green channel gain capacitor input

GCLP 17 green channel gain clamp capacitor input

GDEC 18 green channel gain regulator decoupling input

VCCA(G) 19 green channel gain analog power supply

GIN 20 green channel gain analog input

AGNDG21 green channel gain analog ground

BAGC 22 blue channel AGC output

BBOT 23 blue channel ladder decoupling input (BOT)

BGAINC 24 blue channel gain capacitor input

BCLP 25 blue channel gain clamp capacitor input

BDEC 26 blue channel gain regulator decoupling input

VCCA(B) 27 blue channel gain analog power supply

BIN 28 blue channel gain analog input

AGNDB29 blue channel gain analog ground

n.c. 30 not connected

n.c. 31 not connected

I2C/3W 32 selection input between I2C-bus (active HIGH) and 3-wire

serial bus (active LOW)

ADD1 33 I2C-bus address control input 1

ADD2 34 I2C-bus address control input 2

TCK 35 scan test mode input (active HIGH)

TDO 36 scan test output

DIS 37 I2C-bus and 3-wire serial bus disable control input (disable at

HIGH level)

SEN 38 select enable for 3-wire serial bus input (see Figure 10)

Philips Semiconductors TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product speciﬁcation Rev. 03 — 21 July 2000 9 of 38

SDA 39 I2C-bus/3-wire serial bus data input

VDDD 40 logic I2C-bus/3-wire serial bus digital power supply

VSSD 41 logic I2C-bus/3-wire serial bus digital ground

SCL 42 I2C-bus/3-wire serial bus clock input

n.c. 43 not connected

n.c. 44 not connected

ROR 45 red channel ADC output bit out of range

GOR 46 green channel ADC output bit out of range

BOR 47 blue channel ADC output bit out of range

OGNDB48 blue channel ADC output ground

B0 49 blue channel ADC output bit 0 (LSB)

n.c. 50 not connected

n.c. 51 not connected

B1 52 blue channel ADC output bit 1

B2 53 blue channel ADC output bit 2

B3 54 blue channel ADC output bit 3

B4 55 blue channel ADC output bit 4

B5 56 blue channel ADC output bit 5

B6 57 blue channel ADC output bit 6

B7 58 blue channel ADC output bit 7 (MSB)

VCCO(B) 59 blue channel ADC output power supply

OGNDG60 green channel ADC output ground

G0 61 green channel ADC output bit 0 (LSB)

G1 62 green channel ADC output bit 1

G2 63 green channel ADC output bit 2

G3 64 green channel ADC output bit 3

G4 65 green channel ADC output bit 4

G5 66 green channel ADC output bit 5

G6 67 green channel ADC output bit 6

G7 68 green channel ADC output bit 7 (MSB)

VCCO(G) 69 green channel ADC output power supply

OGNDR70 red channel ADC output ground

R0 71 red channel ADC output bit 0 (LSB)

R1 72 red channel ADC output bit 1

R2 73 red channel ADC output bit 2

R3 74 red channel ADC output bit 3

R4 75 red channel ADC output bit 4

R5 76 red channel ADC output bit 5

R6 77 red channel ADC output bit 6

R7 78 red channel ADC output bit 7 (MSB)

VCCO(R) 79 red channel ADC output power supply

Table 3: Pin description

…continued

Symbol Pin Description

Philips Semiconductors TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product speciﬁcation Rev. 03 — 21 July 2000 10 of 38

CKREFO 80 reference output clock re-synchronized horizontal pulse

CKAO 81 PLL clock output 3 (in phase with reference output clock

CKAO or CKBO)

OGNDPLL 82 PLL digital ground

CKBO 83 PLL clock output 2

CKADCO 84 PLL clock output 1 (in phase with internal ADC clock)

VCCO(PLL) 85 PLL output power supply

DGND 86 digital ground

OE 87 output enable; active LOW (when OE is HIGH, the outputs are

in high-impedance)

PWDWN 88 power-down control input (device is in Power-down mode

when this pin is HIGH)

CLP 89 clamp pulse input (clamp active HIGH)

HSYNC 90 horizontal synchronization input pulse

INV 91 PLL clock output inverter command input (invert when HIGH)

CKEXT 92 external clock input

COAST 93 PLL coast command input

CKREF 94 PLL reference clock input

VCCD 95 digital power supply

AGNDPLL 96 PLL analog ground

CP 97 PLL ﬁlter input

CZ 98 PLL ﬁlter input

VCCA(PLL) 99 PLL analog power supply

n.c. 100 not connected

Table 3: Pin description

…continued

Symbol Pin Description

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