Samsung S3C2451X Bedienungsanleitung

Preliminary

USER'S MANUAL

S3C2451X

RISC Microprocessor

June 11, 2008

Preliminary REV 0.10

Confidential Proprietary of Samsung Electronics Co., Ltd

Preliminary

Important Notice

The information in this publication has been carefully

checked and is believed to be entirely accurate at

the time of publication. Samsung assumes no

responsibility, however, for possible errors or

omissions, or for any consequences resulting from

the use of the information contained herein.

Samsung reserves the right to make changes in its

products or product specifications with the intent to

improve function or design at any time and without

notice and is not required to update this

documentation to reflect such changes.

This publication does not convey to a purchaser of

semiconductor devices described herein any license

under the patent rights of Samsung or others.

Samsung makes no warranty, representation, or

guarantee regarding the suitability of its products for

any particular purpose, nor does Samsung assume

any liability arising out of the application or use of

any product or circuit and specifically disclaims any

and all liability, including without limitation any

consequential or incidental damages.

"Typical" parameters can and do vary in different

applications. All operating parameters, including

"Typicals" must be validated for each customer

application by the customer's technical experts.

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manufacture of said product.

S3C2451X RISC Microprocessor

User's Manual, Preliminary Revision 0.10

any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior

written consent of Samsung Electronics Co.,Ltd.

Samsung Electronics Co., Ltd.

San #24 Nongseo-Dong, Giheung-Gu

Yongin-City Gyeonggi-Do, Korea

446-711

Home Page: http://www.samsungsemi.com/

E-Mail: [email protected]

Printed in the Republic of Korea

Preliminary

S3C2451X_USER’S MANUAL_PRELIMINARY_REV 0.10 iii

Revision History

Revision No Description of Change Refer to Author(s) Date

0.00 - Initial Release (Preliminary) - AP app part. May 26, 2008

0.10 Overview, DRAMC, IOport, TSADC, Electrical

Data updated. - AP app part. June 11, 2008

Preliminary

iv S3C2451X_USER’S MANUAL_REV 0.10

NOTES

Preliminary

S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW

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1 PRODUCT OVERVIEW

INTRODUCTION

This user’s manual describes SAMSUNG's S3C2451X 16/32-bit RISC microprocessor. SAMSUNG’s S3C2451X

is designed to provide hand-held devices and general applications with low-power, and high-performance micro-

controller solution in small die size. To reduce total system cost, the S3C2451X includes the following

components.

The S3C2451X is developed with ARM926EJ core, 65nm CMOS standard cells and a memory complier. Its low-

power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It

adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).

The S3C2451X offers outstanding features with its CPU core, a 16/32-bit ARM926EJ RISC processor designed

by Advanced RISC Machines, Ltd. The ARM926EJ implements MMU, AMBA BUS, and Harvard cache

architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.

By providing a complete set of common system peripherals, the S3C2451X minimizes overall system costs and

eliminates the need to configure additional components. The integrated on-chip functions that are described in

this document include:

•Around 400MHz @ 1.3V, 533MHz @ TBDV Core, 1.8V/2.5V/3.0V/3.3V ROM/SRAM, 1.8V/2.5V

mSDR/mDDR/DDR2 SDRAM, 1.8V/2.5V/3.3V external I/O microprocessor with 16KB I/D-Cache/MMU

•External memory controller (mSDR/mDDR/DDR2 SDRAM Control and Chip Select logic) and CF/ATA I/F

controller

•LCD controller (up to 256K color) with LCD-dedicated DMA

•8-ch DMA controllers with external request pins

•4-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)

•2-ch High Speed SPls

•2 IIC bus interfaces (multi-master support)

•2 IIS Audio CODEC interfaces (24-bit, port 0 supports 5.1ch, port 1 supports 2ch)

•AC97 CODEC Interface

•2 High-Speed MMC and SDMMC combo (SD Host 2.0 and MMC protocol 4.2 compatible)

•2-ch USB Host controller (ver 1.1 Complaint)/1-ch USB Device controller (ver 2.0 Complaint)

•4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer

•10-ch 12-bit ADC and Touch screen interface

•RTC with calendar function

•Camera interface (Max. 8M pixels input support. 2M pixel input support for scaling)

•174 General Purpose I/O ports / 24-ch external interrupt source

•Power control: Normal, Idle, Stop, Deep Stop and Sleep mode

•On-chip clock generator with PLL

Preliminary

PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR

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FEATURES

Architecture

•Integrated system for hand-held devices and

general embedded applications.

•16/32-Bit RISC architecture and powerful

instruction set with ARM926EJ CPU core.

•Enhanced ARM architecture MMU to support

WinCE, EPOC 32 and Linux.

•Instruction cache, data cache, write buffer and

Physical address TAG RAM to reduce the effect

of main memory bandwidth and latency on

performance.

•ARM926EJ CPU core supports the ARM debug

architecture.

•Internal Advanced Microcontroller Bus

Architecture (AMBA) (AMBA2.0, AHB/APB).

System Manager

•Little/Big Endian support.

•Two independent memory bus - one for the

ROM/SRAM bus (ROM Bank0~Bank5) and one

for the DRAM bus (mSDR/mDDR/DDR2

SDRAM Bank0~Bank1)

•Address space: 64M bytes for Rom bank0 ~

bank5, 128M bytes for SDRAM bank0 ~ bank1.

•Supports programmable 8/16-bit data bus width

for ROM/SRAM bank and programmable 16/32-

bit data bus width for SDRAM bank

•Fixed bank start address from Rom bank 0 to

bank 5 and SDRAM bank 0 to bank1.

•Eight memory banks:

– Six memory banks for ROM, SRAM, and

others (NAND/CF etc.).

– Two memory banks for Synchronous DRAM.

•Complete Programmable access cycles for all

memory banks.

•Supports external wait signals to expand the bus

cycle.

•Supports self-refresh mode in SDRAM for

power-down.

•Supports various types of ROM for booting

(NOR/NAND Flash, EEPROM, OneNAND and

others).

NAND Flash Boot Loader

•Supports booting from NAND flash memory.

(Only 8bit boot support)

•64KB for internal SRAM Buffer(8KB internal

buffer for booting)

•Supports storage memory for NAND flash

memory after booting.

•Supports Advanced NAND flash

Cache Memory

•64-way set-associative cache with I-Cache

(16KB) and D-Cache (16KB).

•8words length per line with one valid bit and two

dirty bits per line.

•Pseudo random or round robin replacement

algorithm.

•Write-through or write-back cache operation to

update the main memory.

•The write buffer can hold 16 words of data and

four addresses.

Clock & Power Manager

•On-chip MPLL and EPLL:

EPLL generates the clock to operate USB Host,

IIS, UART, etc.

MPLL generates the clock to operate MCU at

maximum 533MHz @ TBD V.

•Clock can be fed selectively to each function

block by software.

•Power mode: Normal, Idle, Stop, Deep Stop and

Sleep mode

Normal mode: Normal operating mode

Idle mode: The clock for only CPU is stopped.

Stop mode: All clocks are stopped.

Deep Stop mode: CPU power is gated and all

clocks are stopped.

Sleep mode: The Core power including all

peripherals is shut down.

•Woken up by EINT[15:0] or RTC alarm & tick

interrupt from (Deep)Sleep mode and STOP

mode.

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S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW

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FEATURES (Continued)

Interrupt Controller

•77 Interrupt sources

(One Watch dog timer, 5 timers, 12 UARTs, 24

external interrupts, 8 DMA, 2 RTC, 2 ADC, 1 IIC,

2 SPI, 2 SDI, 2 USB, 4 LCD, 1 Battery Fault, 1

NAND, 1 CF, 1 AC97 and 2 CAM I/F, 2 I2S, 2

PCM, 1 2D)

•Level/Edge mode on external interrupt source

•Programmable polarity of edge and level

•Supports Fast Interrupt request (FIQ) for very

urgent interrupt request

Timer with Pulse Width Modulation (PWM)

•4-ch 16-bit Timer with PWM / 1-ch 16-bit internal

timer with DMA-based or interrupt-based

operation

•Programmable duty cycle, frequency, and

polarity

•Dead-zone generation

•Supports external clock sources

RTC (Real Time Clock)

•Full clock feature: msec, second, minute, hour,

date, day, month, and year

•32.768 KHz operation

•Alarm interrupt

•Time tick interrupt

General Purpose Input/Output Ports

•24 external interrupt ports

•174 Multiplexed input/output ports

DMA Controller

•8-ch DMA controller

•Supports memory to memory, IO to memory,

memory to IO, and IO to IO transfers

•Burst transfer mode to enhance the transfer rate

LCD Controller

•Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette

color displays for color

•Supports 16, 24 bpp non-palette true-color

displays for color

•Supports maximum 16M color at 24 bpp mode

•Supports multiple screen size

– Typical actual screen size: 640x480, 320x240,

160x160, and others.

– Maximum frame buffer size is 4Mbytes.

– Maximum virtual screen size in 64K color

mode: 2048x2048, and others

•Support 2 overlay windows for LCD

Camera Interface

•ITU-R BT 601/656 8-bit mode support

•DZI (Digital Zoom In) capability

•Programmable polarity of video sync signals

•Max. 4096x4096 pixels input support

(2048x2048 pixel input support for scaling)

•Image mirror and rotation (X-axis mirror, Y-axis

mirror, and 180° rotation)

•Camera output format (RGB 16/24-bit and

YCbCr 4:2:0/4:2:2 format)

UART

•4-channel UART with DMA-based or interrupt-

based operation

•Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data

transmit/receive (Tx/Rx)

•Supports external clocks for the UART operation

(UEXTCLK)

•Programmable baud rate

•Supports IrDA 1.0

•Loopback mode for testing

•Each channel has internal 64-byte Tx FIFO and

64-byte Rx FIFO.

Preliminary

PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR

1-4

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FEATURES (Continued)

A/D Converter & Touch Screen Interface

•10-ch multiplexed ADC

•Max. 500KSPS and 12-bit Resolution

•Internal FET for direct Touch screen interface

Watchdog Timer

•16-bit Watchdog Timer

•Interrupt request or system reset at time-out

IIC-Bus Interface

•1-ch Multi-Master IIC-Bus

•Serial, 8-bit oriented and bi-directional data

transfers can be made at up to 100 Kbit/s in

Standard mode or up to 400 Kbit/s in Fast mode.

•Line/Point Drawing

•BitBLT, Color Expansion.

•Maximum 2040*2040 image size

•Window clipping

•90°/180°/270°/X-flip/Y-flip Rotation

•Totally 256 3-operand Raster Operation (ROP)

•Alpha Blending

•16/24/32-bpp color format support

•YUV input support (4:2:2, 2-planar)

IIS Multi Audio Interface / IIS-Bus

•2 ports audio interface with DMA-based

operation.

•Port 0 : up to 5.1ch, three 32bit 16depth Tx

FIFOs, One 32bit 16depth Rx FIFO

•Port 1 : 2ch, 32bit 16depth Tx FIFO, 32bit

16depth Rx FIFO

•Serial, 8-/16-/24- bit per channel data transfers

•Supports IIS format and MSB-justified data

format

AC97 Audio Interface

•1port AC97 for audio interface with DMA-based

operation

•16-bit Stereo Audio

PCM Audio interface

•Mono, 16bit PCM, 2 ports audio interface.

•Master mode only, this block always sources the

main shift clock

•Input (16bit 32depth) and output(16bit 32depth)

FIFOs to buffer data

USB Host

•2-port USB Host

•Complies with OHCI Rev. 1.0

•Compatible with USB Specification version 1.1

USB Device

•1-port USB Device

•9 Endpoints for USB Device

•Compatible with USB Specification version 2.0

SD/MMC Host Interface

•SD Standard Host Spec(ver2.0) compatible

•Dedicated DMA access support

•Compatible with SD Memory Card Protocol

version 2.0

•Compatible with SDIO Card Protocol version 1.0

•Compatible with HS-MMC Protocol version 4.2

•512 Bytes FIFO for Tx/Rx

•CE-ATA mode support

SPI Interface

•Compatible with 2-ch Serial Peripheral Interface

Protocol version 2.11 (2ch. High speed SPI

interface)

•2x8 bits Shift register for Tx/Rx

•DMA-based or interrupt-based operation

Operating Voltage Range

•Core: 1.3V for 400MHz

TBD for 533MHz

ROM/SRAM: 1.8V/ 2.5V/3.0V/3.3V

SDRAM: 1.8V/ 2.5V

•I/O: 1.8V/2.5V/3.3V(refer to electrical data)

Operating Frequency

•FCLK Up to 533MHz

•HCLK Up to 133MHz

•PCLK Up to 67MHz

Package

•380 FBGA 13x13

Preliminary

S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW

1-5

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BLOCK DIAGRAM

Figure 1-1. S3C2451X Block Diagram

Preliminary

PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR

1-6

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PIN ASSIGNMENTS

Figure 1-2. S3C2451X Pin Assignments (380-FBGA 0.65mm pitch) Top view

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