Sun Microsystems SPARC T5120 Bedienungsanleitung

SUN SPARC

ENTERPRISE

T5120 AND T5220

SERVER ARCHITECTURE

Unleashing the UltraSPARC

T2 Processor with

CoolThreads

™

Technology

White Paper

October 2007

Sun Microsystems, Inc.

Table of Contents

Executive Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

The Evolution of Chip Multithreading (CMT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Business Challenges for Web 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Rule-Changing Chip Multithreading (CMT) Technology . . . . . . . . . . . . . . . . . . . . . . . 3

Sun SPARC

Enterprise T5120 and T5220 Servers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Space, Watts, and Performance: Introducing the SWaP Metric . . . . . . . . . . . . . . . . 10

The UltraSPARC

T2 Processor with CoolThreads

™

Technology . . . . . . . . . . . . . . 11

UltraSPARC T2: The World's First Massively Threaded System on a Chip (SoC) . . . . 11

Taking Chip Multithreaded Design to the Next Level . . . . . . . . . . . . . . . . . . . . . . . . 12

UltraSPARC T2 Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Sun SPARC Enterprise T5120 and T5220 Server Architecture . . . . . . . . . . . . . . . . 19

System-Level Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Sun SPARC Enterprise T5120 Server Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Sun SPARC Enterprise T5220 Server Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

System Management Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Enterprise-Class Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Scalability and Support for CoolThreads Technology . . . . . . . . . . . . . . . . . . . . . . . . 28

Solaris

™

CoolTools for SPARC: Performance and Rapid Time-to-Market . . . . . . . . . . 33

Sun Java

™

Enterprise System (Java ES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Executive Summary

Sun Microsystems, Inc.

Executive Summary

Use of the Web is changing in fundamental ways, driven by Web 2.0 applications and

the thousands of people who join the global Internet every day through a proliferation

of new interactive devices. The character of applications and services is changing too.

Increasingly, user's don't need to install anything, upgrade anything, license anything,

subscribe to anything, or even buy anything in order to participate and transact. Web

users can even interact directly with content, changing it and improving it. Intellectual

property is shared, rather than locked away, and the most popular services are available

free of charge. Even very small transactions are now encouraged, becoming large in

aggregate. Social networking and other collaborative sites let like-minded people from

around the world share information on enormous range of topics and issues. Business

transactions too are now predominantly Web based.

Serving this dynamic and growing space is becoming very challenging for datacenter

operations. Services need to be able to start small and scale very rapidly, often doubling

capacity every three months even as they remain highly available. Infrastructure must

keep up with these enormous scalability demands, without generating additional

administrative burden. Unfortunately, most datacenters are already severely

constrained by both real estate and power — and energy costs are rising. There is also

a new appreciation for the role that the datacenter plays in reducing energy

consumption and pollution. Virtualization has emerged as an extremely important tool

as organizations seek to consolidate redundant infrastructure, simplify administration,

and leverage under-utilized systems. Security too has never been more important, with

increasing price of data loss and corruption. In addressing these challenges,

organizations can ill afford proprietary infrastructure that imposes arbitrary limitations.

Employing the UltraSPARC

T2 processor — the industry’s ﬁrst massively threaded

system on a Chip (SoC) — Sun SPARC

Enterprise T5120 and T5220 servers offer

breakthrough performance and energy efﬁciency to drive Web 2.0 infrastructure and

address other demanding datacenter challenges. Next-generation CoolThreads

™

chip

multithreading (CMT) technology supports up to 64 threads in as little as one rack unit

(RU) — providing increased computational density while staying within variously

constrained envelopes of power and cooling. Very high levels of integration help reduce

latency, lower costs, and improve security and reliability. Balanced system design

provides support for a wide range of application types — from Web services to high

performance computing (HPC). Uniformity of management interfaces and adoption of

standards helps reduce administrative costs. With both the processor and the Solaris

™

Operating System (Solaris OS) available under open source licensing, organizations are

free to innovate and join with a world-wide technical community.

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Chapter 1

The Evolution of Chip Multithreading (CMT)

By any measure, Sun’s ﬁrst-generation CMT processors were an unprecedented success.

Sun Fire

™

/ Sun SPARC Enterprise T1000 and T2000 servers based on the UltraSPARC T1

processor with CoolThreads technology won enthusiastic praise, and generated the

fastest product ramp in Sun’s history. Delivering up to ﬁve times the throughput in a

quarter of the space and power, these systems even garnered the ﬁrst ever rebate from

a power utility

— a trend that is being repeated across the world. Now CMT

technology is evolving rapidly to meet the constantly changing demands of a wide

range of Web and other applications.

Business Challenges for Web 2.0

Marked by the prevalence of Web services and service-oriented architecture (SOA), the

emerging

Participation Age

promises the ability to deliver rich new content and high-

bandwidth services to larger numbers of users than ever before. Through this

transition, organizations across many industries hope to address larger markets, reduce

costs, and gain better insights into their customers. At the same time, an increasingly

broad array of wired and wireless client devices are bringing network computing into

the everyday lives of millions of people. These trends are redeﬁning datacenter

scalability and capacity requirements, even as they collide with fundamental real

estate, power, and cooling constraints.

•

Building out for Web Scale

Web scale applications engender a new pace and urgency to infrastructure

deployment. Organizations must accelerate time to market and time to service,

while delivering scalable high-quality and high-performance applications and

services. Many need to be able to start small with the ability to scale very quickly,

with new customers and innovative new Web services often implying a doubling of

capacity in months rather than years.

At the same time, organizations must reduce their environmental impact by

working within the power, cooling, and space available in their current

datacenters. Operational costs too are receiving new scrutiny, along with system

administrative costs that can account for up to 40 percent of an IT budget.

Simplicity and speed are paramount, giving organizations the ability to respond

quickly to dynamic business conditions. Organizations are also striving to

eliminate vendor lock-in as they look to preserve previous, current, and future

investments. Open platforms built around open standards help provide maximum

ﬂexibility while reducing costs of both entry and exit.

1.In August of 2006, Pacific Gas and Electric (PG&E) began offering a substantial energy rebate for

purchasing and deploying Sun Fire / Sun SPARC Enterprise T1000 and T2000 servers

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• Driving Datacenter Virtualization and Eco-Efficiency

Coincident with the need to scale services, many datacenters are recognizing the

advantages of deploying fewer standard platforms to run a mixture of commercial

and technical workloads. This process involves consolidating under-utilized and

often sprawling server infrastructures with effective virtualization solutions that

serve to enhance business agility, improve disaster recovery, and reduce operating

costs. This focus can help reduce energy costs and break through datacenter

capacity constraints by improving the amount of realized performance for each

watt of power the datacenter consumes.

Eco-efﬁciency provides tangible beneﬁts, improving

ecology

by reducing carbon

footprint to meet legislative and corporate social responsibility goals, even as it

improves the

economy

of the organization paying the electric bill. As systems are

consolidated onto more dense and capable computing infrastructure, demand for

datacenter real estate is also reduced. With careful planning, this approach can

also improve service uptime and reliability by reducing hardware failures resulting

from excess heat load. Servers with high levels of standard reliability, availability,

and serviceability (RAS) are now considered a requirement.

• Securing the Enterprise at Speed:

Organizations are increasingly interested in securing all communications with

their customers and partners. Given the risks, end-to-end encryption is essential in

order to inspire conﬁdence in security and conﬁdentiality. Encryption is also

increasingly important for storage, helping to secure stored and archived data

even as it provides a mechanism to detect tampering and data corruption.

Unfortunately, the computational costs of increased encryption can increase the

burden on already over-taxed computational resources. Security also needs to take

place at line speed, without introducing bottlenecks that can impact the customer

experience or slow transactions. Solutions must help to ensure security and

privacy for clients and bring business compliance for the organization, all without

impacting performance or increasing costs.

Rule-Changing Chip Multithreading (CMT) Technology

Addressing these challenges has outstripped the capabilities of traditional processors

and systems, and required a fundamentally new approach.

Moore’s Law, and the Diminishing Returns of Traditional Processor

Design

The oft-quoted tenant of Moore’s Law states that the number of transistors that will ﬁt

in a square inch of integrated circuitry will approximately double every two years. For

over three decades the pace of Moore’s law has held, driving processor performance to

new heights. Processor manufacturers have long exploited these gains in chip real

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estate to build increasingly complex processors, with instruction-level parallelism (ILP)

as a goal. Today these traditional processors employ very high frequencies along with a

variety of sophisticated tactics to accelerate a single instruction pipeline, including:

• Large caches

• Superscalar designs

• Out-of-order execution

• Very high clock rates

• Deep pipelines

• Speculative pre-fetches

While these techniques have produced faster processors with impressive-sounding

multiple-gigahertz frequencies, they have largely resulted in complex, hot, and power-

hungry processors that are not well suited to the types of workloads often found in

modern datacenters. In fact, many datacenter workloads are simply unable to take

advantage of the hard-won ILP provided by these processors. Applications with high

shared memory and high simultaneous user or transaction counts are typically more

focused on processing a large number of simultaneous threads (thread-level

parallelism, TLP) rather than running a single thread as quickly as possible (ILP).

Making matters worse, the majority of ILP in existing applications has already been

extracted and further gains promise to be small. In addition, microprocessor frequency

scaling itself has leveled off because of microprocessor power issues. With higher clock

speeds, each successive processor generation has seemingly demanded more power

than the last, and microprocessor frequency scaling has leveled off in the 2-3 GHz range

as a result. Deploying pipelined Superscalar processors requires more power, limiting

this approach by the fundamental ability to cool the processors.

Chip Multiprocessing with Multicore Processors

To address these issues, many in the microprocessor industry have used the transistor

budget provided by Moore's Law to group two or even four conventional processor

cores on a single physical die — creating multicore processors (or chip multiprocessors,

CMP). The individual processor cores introduced by many CMP designs have no greater

performance than previous single-processor chips, and in fact, have been observed to

run single-threaded applications more slowly than single-core processor versions.

However, the aggregate chip performance increases since multiple programs (or

multiple threads) can be accommodated in parallel (thread level parallelism).

Unfortunately, most currently-available (or soon to be available) chip multiprocessors

simply replicate cores from existing (single-threaded) processor designs. This approach

typically yields only slight improvements in aggregate performance since it ignores key

performance issues such as memory speed and hardware thread context switching. As

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a result, while these designs provide some additional throughput and scalability, they

can consume considerable power and generate signiﬁcant heat — without a

commensurate increase in overall performance.

Chip Multithreading (CMT) with CoolThreads

™

Technology

Sun engineers were early to recognize the disparity between processor speeds and

memory access rates. While processor speeds continue to double every two years,

memory speeds have typically doubled only every six years. As a result, memory latency

now dominates much application performance, erasing even very impressive gains in

clock rates. This growing disconnect is the result of memory suppliers focusing on

density and cost as their design center, rather than speed.

Unfortunately, this relative gap between processor and memory speeds leaves ultra-fast

processors idle as much as 85 percent of the time, waiting for memory transactions to

complete. Ironically, as traditional processor execution pipelines get faster and more

complex, the effect of memory latency grows — fast, expensive processors spend more

cycles doing nothing. Worse still, idle processors continue to draw power and generate

heat. It is easy to see that frequency (gigahertz) is truly a misleading indicator of real

performance.

First introduced with the UltraSPARC T1 processor, chip multithreading takes advantage

of CMP advances, but adds a critical capability —

the ability to scale with threads

rather than frequency

. Unlike traditional single-threaded processors and even most

current multicore (CMP) processors, hardware multithreaded processor cores allow

rapid switching between active threads as other threads stall for memory. Figure 1

illustrates the difference between CMP, ﬁne-grained hardware multithreading (FG-MT),

and chip multithreading. The key to this approach is that each core in a CMT processor

is designed to switch between multiple threads on each clock cycle. As a result, the

processor’s execution pipeline remains active doing real useful work, even as memory

operations for stalled threads continue in parallel.

Figure 1. Chip multithreading combines CMP and ﬁne-grained hardware multithreading

Chip

Multiprocessing

(CMP)

Fine-Grained

Multithreading

(FG-MT)

Chip

Multithreading

(CMT)

(n cores

per processor)

(m strands

per core)

(n x m threads

per processor)

Memory Latency Compute

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Chip multithreading provides real value since it increases the ability of the execution

pipeline to do actual work on any given clock cycle. Utilization of the processor pipeline

is greatly enhanced since a number of execution threads now share its resources. The

negative effects of memory latency are effectively masked, since the processor and

memory subsystems remain active in parallel to the processor execution pipeline.

Because these individual processor cores implement much simpler pipelines that focus

on scaling with threads rather than frequency (emphasizing TLP over ILP), they are also

substantially cooler and require signiﬁcantly less electrical energy to operate. This

innovative approach results in CoolThreads processor technology — multiple physical

instruction execution pipelines (one for each core), with multiple active thread contexts

per core.

The UltraSPARC

T2 Processor with CoolThreads Technology

Unlike complex single-threaded processors, CMT processors utilize the available

transistor budget to implement multiple hardware multithreaded processor cores on a

chip die. The UltraSPARC T2 processor takes the CMT model to the next level, providing

up to eight cores with each core supporting up to eight threads via two independent

pipelines per core — effectively doubling the throughput of the UltraSPARC T1

processor. In addition, the UltraSPARC T2 processor uses this transistor budget to

implement the industry’s ﬁrst massively threaded System on a Chip (SoC), with a single

processor die hosting:

• Up to 64 threads per processor (up to eight cores supporting eight threads each)

• On-chip Level-1 and Level-2 caches

• Per-core ﬂoating point capabilities

• Per-core cryptographic acceleration

• Two on-chip 10 Gb Ethernet interfaces

• On-chip PCI Express interface

Through this SoC design, the UltraSPARC T2 processor signiﬁcantly enhances the

general purpose nature of the CPU by building in eight ﬂoating point units (1 per core).

Enhanced ﬂoating point capabilities open the UltraSPARC T2 to the world of compute-

intensive applications as well as the traditionally CMT friendly datacenter throughput

applications. No-cost security and cryptographic acceleration is provided by the on-chip,

per-core streaming accelerators. In addition, the ability to move data in and out of the

processor is signiﬁcantly aided by an integrated PCI-Express interface and dual

10 Gigabit Ethernet interfaces.

Sun SPARC

Enterprise T5120 and T5220 Servers

Sun SPARC Enterprise T5120 and T5220 servers (Figure 2) are designed to leverage the

considerable resources of the UltraSPARC T2 processor in the form of cost-effective

general-purpose platforms. These systems deliver up to twice the throughput of their

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predecessors, while leading competitors in terms of performance, performance per

watt, and

SWaP

performance (as evaluated by the Space, Watts, and Performance

metric detailed later in this section). These systems also extend the beneﬁts of CMT

from multithreaded commercial workloads into technical workloads rich in ﬂoating

point operations.

With support for 64 threads, large memory, cryptographic acceleration, and integrated

on-chip 10 Gb Ethernet networking and I/O technology, these servers represent a

departure from traditional system design. The 1U Sun SPARC Enterprise T5120 is ideal

for providing high throughput within signiﬁcant power, cooling, and space constraints,

delivering a 64-thread UltraSPARC T2 processor in a space- and power-efﬁcient 1U

rackmount package. As a compute node with massively horizontally scaled

environments, the Sun SPARC Enterprise T5120 can help provide a substantial building

block for application tier, Web services, or even high performance computing (HPC)

infrastructure. Network infrastructure applications such as portal, directory, network

identity, ﬁle service, and backup are all a good ﬁt for this server.

The Sun SPARC Enterprise T5220 server provides both throughput as well as

expandability, with extra I/O and internal disk options afforded by the 2U rackmount

form factor. With greater I/O and internal disk, typical workloads include demanding

mid-tier application server deployments or Web- and application-tier consolidation,

virtualization, and consolidation projects requiring maximum uptime with future

growth and integration into diverse environments. The Sun SPARC Enterprise T5220 is

also ideal for OLTP database deployments.

Figure 2. Sun SPARC Enterprise T5120 and T5220 servers

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Designed to complement each other, as well as the rest of Sun’s server product line, the

Sun SPARC Enterprise T5120 and T5220 servers address the dynamic needs of the

modern datacenter.

• Efficient and Predictable Scalability

With support for 64 threads and large memories, Sun SPARC Enterprise T5120 and

T5220 servers are the ﬁrst to utilize the 10 Gb Ethernet, I/O, and cryptographic

acceleration provided directly by the UltraSPARC T2 processor chip. This approach

provides leading levels of performance and scalability with extremely high levels

of power, heat, and space efﬁciency.

• Accelerated Time to Market

Sun SPARC Enterprise T5120 and T5220 servers running the Solaris OS provide full

binary compatibility with earlier UltraSPARC systems, preserving investments and

speeding time to market. Sun’s CoolTools for SPARC help accelerate application

selection, proﬁling, testing, tuning, debugging and deployment of key

applications on CMT systems.

• Simplified Management

Each Sun SPARC Enterprise T5120 and T5220 server provides an Integrated Lights

Out Management (ILOM) service processor, compatible with Sun’s x64 servers.

ILOM provides a command line interface (CLI), a Web-based graphical user

interface (GUI), and Intelligent Platform Management Interface (IPMI)

functionality to aid with out-of-band monitoring and administration. ILOM on

these systems also provides an Advanced Lights Out Management (ALOM)

backwards compatibility mode for administrators familiar with Sun Fire / Sun

SPARC Enterprise T1000 and T2000 servers.

• The Industry's Most Open Platform

Sun SPARC Enterprise servers are the industry’s most open platforms, providing

the only mainstream processor and hypervisor offered under the GNU General

Public License (GPL). These systems offer a choice of operating systems, including

the Solaris OS, Linux, and BSD variants. The Solaris OS is free and open, offering

full binary compatibility and enterprise-class features. Sun Java

™

Enterprise

System middleware is pre-loaded.

• Industry-Leading Tools for Virtualization and Consolidation

Sun’s chip multithreading (CMT) technology is ideal for consolidation, providing

low-level multithreading support for virtualization at every layer of the technology

stack. Sun Logical Domains exploit the UltraSPARC T2 processor’s 64 threads to

support multiple guest operating system instances, while Solaris Containers

provide virtualization within a single Solaris OS instance. The advanced ZFS ﬁle

system provides storage virtualization for storage and considerable scalability.

Andere Handbücher für SPARC T5120

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