Texas Instruments DS125RT410 Bedienungsanleitung

DS125RT410

www.ti.com

SNLS459 –APRIL 2011

DS125RT410 Low Power Multi-Rate Quad Channel Retimer

Check for Samples: DS125RT410

1FEATURES APPLICATIONS

2• Each channel independently locks to data • Front port SFF 8431 (SFP+) optical and direct •

rates from 9.8 to 12.5 Gbps and submultiples Input signal detection, CDR lock attach copper

• Fast lock operation based on protocol-select • Backplane reach extension, data retimer

mode • Ethernet: 10GbE, 1GbE

• Low latency (~300ps) • CPRI: Line bit rate options 3–7

• Adaptive equalization up to 34 dB boost at 5 • Interlaken: All lane bit rates

GHz For other data rates and data transmission

• Adjustable transmit VOD : 600 to 1300 mVp-p protocols, other pin-compatible devices in the

• Adjustable transmit de-emphasis to -15 dB retimer family can be used.

• Typical Power Dissipation (EQ+CDR+DE): 150 DESCRIPTION

mW / channel The DS125RT410 is four channel retimers with

• Programmable output polarity inversion integrated signal conditioning. The devices include a

• Input signal detection, CDR lock fully adaptive Continuous-Time Linear Equalizer

detection/indicator (CTLE), Clock and Data Recovery (CDR) and

transmit De-Emphasis (DE) driver to enable data

• On-chip Eye Monitor (EOM), PRBS generator transmission over long, lossy and crosstalk-impaired

• Single 2.5 V ±5% power supply highspeed serial links to achieve BER < 1×10-15.

• SMBus/EEPROM configuration modes Each channel can independently lock to data rate

• Operating temperature range of -40 to 85°C from 9.8 to 12.5 Gbps, and associated sub rates (div

• RHS 48-pin 7 mm x 7 mm package by 2, 4 and 8) to support a variety communication

protocols. A 25 MHz reference clock is required,

• Easy pin compatible upgrade between which need not be synchronous with the serial data.

repeater and retimers

– DS100RT410 (EQ+CDR+DE): 10.3125 Gbps The programmable settings can be applied using the

SMBus (I2C) interface, or they can be loaded via an

– DS100DF410 (EQ+DFE+CDR+DE): 10.3125 external EEPROM. An on-chip eye monitor and a

Gbps PRBS generator allow real-time measurement of

– DS110RT410 (EQ+CDR+DE): 8.5 - 11.3 Gbps high-speed serial data for system bring-up or field

– DS110DF410 (EQ+DFE+CDR+DE): 8.5 - 11.3 tuning. Flow-through pinout and single power supply

Gbps make the DS125RT410 easy to use.

– DS125RT410 (EQ+CDR+DE): 9.8 - 12.5 Gbps The device is offered in a RHS 48-pin, 7 mm x 7 mm

package with flow-through pinout for the high speed

– DS125DF410 (EQ+DFE+CDR+DE): 9.8 - 12.5 signals.

Gbps

– DS100BR410 (EQ+DE): Up to 10.3125 Gbps

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Line Card

Switch Fabric

ASIC

Back

Plane/

Mid

Plane

Optical Modules

DS125RT410 Passive Copper

ASIC

DS125RT410

Connector

Noisy Signal

Clean Signal

DS125RT410

10GbE

CPRI

Interlaken

Others

SFP+ (SFF8431)

QSFP

DS125RT410

SNLS459 –APRIL 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Typical Application Diagram

Product Folder Links: DS125RT410

TOP VIEW

RXN3

VDD

RXN2

VDD

RXN1

VDD

RXN0

TXN3

GND

TXN2

GND

TXP1

TXN0

RXP1

VDD

RXP2

RXP3 TXP3

TXP2

GND

1RXP0 36 TXP0

32 TXN1

DS125RT410

DAP = GND

LPF_CP_3

LPF_REF_3

VDD

LOCK_3/ADDR_3

SDC

SDA

REFCLK_IN

EN_SMB

LOCK_2/ADDR_2

GND

LPF_REF_2

LPF_CP_2

7 mm x 7 mm, 0.5 mm pitch

LPF_REF_1

LPF_CP_1

GND

LOCK_1/ADDR_1

ALL_DONE

REFCLK_OUT

INT

READ_EN

LOCK_0/ADDR_0

VDD

LPF_REF_0

LPF_CP_0

DS125RT410

www.ti.com

SNLS459 –APRIL 2011

Connection Diagram

Product Folder Links: DS125RT410

DS125RT410

SNLS459 –APRIL 2011

www.ti.com

Pin Descriptions

Pin Name Pin # I/O, Type Description

HIGH-SPEED DIFFERENTIAL I/O

RXP0 1 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer.

RXN0 2 Nominal differential input impedance = 100Ω.

RXP1 4 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer.

RXN1 5 Nominal differential input impedance = 100Ω.

RXP2 8 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer.

RXN2 9 Nominal differential input impedance = 100Ω.

RXP3 11 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer.

RXN3 12 Nominal differential input impedance = 100Ω.

TXP0 36 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver.

TXN0 35 Nominal differential output impedance = 100Ω.

TXP1 33 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver.

TXN1 32 Nominal differential output impedance = 100Ω.

TXP2 29 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver.

TXN2 28 Nominal differential output impedance = 100Ω.

TXP3 26 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver.

TXN3 25 Nominal differential output impedance = 100Ω.

LOOP FILTER CONNECTION PINS

LPF_CP_0 47 I/O, analog Loop filter connection

LPF_REF_0 48 Place a 22 nF ± 10% Capacitor between LPF_CP_0 and LPF_REF_0

LPF_CP_1 38 I/O, analog Loop filter connection

LPF_REF_1 37 Place a 22 nF ± 10% Capacitor between LPF_CP_1 and LPF_REF_1

LPF_CP_2 23 I/O, analog Loop filter connection

LPF_REF_2 24 Place a 22 nF ± 10% Capacitor between LPF_CP_2 and LPF_REF_2

LPF_CP_3 14 I/O, analog Loop filter connection

LPF_REF_3 13 Place a 22 nF ± 10% Capacitor between LPF_CP_3 and LPF_REF_3

REFERENCE CLOCK I/O

REFCLK_IN 19 I, 2.5V analog Input is 2.5 V, 25 MHz ± 100 ppm reference clock from external oscillator

No stringent phase noise requirement

REFCLK_OUT 42 O, 2.5V analog Output is 2.5 V, buffered replica of reference clock input for connecting multiple

DS125RT410s on a board.

LOCK INDICATOR PINS

LOCK0 45 O, 2.5V Output is 2.5 V, the pin is high when CDR lock is attained on the corresponding

LOCK1 40 LVCMOS channel.

LOCK2 21 Note that these pins are shared with SMBus address strap input functions read

LOCK3 16 at startup.

SMBus MASTER MODE PINS

ALL_DONE 41 O, 2.5V Output is 2.5 V, the pin goes low to indicate that the SMBus master

LVCMOS EEPROMread has been completed.

READ_EN 44 I, 2.5V Input is 2.5 V, a transition from high to low starts the load from the external

LVCMOS EEPROM. The READ_EN pin must be tied low when in SMBus slave mode.

INTERRUPT OUTPUT

INT 43 O, 3.3V Used to signal horizontal or vertical eye opening out of tolerance, loss of signal

LVCMOS, Open detect, or CDR unlock.

Drain External 2KΩto 5KΩpull-up resistor is required.

Pin is 3.3 V LVCMOS tolerant.

SERIAL MANAGEMENT BUS (SMBus) INTERFACE

EN_SMB 20 I, 2.5V analog Input is 2.5 V, selects SMBus master mode or SMBus slave mode.

EN_SMB = High for slave mode

EN_SMB = Float for master mode

Tie READ_EN pin low for SMBus slave mode. See Table 3

SDA 18 I/O, 3.3V Data Input / Open Drain Output

LVCMOS, Open External 2KΩto 5KΩpull-up resistor is required.

Drain Pin is 3.3 V LVCMOS tolerant.

SDC 17 I/O, 3.3V Clock Input / Open Drain Clock Output

LVCMOS, Open External 2KΩto 5KΩpull-up resistor is required.

Drain Pin is 3.3 V LVCMOS tolerant.

Product Folder Links: DS125RT410

DS125RT410

www.ti.com

SNLS459 –APRIL 2011

Pin Descriptions (continued)

Pin Name Pin # I/O, Type Description

ADDR_0 45 I, 2.5V Input is 2.5 V, the ADDR_[3:0] pins set the SMBus address for the retimer.

ADDR_1 40 LVCMOS These pins are strap inputs. Their state is read on power-up to set the SMBus

ADDR_2 21 address in SMBus control mode.

ADDR_3 16 High = 1KΩto VDD, Low = 1KΩto GND

Note that these pins are shared with the lock indicator functions. See Table 4

POWER

VDD 3, 6, 7, Power VDD = 2.5 V ± 5%

10, 15, 46

GND 22, 27, Power Ground reference.

30, 31,

34, 39

DAP PAD Power Ground reference. The exposed pad at the center of the package must be

connected to ground plane of the board with at least 4 vias to lower the ground

impedance and improve the thermal performance of the package.

Absolute Maximum Ratings (1)

Supply Voltage (VDD) -0.5V to +2.75V

2.5 I/O Voltage -0.5V to +2.75V

(LVCMOS and Analog)

3.3 LVCMOS I/O Voltage -0.5V to +4.0V

(SDA, SDC, INT)

Signal Input Voltage (RXPn, RXNn) -0.5V to +2.75V

Signal Output Voltage (TXPn, TXNn) -0.5V to +2.75V

Junction Temperature +150°C

Storage Temperature -65°C to +150°C

ESD Rating

HBM, STD - JESD22-A114F ≥6 kV

MM, STD - JESD22-A115-A ≥250 V

CDM, STD - JESD22-C101-D ≥1250 V

Thermal Resistance

θJA, No Airflow,

4 layer JEDEC, 9 thermal vias 26.1 °C/W

For soldering specifications: see product folder at http://www.ti.com/lit/an/snoa549c/snoa549c.pdf

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating

Conditions indicate conditions at which the device is functional and the device should not be operated outside these conditions.

Recommended Operating Conditions Min Typ Max Units

Supply Voltage

VDD to GND 2.375 2.5 2.625 V

Ambient Temperature -40 25 +85 °C

Product Folder Links: DS125RT410

DS125RT410

SNLS459 –APRIL 2011

www.ti.com

Electrical Characteristics

Over recommended operating supply and temperature ranges with default register settings unless otherwise specified. (1)

Symbol Parameter Conditions Min Typ Max Units

POWER

PD Power Supply Consumption Average Power Consumption(2) 660 mW

Max Transient Power Supply 500 610 mA

Current(3)

NTPS Supply Noise Tolerance(4) 50 Hz to 100 Hz 100 mVP-P

100 Hz to 10 MHz 40 mVP-P

10 MHz to 5.0 GHz 10 mVP-P

2.5V LVCMOS DC SPECIFICATIONS

VIH High Level Input Voltage 1.75 VDD V

VIL Low Level Input Voltage GND 0.7 V

VOH High Level Output Voltage IOH = -3mA 2.0 V

VOL Low Level Output Voltage IOL = 3mA 0.4 V

IIN Input Leakage Current VIN = VDD +10 μA

VIN = GND -10 μA

IIH Input High Current (EN_SMB pin) VIN = VDD +55 μA

IIL Input Low Current (EN_SMB pin) VIN = GND -110 μA

3.3 V LVCMOS DC SPECIFICATIONS (SDA, SDC, INT)

VIH High Level Input Voltage VDD = 2.5 V 1.75 3.6 V

VIL Low Level Input Voltage VDD = 2.5 V GND 0.7 V

VOL Low Level Output Voltage IPULLUP = 3mA 0.4 V

IIH Input High Current VIN = 3.6 V, VDD = 2.5V +20 +40 μA

IIL Input Low Current VIN = GND, VDD = 2.5V -10 +10 μA

fSDC SMBus clock rate 100 400 KHz

DATA BIT RATES

RBBit Rate Range 9.8 12.5 Gbps

SIGNAL DETECT

SDH Signal Detect ON Threshold Level Default input signal level to assert 70 mVp-p

signal detect, 10.3125 Gbps,

PRBS-31

SDL Signal Detect OFF Threshold Level Default input signal level to de- 10 mVp-p

assert signal detect, 10.3125 Gbps,

PRBS-31

(1) Typical values represent most likely parametric norms at VDD = 2.5V, TA= 25°C., and at the Recommended Operation Conditions at the

time of product characterization.

(2) VDD= 2.5V, TA= 25°C. All four channels active and locked.

(3) Max momentary power supply current lasting less than 1s. The retimer may consume more power than the maximum average power

rating during the time required to acquire CDR lock.

(4) Allowed supply noise (mVP-P sine wave) under typical conditions.

Product Folder Links: DS125RT410

DS125RT410

www.ti.com

SNLS459 –APRIL 2011

Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges with default register settings unless otherwise specified. (1)

Symbol Parameter Conditions Min Typ Max Units

RECEIVER INPUTS (RXPn, RXNn)

VTX2, min Minimum Source Transmit Launch (5) 600 mVP-P

Signal Level (IN, diff)

VTX2, max Maximum Source Transmit Launch (5) 1000 mVP-P

Signal Level (IN, diff)

VTX1, max Maximum Source Transmit Launch (6) 1200 mVP-P

Signal Level (IN, diff)

VTX0, max Maximum Source Transmit Launch (7) 1600 mVP-P

Signal Level (IN, diff)

LRI Maximum Differential Input Return 100 MHz – 6 GHz -15 dB

Loss - |SDD11|

ZDDifferential Input Impedance 100 MHz – 6 GHz 100 Ω

ZSSingle-Ended Input Impedance 100 MHz – 6 GHz 50 Ω

DRIVER OUTPUTS (TXPn, TXNn)

VOD0 Differential output voltage Differential measurement with

OUT+ and OUT- terminated by

50Ωto GND, AC-Coupled,

SMBus register VOD control 400 675 mVP-P

(Register 0x2d bits 2:0) set to 0,

minimum VOD

De-emphasis control set to

minimum (0 dB)

VOD7 Differential output voltage Differential measurement with

OUT+ and OUT- terminated by

50Ωto GND, AC-Coupled

SMBus register VOD control 1000 mVP-P

(Register 0x2d bits 2:0) set to 7,

maximum VOD

De-emphasis control set to

minimum (0 dB)

VOD_DE De-emphasis level Differential measurement with

(8) OUT+ and OUT- terminated by

50Ωto GND, AC-Coupled

Set by SMBus register control to -15 dB

maximum de-emphasis setting

Relative to the nominal 0 dB de-

emphasis level set at the minimum

de-emphasis setting

tR, tFTransition time (rise and fall Transition time control = Full Slew 39 ps

times)(8) (9) Rate

Transition time control = Limited 50 ps

Slew Rate

LRO Maximum Differential Output 100 MHz – 6 GHz(10) -15 dB

Return Loss - |SDD22|

tDP Propagation Delay Retimed data 300 ps

TDE De-emphasis pulse duration(11) Measured at VOD = 1000 mVP-P,75 ps

de-emphasis setting = -12 dB

TJ Output total jitter Measured at BER = 10-12(12) 10 ps

(5) Differential signal amplitude at the transmitter output providing < 1x10-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data

pattern. Input transmission channel is 40-inch long FR-4 stripline, 4-mil trace width.

(6) Differential signal amplitude at the transmitter output providing < 1x10-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data

pattern. Input transmission channel is 30-inch long FR-4 stripline, 4-mil trace width.

(7) Differential signal amplitude at the transmitter output providing < 1x10-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data

pattern. No input transmission channel.

(8) Measured with clock-like {11111 00000} pattern.

(9) Slew rate is controlled by SMBus register settings.

(10) Measured with 10 MHz clock pattern output.

(11) De-emphasis pulse width varies with VOD and de-emphasis settings.

(12) Typical with no output de-emphasis, minimum output transmission channel.

Product Folder Links: DS125RT410

DS125RT410

SNLS459 –APRIL 2011

www.ti.com

Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges with default register settings unless otherwise specified. (1)

Symbol Parameter Conditions Min Typ Max Units

TSKEW Intra Pair Skew Difference in 50% crossing

between TXPn and TXNn for any 3 ps

output

CLOCK AND DATA RECOVERY

BWPLL PLL Bandwidth Measured at 10.3125 Gbps 5 MHz

-3 dB

JTOL Input sinusoidal jitter tolerance Measured at BER = 10-15

10 kHz to 250 MHz sinusoidal jitter 0.6 UI

frequency

JTRANS Jitter Transfer Measured at BER = 10-15

Sinusoidal jitter at 10 MHz jitter -6 dB

frequency

TLOCK CDR Lock Time Measured at 10.3125 Gbps 15 ms

Product Folder Links: DS125RT410

RXPn

RXNn

EQ RETIMER DRIVER

TXPn

TXNn

SMBus

SDA

SDC

REFCLK_IN

SMBus

LOCK

EN_SMB

100100

Signal

Detect

SMBus

CDR

DS125RT410

www.ti.com

SNLS459 –APRIL 2011

FUNCTIONAL DESCRIPTION

The DS125RT410 is a low-power, multi-rate, 4-channel retimer. Each of the four channels operates

independently. Each channel includes a Continuous-Time Linear Equalizer (CTLE) which compensates for the

presence of a dispersive transmission channel between the source and the DS125RT410's input.

Each channel includes an independent Voltage-Controlled Oscillator (VCO) and Phase-Locked Loop (PLL) which

produce a clean clock. The clean clock produced by the VCO and the PLL is phase-locked to the incoming data

clock and the high-frequency jitter on the incoming data is attenuated by the PLL, producing a clean clock with

substantially reduced jitter. This clean clock is used to retime the incoming data, removing high-frequency jitter

from the data stream and producing a data output signal with reduced jitter.

Each channel of the DS125RT410 features an output driver with programable differential output voltage and

output de-emphasis control. The output de-emphasis compensates for dispersion in the transmission channel at

the output of the DS125RT410.

These three functions together make up the data path for the DS125RT410.

Figure 1. DS125RT410 Data Path Block Diagram — One of Four Channels

Device Data Path Operation

The data path operation of the DS125RT410 comprises three functional sections as shown in the data path block

diagram of Figure 1. The three functional sections are as follows.

• Channel Equalization

• Clock and Data Recovery

• Output Driver

Channel Equalization

Physical transmission media such as traces on printed circuit boards (PCBs) or copper cables exhibit a low-pass

frequency response characteristic. The magnitude of the high-frequency loss varies with the length of the

transmission media and with the loss of the materials which comprise it. This differential high-frequency loss and

the frequency-dependent group delay of the transmission media introduce inter-symbol interference in the high-

speed broadband signals propagating through the transmission media.

The DS125RT410 applies a frequency-response equalization function to the incoming data stream. The

equalization function reduces the effect of the frequency-dependent loss in the transmission media between the

transmitter output and the input of the DS125RT410. The DS125RT410 includes a Continuous Time Linear

Equalizer or CTLE which applies the frequency-response equalization. The CTLE is designed to provide a

controlled-amount of high-frequency boost to the signal in the frequency domain to compensate for the

frequency-dependent loss in the transmission media.

Product Folder Links: DS125RT410

0 1 2 3 4 5 6 7 8 9 10

-1.0

-0.5

0.0

0.5

1.0

VOD (V)

TIME (UI)

DS125RT410

SNLS459 –APRIL 2011

www.ti.com

The CTLE is a four-stage variable boost high-gain amplifier with a quasi-high-pass characteristic. Each of the

four stages can be set to provide various amounts of high-frequency boost with the overall transfer function of

the CTLE set by the cascade of all four sections. The high-frequency boost of each CTLE stage is variable. The

optimum boost for each stage is one that causes the transfer function magnitude of the transmission channel and

the CTLE in cascade to be flat over a band of frequencies extending up to half the data rate which is commonly

referred to as the “Nyquist” frequency. In normal operation, the DS125RT410 sets the boost of the CTLE

automatically to approximate the optimum cascaded response.

Clock and Data Recovery

The DS125RT410 performs its clock and data recovery function by detecting the bit transitions in the incoming

data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit

transitions. This process produces a recovered clock with greatly reduced jitter at jitter frequencies outside the

bandwidth of the CDR Phase-Locked Loop (PLL). This is the primary benefit of using the DS125RT410 in a

system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter budget for the

system.

The DS125RT410 uses the 25 MHz reference to determine the coarse tuning setting for its internal VCO. On

power-up, on CDR reset, and when the DS125RT410 loses lock and cannot re-acquire lock after four attempts,

the 25 MHz reference is used to calibrate the VCO frequency. The required VCO frequency is set by using the

rate/subrate settings (see Table 1) or by manually setting the PPM count and divide ratio. To calibrate the VCO

frequency, the DS125RT410 searches through the available VCO coarse tuning settings and counts the divided

VCO frequency using the 25 MHz reference as a clock source. The VCO coarse tuning setting which provides

the VCO frequency closest to the required frequency is stored, and this coarse tuning setting is used for

subsequent operation. This produces a fast, robust phase lock to the input signal.

Output Driver

The DS125RT410 is commonly used in applications where lossy transmission media exist both at the input and

the output of the DS125RT410. The CTLE compensates for lossy transmission media at the input to the

DS125RT410. The output de-emphasis compensates for the lossy transmission media at the output of the

DS125RT410.

When there is a transition in the output data stream, the output differential voltage reaches its configured

maximum value within the configured rise/fall time of the output driver. Following this, the differential voltage

rapidly falls off until it reaches the configured VOD level minus the configured de-emphasis level. This

accentuates the high-frequency components of the output driver signal at the expense of the low-frequency

components. This pre-distorted signal, with its high-frequency components emphasized relative to its low-

frequency components, travels down the dispersive transmission media at the output of the DS125RT410 with

less inter-symbol interference than an undistorted signal would exhibit.

The output driver is capable of driving variable output voltages with variable amounts of analog de-emphasis.

The output voltage and de-emphasis level can be configured by writing registers over the SMBus. The

DS125RT410 cannot determine independently the appropriate output voltage or de-emphasis setting, so the user

is responsible for configuring these parameters. They can be set for each channel independently.

An idealized transmit waveform with analog de-emphasis applied is shown in Figure 2.

Figure 2. Idealized De-Emphasis Waveform

Product Folder Links: DS125RT410

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