Texas Instruments TAS3002 Installations- und Benutzerhandbuch

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2001 Digital Audio: Digital Speakers

Data

Manua

SLAS307B

1−1

1 Introduction

1.1 Description

The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital

parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides

high-quality, soft digital volume, bass, and treble control. All control parameters are uploaded from an outside MCU

through the I2C slave port or from an external EEPROM through the I2C master port.

The TAS3002 device also has an integrated 24-bit stereo codec with two I2C-selectable, single-ended inputs per

channel.

The digital parametric equalization consists of seven cascaded, independent biquad filters per channel. Each biquad

filter has five 24-bit coefficients that can be configured into many different filter functions (such as band-pass,

high-pass, and low-pass).

The internal loudness contour algorithm can be controlled and programmed with an I2C command.

Dynamic range compression/expansion (DRCE) is programmable through the I2C port. The system designer can set

the threshold, energy estimation time constant, compression ratio, and attack and decay time constants.

The TAS3002 device supports 13 serial interface formats (I2S, left justified, right justified) with data word lengths of

16, 18, 20, or 24 bits. The sampling frequency (fS) may be set to 32 kHz, 44.1 kHz, or 48 kHz. The 13 serial interface

formats are listed and described in Section 2.1.

The TAS3002 device uses a system clock generated by the internal phase-locked loop (PLL). The reference clock

for the PLL is provided by an external master clock (MCLK) of 256fSor 512fS, or a 256fScrystal.

The TAS3002 device has six internally configurable general-purpose input (GPI) terminals that control volume, bass,

treble, and equalization. Each GPI terminal has a debounce algorithm that is programmed into the TAS3002 internal

microcontroller.

1.2 Features

•Programmable seven-band parametric equalization

•Programmable digital volume control

•Programmable digital bass and treble control

•Programmable dynamic range compression/expansion (DRCE)

•Programmable loudness contour/dynamic bass control

•Configurable serial port for audio data

•Two input data channels that can be mixed with digital data from the analog-to-digital converter (ADC) of

the codec (analog input). These channels are controlled by I2C commands.

•Three output data channels: Left and right data go through equalization; bass, treble, DRCE, and volume

to SDOUT1; SDOUT2 mixes left and right data. SDOUT2 operates as a center channel or subwoofer

channel. The output of the ADC is available for additional processing.

•Capability to digitally mix left and right input channels for a monaural output to facilitate subwoofer operation

•Serial I2C master/slave port that allows:

− Downloading of control data to the device externally from the EEPROM or an I2C master

− Controlling other I2C devices

1−2

•Two I2C-selectable, single-ended analog input stereo channels

•Equalization bypass mode

•Single 3.3-V power supply

•Power down without reloading the coefficients

•Sampling rates of 32 kHz, 44.1 kHz, or 48 kHz

•Master clock frequency of 256fSor 512fS

•Can have crystal input to replace MCLK. Crystal input frequency is 256fS.

•Six GPI terminals for volume, bass, treble up/down control, mute, and selection of equalization filters

1.3 Functional Block Diagram

Figure 1−1 is a block diagram showing the major functions of the TAS3002.

1−3

Control

PWR_DN

TEST

AINRP

AINRM

AINLM

AINLP

24-Bit

Stereo

ADC

RINA

RINB

AINRM

AINRP

AINLM

AINLP

LINA

LINB

Control

CS1

SDA

SCL

Controller

GPI0

GPI1

GPI2

GPI3

GPI4

GPI5

24-Bit

Stereo DAC

CAP_PLL

MCLK

XTALO

MCLKO

CLKSEL

SDIN2

SDIN1

SDATA

Control

LRCLK/O

SCLK/O

SDOUT1

L+R SDOUT2

32-Bit Audio Signal

Processor

AOUTL

VCOM

AOUTR

L+R

R32-Bit Audio Signal

Processor

OSC/CLK

Select PLL

Reference

Voltage Supplies

Analog Supplies

Digital

IFM/S

RESET

INPA

ALLPASS

XTALI/

AVSS(REF)

VRFILT

AVDD

AVSS

VREFM

DVDD

DVSS

VREFP

I2C

SDOUT0

Figure 1−1. TAS3002 Block Diagram

1−4

1.4 Terminal Assignments

Figure 1−2 shows the terminal locations on the package outline, along with the signal name assigned to each

terminal.

14 15

AVDD

GPI5

GPI4

GPI3

GPI2

GPI1

GPI0

ALLPASS

SDOUT1

SDOUT0

LINA

VRFILT

AVSS(REF)

AVSS

INPA

RESET

CS1

PWR_DN

TEST

CAP_PLL

CLKSEL

MCLKO

17 18 19 20

AINRM

AINRP

AOUTR

VCOM

47 46 45 44 4348 42

LINB

AINLP

AINLM

40 39 3841

21 22 23 24

AOUTL

RINA

RINB

PACKAGE

(TOP VIEW)

XTALI/MCLK

XTALO

SCL

SDA

DVDD

DVSS

LRCLK/O

SCLK/O

IFM/S

SDIN1

SDIN2

SDOUT2

REFM

VREFP

Figure 1−2. TAS3002 Terminal Assignments

1.5 Terminal Functions

Table 1−1 lists the terminals in alphanumeric order by signal name, along with the terminal number, terminal type,

and a description of the terminal function.

Table 1−1. TAS3002 Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

AINLM 46 I ADC left channel analog input (antialias capacitor)

AINLP 47 I ADC left channel analog input (antialias capacitor)

AINRM 43 I ADC right channel analog input (antialias capacitor)

AINRP 42 I ADC right channel analog input (antialias capacitor)

ALLPASS 27 I Logic high bypasses equalization filters

AOUTL 39 O Left channel analog output

AOUTR 37 O Right channel analog output

AVDD 35 I Analog power supply (3.3 V)

AVSS 4 I Analog voltage ground

AVSS(REF) 3 I Analog ground voltage reference

1−5

Table 1−1. TAS3002 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

CAP_PLL 10 I Loop filter for internal phase-locked loop (PLL)

CLKSEL 11 ILogic low selects 256fS; logic high selects 512fSMCLK

CS1 7 I I2C address bit A0; low = 68h, high = 6Ah

DVDD 17 I Digital power supply (3.3 V)

DVSS 18 I Digital ground

GPI0

GPI1

GPI2

GPI3

GPI4

GPI5

ISwitch input terminals

IFM/S 21 I Digital audio I/O control (low = input; high = output)

INPA 5 O Low when analog input A is selected (will sink 4 mA)

LINA 1 I Left channel analog input 1

LINB 48 I Left channel analog input 2

LRCLK/O 19 I/O Left/right clock input/output (output when IFM/S is high)

MCLKO 12 O MCLK output for slave devices

NC 34 No connection; Can be used as a printed circuit board routing channel

NC 36 No connection; Can be used as a printed circuit board routing channel

PWR_DN 8 I Logic high places the TAS3002 device in power-down mode

RESET 6 I Logic low resets the TAS3002 device to the initial state

RINA 40 I Right channel analog input 1

RINB 41 I Right channel analog input 2

SCL 15 I/O I2C clock connection

SCLK/O 20 I/O Shift (bit) clock input (output when IFM/S is high)

SDA 16 I/O I2C data connection

SDIN1 22 I Serial data input 1

SDIN2 23 I Serial data input 2

SDOUT0 25 O Serial data output from ADC

SDOUT1 26 O Serial data output (from internal audio processing)

SDOUT2 24 O Serial data output (a monaural mix of left and right, before processing)

TEST 9 I Reserved manufacturing test terminal; connect to DVSS

VCOM 38 O Digital-to-analog converter mid-rail supply (decouple with parallel combination of 10-µF and 0.1-µF

capacitors)

VREFM 45 I ADC minus voltage reference

VREFP 44 I ADC plus voltage reference

VRFILT 2 O Voltage reference low pass filter

XTALI/MCLK 13 I Crystal or external MCLK input

XTALO 14 I Crystal input (crystal is connected between terminals 13 and 14)

1−6

2−1

2 Audio Data Formats

2.1 Serial Interface Formats

The TAS3002 device works in master or slave mode.

In the master mode, terminal 21 (IFM/S) is tied high. This activates the master clock (MCLK) circuitry. A crystal can

be connected across terminals 13 (XTALI/MCLK) and 14 (XTALO), or an external, TTL-compatible MCLK can be

connected to XTALI/MCLK. In that case, MCLK is outputs on terminal 12 (MCLKO), with terminals 19 (LRCLK/O) and

20 (SCLK/O) becoming outputs to drive slave devices.

In the slave mode, IFM/S is tied low. LRCLK/O and SCLK/O are inputs and the interface operates as a slave device

requiring externally supplied MCLK, LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options

for selecting the clock rates. If the 512fSMCLK rate is selected, terminal 11 (CLKSEL) is tied high and an MCLK rate

of 512fSmust be supplied. If the 256fSMCLK is selected, CLKSEL is tied low and an MCLK of 256fSmust be supplied.

In both cases, an LRCLK of 64SCLK must be supplied.

•MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.

•If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.

The TAS3002 device is compatible with 13 different serial interfaces. Available interface options are I2S, right justified,

and left justified. Table 2−1 indicates how the 13 options are selected using the I2C bus and the main control register

(MCR, I2C address 01h). All serial interface options at either 16, 18, 20, or 24 bits operate with SCLK at 64fS.

Additionally, the 16-bit mode operates at 32fS.

Table 2−1. Serial Interface Options

MODE MCR BIT (6) MCR BIT (5−4) MCR BIT (1−0) SERIAL INTERFACE

SDIN1, SDIN2, SDOUT1, SDOUT2, AND SDOUT0

0 0 00 00 16-bit, 32fS

1 1 00 00 16-bit, left justified, 64fS

2 1 01 00 16-bit, right justified, 64fS

3 1 10 00 16-bit, I2S, 64fS

4 1 00 01 18-bit, left justified, 64fS

5 1 01 01 18-bit, right justified, 64fS

6 1 10 01 18-bit, I2S, 64fS

7 1 00 10 20-bit, left justified, 64fS

8 1 01 10 20-bit, right justified, 64fS

9 1 10 10 20-bit, I2S, 64fS

10 1 00 11 24-bit, left justified, 64fS

11 1 01 11 24-bit, right justified, 64fS

12 1 10 11 24-bit, I2S, 64fS

Figure 2−1 through Figure 2−3 illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the

different interface protocols.

2−2

2.2 Digital Output Modes

The digital output modes (SDOUT1, SDOUT2, SDOUT0) are described in Sections 2.2.1 through 2.2.3.

2.2.1 MSB-First, Right-Justified, Serial-Interface Format

The normal output mode for the MSB-first, right-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−1

shows the following characteristics of this protocol:

•Left channel is transmitted when LRCLK is high.

•The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK.

•The SDOUT(s) MSB (playback) data is transmitted at the same time as LRCLK edge and captured at the

next rising edge of SCLK.

•If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.

SCLK

LRCLK = fS

MSB LSB

………… …… MSB LSB

……

SDIN

MSB LSB

…… …… MSB LSB

……

Left Channel Right Channel

SDOUT ……

Figure 2−1. MSB-First, Right-Justified, Serial-Interface Format

2−3

2.2.2 I2S Serial-Interface Format

The normal output mode for the I2S serial-interface format is for 16, 18, 20, or 24 bits.

Figure 2−2 shows the following characteristics of this protocol:

•Left channel is transmitted when LRCLK is low.

•SDIN is sampled with the rising edge of SCLK.

•SDOUT is transmitted on the falling edge of SCLK.

•If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.

SCLK

LRCLK = fS

X LSB

SDIN

X LSB

Left Channel Right Channel

SDOUT

……

…

MSB

X LSB

……

…

MSB

Figure 2−2. I2S Serial-Interface Format

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