Texas Instruments LMH0318 Handbuch

Programmer's Guide

SNLU183–September 2015

LMH0318 Programming Guide

This document provides a reference for the LMH0318 Reclocker from a programming model perspective.

It contains detailed information relating to programming and different configuration options. The intended

audience includes software as well as hardware engineers working on the system diagnostics and control

software.

The reader should be familiar with the LMH0318 datasheet (SNLS508). In addition to the LMH0318

datasheet, all other collateral data related to the LMH0318 Reclocker (application notes, models, etc.), are

available on the TI website. Alternatively, contact your local Texas Instruments field sales representative.

Contents

1 Access Methods ............................................................................................................. 2

1.1 Register Programming via SMBus and SPI Interface.......................................................... 2

1.2 Register Programming via SPI.................................................................................... 3

1.3 Register Types ..................................................................................................... 3

2 Initialization Set Up.......................................................................................................... 4

3 Register Command Syntax ................................................................................................ 5

4 Device Configuration ....................................................................................................... 6

4.1 Common Device Configuration ................................................................................... 6

4.2 Common Register Commands ................................................................................... 7

5 Register Tables............................................................................................................. 19

5.1 Global Registers................................................................................................... 19

5.2 Receiver Registers................................................................................................ 23

5.3 CDR Registers..................................................................................................... 29

5.4 Transmitter Registers............................................................................................. 34

List of Tables

1 LMH0318 Register Initialization............................................................................................ 4

2 LMH0318 SMPTE Configuration .......................................................................................... 6

3 SMPTE Data Rate Selection............................................................................................... 9

4 CTLE Boost Setting vs Media Trace Length............................................................................ 10

5 Global Registers............................................................................................................ 19

6 Receiver Registers......................................................................................................... 23

7 CDR Registers.............................................................................................................. 29

8 Transmitter Registers...................................................................................................... 34

SNLU183–September 2015 LMH0318 Programming Guide

Access Methods

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1 Access Methods

Two methods are provided for accessing the LMH0318 Registers:

• Register control via the Serial Management Bus (SMBus)

• Register control via the Serial Parallel Interface (SPI)

In a typical system, either SMBus or SPI access is used to configure and monitor the device status.

Unless specified, the register configurations for SPI and SMBus are the same.

1.1 Register Programming via SMBus and SPI Interface

The LMH0318 internal registers can be accessed through standard SMBus or SPI protocol. The SMBUS

Mode is enabled by setting MODE_SEL pin = LOW (1 kΩto GND). Pins associated with SMBus interface

are:

* ADDR0 (pin #2): Strap pin used to set the SMBus address

* ADDR1 (pin #15): Strap pin used to set the SMBus address

* SDA (pin #14): SMBus data pin

* SCL (pin #3): SMBus clock pin

The SMBus slave address is strapped at power up based on the configuration of the ADDR0 and ADDR1

pins. The state of these two pins are read on power up - after the internal power-on reset signal is de-

asserted. The maximum operating speed supported on the SMBus is 400 kHz.

There are 16 unique SMBus addresses that can be assigned to each device by placing external Resistor

straps on the ADDR0 and ADDR1 pins (pin #2 and #15).

1.1.1 SMBus Slave Address

ADDR0 ADDR1

ADDR0 ADDR1 7-bit SMBus Address (1) 8-bit SMBus Write Address

Binary Binary

1 kΩto GND 1 kΩto GND 00 00 0D 1A

1 kΩto GND 20 kΩto GND 00 01 0E 1C

1 kΩto GND Float 00 10 0F 1E

1 kΩto GND 1 kΩto VDD 00 11 10 20

20 kΩto GND 1 kΩto GND 01 00 11 22

20 kΩto GND 20 kΩto GND 01 01 12 24

20 kΩto GND Float 01 10 13 26

20 kΩto GND 1 kΩto VDD 01 11 14 28

Float 1 kΩto GND 10 00 15 2A

Float 20 kΩto GND 10 01 16 2C

Float Float 10 10 17 2E (2)

Float 1 kΩto VDD 10 11 18 30

1 kΩto VDD 1 kΩto GND 11 00 19 32

1 kΩto VDD 20 kΩto GND 11 01 1A 34

1 kΩto VDD Float 11 10 1B 36

1 kΩto VDD 1 kΩto VDD 11 11 1C 38

(1) Seven (7) bit SMBus addresses need to include LSB equal to zero for write and 1 for read operation. For example, for 7 bit hex

address 0x0D, the controlling program should use I2C hex address 0x1A to write and 0X1B to read. This is true for other

addresses as well.

(2) Default SMBus Address

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Access Methods

1.2 Register Programming via SPI

Alternatively, when MODE_Sel is pulled high with 1 kΩ-resistor, the SPI interface is used for device

configuration. Pins associated with the SPI interface are:

* MOSI: Master Output, Slave input (pin#4)

* MISO: Master Input, Slave Output (pin#15)

* SS_N: Slave Select active low (pin#2)

* SPI_SCK: Serial clock output from master (pin#3)

The maximum operating speed supported on the SPI bus is 20 MHz.

1.3 Register Types

The LMH0318 register set is divided into four groups:

• Global Registers- These registers are divided into share and channel registers. Share register define

LMH0318 ID, revision, enabling shared registers. Channels registers are feature specific such as

interrupt status or interrupt mask

• Receiver Registers- These registers are associated with input stage of the device - equalizer boost

setting, signal detect levels and input mux selection.

• Clock Data Recovery (CDR) Registers- These registers control CDR state machine, Eye Opening

Monitor (EOM), and configuration.

• Transmitter Registers- These registers configure output multiplexers and output parameters for OUT0

and OUT1.

SNLU183–September 2015 LMH0318 Programming Guide

Initialization Set Up

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2 Initialization Set Up

After power up or register reset write the initialization sequences:

Table 1. LMH0318 Register Initialization

DESCRIPTION ADDRESS [Hex] VALUE [Hex]

Enable Channel Registers 0xFF 0x04

Enable Full Temperature Range 0x16 0x25

0x3E 0x00

Initialize CDR State Machine Control 0x55 0x02

0x6A 0x00

Restore media CTLE Setting 0x03 xx

Reset CDR 0x0A 0x5C

Release Reset 0x0A 0x50

See LMH0318 Register Initialization for detailed register programming

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3 Register Command Syntax

Unless otherwise specified, the settings below apply to both SMBus and SPI register programming.

Operations are read-modify-write. This requires the register to be read first and modified by applying the

specific bit mask.

Command Syntax:

RAW Register Register Register Mask //Comments

Address Content

RAW: This defines a Read/Write command

//: Text comment

Example: RAW In this example, we are setting reg 0x80[0] = 1'b to power down OUT0.

80 01 01 0x80[7:1] are not modified since mask = 0x01

RAR Register Register Register Mask //Comments

Address Content

RAR: Read Only Command

being read

//: Characters following // are text comments

Example: RAR Read 0xE2[4] and check if bit 4 is set

E2 10 10

●When using SMBus or SPI interface, the host controller may need to set over-ride bit prior to setting

the control bits of a register

●It is recommended to issue CDR Reset and Release after changing register settings that alters CDR

state machine

●See Register Tables for further details on register bit definitions

SNLU183–September 2015 LMH0318 Programming Guide

Device Configuration

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4 Device Configuration

The following sections provide guidance for programming the LMH0318 for certain common applications.

Throughout the rest of the document, macro examples are given to setup the device for different

configurations and settings.

4.1 Common Device Configuration

The LMH0318 supports SMPTE data rates. Once configured for SMPTE application, the LMH0318 can be

optioned to lock to a selection of data rates and report lock status. The following is an example of common

Table 2. LMH0318 SMPTE Configuration

COMMAND REGISTER VALUE MASK //Comments

//Initialization sequence

RAW FF 04 07 //Select Channel Registers

RAW 16 25 FF //Enable Full Temperature Range

RAW 3E 00 80 //Initialize CDR State Machine Control

RAW 55 02 02

RAW 6A 00 FF

RAW 03 XX FF //Use the desired CTLE settings. See CTLE Test Mode to determine the

CTLE setting

RAW 0A 0C 0C //Reset CDR

RAW 0A 00 0C //Release CDR reset

//In default mode, the LMH0318 automatically locks to different SMPTE

and ST-2082/1 data rates

RAR 1 1 1 //Read LOS of IN0

//Assuming signal is present on IN0, enable IN0 to 75 ΩOUT0 and power

RAW 31 1 3 down 50 ΩOUT1

RAW 2F 00 C0 //Default SMPTE is enabled

RAW 0A 0C 0C //Reset CDR

RAW 0A 00 0C //Release CDR Reset

RAR 02 18 18 //If reg 0x02[4:3] = 11'b, CDR locked

RAW 0C 30 F0 //Setup register 0x0C to enable reg 0x02 to read the VCO divider settings

RAR 02 38 38 //0x02[5:3] Indicates lock rates

RAW 0C 00 F0 //Setup register 0x0C to enable reg 0x02 to read lock indication

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Device Configuration

4.2 Common Register Commands

The followings macros specify register settings for common operations.

4.2.1 Enable Channel Control

In default mode, the shared registers are enabled. To change any channel specific parameter, input

selection, Eye Opening Monitor, Horizontal Eye Opening (HEO), or Vertical Eye Opening (VEO), channel

control must first be enabled as follows:

RAW FF 04 07 //Select Channel Registers

Note: Share register 0xFF can be written/read all the time and does not require selection of share register

bank.

4.2.2 LMH0318 Reset Registers

The LMH0318 has two reset functions: CDR State Machine Reset and Register Reset.

4.2.2.1 LMH0318 CDR State Machine Reset

This operation should be done after changing any of the channel registers.

RAW FF 04 07 //Select Channel Registers

RAW 0A 0C 0C //Reset for the new settings to take place

RAW 0A 00 0C //Release CDR Reset

4.2.2.2 LMH0318 Register Reset

Restore registers default settings:

RAW FF 04 07 //Select Channel Registers

RAW 00 04 04 //Reset Channel Registers

RAW FF 00 07 //Select shared registers

RAW E2 01 0F //Enable Clock Data Recovery (CDR) State Machine

RAR E2 10 10 //Wait until bit 4 set

RAW FF 04 07 //Select Channel Register

Note: LMH0318 Register Initialization must be done after issuing Register Reset

SNLU183–September 2015 LMH0318 Programming Guide

Device Configuration

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4.2.2.3 LMH0318 Register Initialization

After power up, ENABLE pin transition from low to high, or LMH0318 Register Reset write the following

RAW FF 04 07 //Select Channel Registers

RAW 16 25 FF //Enable Full Temperature Range

RAW 3E 00 80 //Initialize CDR State Machine Control

RAW 55 02 02

RAW 6A 00 FF

RAW 03 XX FF //Use the desired CTLE settings. See CTLE Test Mode to determine the CTLE

setting

RAW 0A 0C 0C //Reset CDR

RAW 0A 00 0C //Release CDR reset

4.2.3 Force Power Down

The ENABLE pin (#6) can be used to force the LMH0318 in power down. Additionally, the LMH0318

powers down when there is loss of signal (selected channel Signal Detect is not asserted). There could be

a need to power down the device even when there is active signal. This could be achieved either by

disabling ENABLE pin or forcing the signal detect de-asserted and thus powering down the selected

channel.

To force IN0 signal detect off:

RAW FF 04 07 //Select Channel Registers

RAW 14 40 C0 //Force Signal Detect Off for IN0

To force IN1 signal detect off:

RAW FF 04 07 //Select Channel Registers

RAW 15 40 C0 //Force Signal Detect Off for IN1

After forcing signal detect off, the controlling program may need to enable the signal detect on IN0 or IN1

(normal operation):

RAW FF 04 07 //Select Channel Registers

RAW 14 00 C0 //IN0 Signal Detect Normal Operation

RAW FF 04 07 //Initialize CDR State Machine Control

RAW 15 00 C0 //IN1 Signal Detect Normal Operation

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Device Configuration

4.2.4 Selective Data Rate Lock

In default mode, the LMH0318 is configured to automatically lock to all SMPTE data rates. The LMH0318

can be configured to lock to certain data rate or restricts the dividers so the CDR can only lock to the

desired data rate. This enables faster lock time.

Table 3. SMPTE Data Rate Selection

1: Enable CDR Lock to 270Mbps

Reg 0xA0[4] 0: Disable CDR Lock to 270Mbps

1: Enable CDR Lock to 1.485/1.4835 Gbps

Reg 0xA0[3] 0: Disable CDR Lock to 1.485/1.4835 Gbps

1: Enable CDR Lock to 2.97/2.967 Gbps

Reg 0xA0[2] 0: Disable CDR Lock to 2.97/2.967 Gbps

For example, to enable lock to 3G, HD, and 270 Mbps, the following script can be used:

RAW FF 04 07 //Select Channel Registers

RAW A0 1C 1F //Enable Lock to ST 424, ST 292, and ST 259 only

RAW 0A 0C 0C //Initialize CDR State Machine Control

RAW 0A 00 0C //Release CDR Reset

Alternatively, the following sequence can be used to disable lock to certain data rates (for example 3G):

RAW FF 04 07 //Select Channel Registers

RAW A0 00 04 //Disable Lock to 3G

RAW 0A 0C 0C //Reset CDR

RAW 0A 00 0C //Release CDR Reset

4.2.5 Check Status of LOS (Loss Of Signal) on Input 1 or Input 0

The LMH0318 has two inputs and each input has its own signal detector. Based on signal detect status

and input channel selected, the device automatically goes into power down. For example, if IN0 is

selected and there is no signal on IN0 then the device, CDR and output drivers go into power down. The

following macro checks the status of the signal detects on IN0 or IN1:

RAW FF 04 07 //Select Channel Registers

RAW 1 01 01 //Read LOS of IN0

RAW 1 02 02 //Read LOS of IN1

SNLU183–September 2015 LMH0318 Programming Guide

Device Configuration

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4.2.6 Input/Output Selection

The LMH0318 has 2:1 Mux on the Input and 1:2 Fan out on the output. Different input and output

configuration can be selected. The following settings allow these different configurations:

RAW FF 04 07 //Select Channel Registers

RAW 31 00 03 //Set to 00: Enable IN0 to OUT0 and OUT1

RAW FF 04 07 //Select Channel Registers

RAW 31 01 03 //Set to 01: Enable IN0 to OUT0 (OUT1 is powered down)

RAW FF 04 07 //Select Channel Registers

RAW 31 02 03 //Set to 10: Enable IN1 to OUT1 (OUT0 is powered down)

RAW FF 04 07 //Select Channel Registers

RAW 31 03 03 //Set to 11: Enable IN1 to OUT0 and OUT1

4.2.7 CTLE Test Mode

The LMH0318 Continuous Time Linear Equalizer compensates for the high frequency loss caused by the

transmission media. Deterministic jitter due to the ISI (Inter Symbol Interference) caused by the media can

be equalized by the LMH0318 CTLE.

In the default mode, the CTLE boost is determined by register 0x03. The default value of 0x80'h equalizes

10-15 inches PCB FR4 trace loss. The user may change register 0x03 to enable different boost settings

for different media loss characteristics . Table 4 shows recommended CTLE boost settings vs different

media trace length.

Table 4. CTLE Boost Setting vs Media Trace Length

FR4 TRACE SDD21 (dB) WRITE BOOST SETTING BOOST SETTING

LENGTH REGISTER

@ 6 GHz VALUE @ 3 GHz (dB) @ 6 GHz (dB)

(Inches)

1 -1.5 0x03 0x00 4.9 5.8

5 -7.5 0x03 0x00 4.9 5.8

10 -10.5 0x03 0x10 7.7 10.2

15 -15.5 0x03 0x50 10.9 15.3

20 -19.5 0x03 0x50 10.9 15.3

25 -24.5 0x03 0x60 13.2 17

30 -27.5 0x03 0x94 16.2 21.8

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