Texas Instruments TMS320DM355 Bedienungsanleitung

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PRODUCT PREVIEW

1 TMS320DM355 Digital Media System-on-Chip (DMSoC)

1.1 Features

TMS320DM355Digital Media System-on-Chip (DMSoC)

SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007

encoder•High-Performance Digital MediaSystem-on-Chip •External Memory Interfaces (EMIFs)– 216- and 270-MHz ARM926EJ-S Clock Rate – DDR2 and mDDR SDRAM 16-bit wide EMIFWith 256 MByte Address Space (1.8-V I/O)– Fully Software-Compatible With ARM9

– Asynchronous16-/8-bit Wide EMIF (AEMIF)•ARM926EJ-S Core

•Flash Memory Interfaces– Support for 32-Bit and 16-Bit (Thumb Mode)

– NAND (8-/16-bit Wide Data)Instruction Sets

– OneNAND(16-bit Wide Data)– DSP Instruction Extensions and SingleCycle MAC

•Flash Card Interfaces– ARM Jazelle Technology

– Two Multimedia Card (MMC) / Secure– EmbeddedICE-RT Logic for Real-Time Digital (SD/SDIO)Debug

– SmartMedia•ARM9 Memory Architecture

•Enhanced Direct-Memory-Access (EDMA)– 16K-Byte Instruction Cache Controller (64 Independent Channels)– 8K-Byte Data Cache

•USB Port with Integrated 2.0 High-Speed PHYthat Supports– 32K-Byte RAM

– USB 2.0 Full and High-Speed Device– 8K-Byte ROM

– USB 2.0 Low, Full, and High-Speed Host– Little Endian

•Three 64-Bit General-Purpose Timers (each•Video Processing Subsystem

configurable as two 32-bit timers)– Front End Provides:

•One 64-Bit Watch Dog Timer•Hardware IPIPE for Real-Time ImageProcessing •Three UARTs (One fast UART with RTS andCTS Flow Control)•CCD and CMOS Imager Interface

•Three Serial Port Interfaces (SPI) each with•14-Bit Parallel AFE (Analog Front End)

two Chip-SelectsInterface Up to 67.5 MHz

•One Master/Slave Inter-Integrated Circuit•Glueless Interface to Common Video

C) Bus™Decoders

•BT.601/BT.656 Digital YCbCr 4:2:2 •Two Audio Serial Port (ASP)(8-/16-Bit) Interface

– I2S and TDM I2S•Histogram Module

– AC97 Audio Codec Interface•Resize Engine

– S/PDIF via Software– Resize Images From 1/16x to 8x

– Standard Voice Codec Interface (AIC12)– Separate Horizontal/Vertical Control

– SPI Protocol (Master Mode Only)– Two Simultaneous Output Paths

•Four Pulse Width Modulator (PWM) Outputs– Back End Provides:

•Four RTO (Real Time Out) Outputs•Hardware On-Screen Display (OSD)

•Up to 104 General-Purpose I/O (GPIO) Pins•Composite NTSC/PAL video encoder

(Multiplexed with Other Device Functions)output

•On-Chip ARM ROM Bootloader (RBL) to Boot•8-/16-bit YCC and Up to 18-Bit RGB666

From NAND Flash, MMC/SD, or UARTDigital Output

•Configurable Power-Saving Modes•BT.601/BT.656 Digital YCbCr 4:2:2

•Crystal or External Clock Input (typically(8-/16-Bit) Interface

24 MHz or 36 MHz)•Supports digital HDTV (720p/1080i)

•Flexible PLL Clock Generatorsoutput for connection to external

•Debug Interface Support

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this document.I

C-bus is a trademark of Texas Instruments.Windows is a trademark of Microsoft.All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the

Copyright © 2007–2007, Texas Instruments Incorporatedformative or design phase of development. Characteristic data andother specifications are design goals. Texas Instruments reservesthe right to change or discontinue these products without notice.

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PRODUCT PREVIEW

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007

– IEEE-1149.1 (JTAG) •337-Pin Ball Grid Array (BGA) PackageBoundary-Scan-Compatible (ZCE Suffix), 0.65-mm Ball Pitch– ETB (Embedded Trace Buffer) with

•90nm Process Technology4K-Bytes Trace Buffer memory

•3.3-V and 1.8-V I/O, 1.3-V Internal– Device Revision ID Readable by ARM

2TMS320DM355 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback

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1.2 Description

TMS320DM355Digital Media System-on-Chip (DMSoC)

SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007

The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IPsecurity cameras, 4-channel digital video recorders, video door bell application, and other low costportable digital video applications. Designed to offer portable video designers and manufacturers theability to produce affordable portable digital video solutions with high picture quality, the DM355 combineshigh performance, high quality, low power consumption at a very low price point. The DM355 also enablesseamless interface to most additional external devices required for a complete digital cameraimplementation. The interface is flexible enough to support various types of CCD and CMOS sensors,signal conditioning circuits, power management, DDR/mDDR memory, SRAM, NAND, shutter, Iris andauto-focus motor controls, etc.

The processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core thatperforms 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core usespipelining so that all parts of the processor and memory system can operate continuously. The ARM coreincorporates:

•A coprocessor 15 (CP15) and protection module•Data and program Memory Management Units (MMUs) with table look-aside buffers.•Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtualindex virtual tag (VIVT).

DM355 performance is enhanced by its MPEG/JPEG co-processor. The MPEG/JPEG co-processorperforms the computational operations required for image processing; JPEG compression and MPEG1,2,4video and imaging standards.

The device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:•A Video Processing Front-End (VPFE)•A Video Processing Back-End (VPBE)

The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBEprovides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.

The DM355 peripheral set includes:•An inter-integrated circuit (I2C) Bus interface•Two audio serial ports (ASP)•Three 64-bit general-purpose timers each configurable as two independent 32-bit timers•A 64-bit watchdog timer•Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generationmodes, multiplexed with other peripherals•Three UARTs with hardware handshaking support on one UART•Three serial port Interfaces (SPI)•Four pulse width modulator (PWM) peripherals•Four real time out (RTO) outputs•Two Multi-Media Card / Secure Digital (MMC/SD) interfaces•A USB 2.0 full and high-speed device and host interface•Two external memory interfaces:– An asynchronous external memory interface (AEMIF) for slower memories/peripherals such asNAND and OneNAND,– A high speed synchronous memory interface for DDR2/mDDR.

For software development support the has a complete set of ARM development tools which include: Ccompilers, assembly optimizers to simplify programming and scheduling, and a Windows™ debuggerinterface for visibility into source code execution.

Submit Documentation Feedback TMS320DM355 Digital Media System-on-Chip (DMSoC) 3

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PRODUCT PREVIEW

1.3 Functional Block Diagram

Peripherals

64bit DMA/Data Bus

JTAG 24 MHz 27 MHz

(optional)

CCD/

CMOS

Module

DDR2/MDDR 16

CLOCK

PLL

CLOCK ctrl

PLLs

JTA

JTAG

I/F

Clocks

ARM

z )

ARM926EJ-S_Z8

I-cach

16 K

l-cache

16KB

32 K

RAM

32KB

D-cach

D-cache

8KB

8 K

ROM

8KB

CCD

CCDC

DMA / Data and configuration bus

DMA/Data and configuration bus

DDR

z )

DDR

controller

DLL/

PHY

16 bit

32bit Configuration Bus

IPIP

IPIPE

VPBE

Vide

Encod

Video

Encoder

10b

DAC OS

OSD

ARM

ARM INTC

Enhanced

channels

3PCC /TC

(100 MHz

Enhanced DMA

64 channels

Composite video

Digital RGB/YUV

Nand /

Nand/SM/

Async/One Nand

(EMIF2.3)

USB 2.0

USB2.0 PHY

Speaker

microphone

LD /

ASP (2x)

LD/CM

Buffer Logic

VPSS

MMC/SD (x2)

SPI I/F (x3)

UART (x3)

I2C

Timer/

WDT (x4 - 64)

GIO

PWM (x4)

RTO

VPFE

Enhanced

channels

3PCC /TC

(100 MHz

MPEG/JPEG

Coprocessor

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007

Figure 1-1 shows the functional block diagram of the DM355 device.

Figure 1-1. Functional Block Diagram

TMS320DM355 Digital Media System-on-Chip (DMSoC)4Submit Documentation Feedback

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PRODUCT PREVIEW

Contents

TMS320DM355Digital Media System-on-Chip (DMSoC)

SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007

1 TMS320DM355 Digital Media System-on-Chip 4.2 Recommended Operating Conditions ............... 92(DMSoC) ................................................... 1

4.3 Electrical Characteristics Over RecommendedRanges of Supply Voltage and Operating Case1.1 Features .............................................. 1

Temperature (Unless Otherwise Noted) ............ 931.2 Description ............................................ 3

5 Peripheral Information and Electrical1.3 Functional Block Diagram ............................ 4

Specifications ........................................... 942 Device Overview ......................................... 6

5.1 Parameter Information Device-Specific Information 942.1 Device Characteristics ................................ 6

5.2 Recommended Clock and Control Signal Transition2.2 Memory Map Summary ............................... 7

Behavior ............................................. 962.3 Pin Assignments ...................................... 9

5.3 Power Supplies ...................................... 962.4 Pin Functions ........................................ 13

5.4 Reset ................................................ 982.5 Pin List .............................................. 36

5.5 Oscillators and Clocks ............................... 992.6 Device Support ...................................... 55

5.6 General-Purpose Input/Output (GPIO) ............. 1043 Detailed Device Description .......................... 59

5.7 External Memory Interface (EMIF) ................. 1063.1 ARM Subsystem Overview .......................... 59

5.8 MMC/SD ........................................... 1133.2 ARM926EJ-S RISC CPU ............................ 60

5.9 Video Processing Sub-System (VPSS) Overview .1153.3 Memory Mapping .................................... 62

5.10 USB 2.0 ............................................ 1273.4 ARM Interrupt Controller (AINTC) ................... 63

5.11 Universal Asynchronous Receiver/Transmitter(UART) ............................................. 1293.5 Device Clocking ..................................... 65

5.12 Serial Port Interface (SPI) .......................... 1313.6 PLL Controller (PLLC) ............................... 73

5.13 Inter-Integrated Circuit (I2C) ....................... 1343.7 Power and Sleep Controller (PSC) .................. 77

5.14 Audio Serial Port (ASP) ............................ 1373.8 System Control Module ............................. 77

5.15 Timer ............................................... 1443.9 Pin Multiplexing ...................................... 78

5.16 Pulse Width Modulator (PWM) ..................... 1453.10 Device Reset ........................................ 79

5.17 Real Time Out (RTO) .............................. 1473.11 Default Device Configurations ....................... 80

5.18 IEEE 1149.1 JTAG ................................ 1483.12 Device Boot Modes ................................. 83

6 Revision History ...................................... 1513.13 Power Management ................................. 85

7 Mechanical Data ....................................... 1533.14 64-Bit Crossbar Architecture ........................ 87

7.1 Thermal Data for ZCE ............................. 1533.15 MPEG/JPEG Overview .............................. 90

7.1.1 Packaging Information ............................. 1534 Device Operating Conditions ........................ 914.1 Absolute Maximum Ratings Over Operating CaseTemperature Range(Unless Otherwise Noted) .......................... 91

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PRODUCT PREVIEW

2 Device Overview

2.1 Device Characteristics

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007

Table 2-1 provides an overview of the DMSoC. The table shows significant features of the device,including the peripherals, capacity of on-chip RAM, ARM operating frequency, the package type with pincount, etc.

Table 2-1. Characteristics of the Processor

HARDWARE FEATURES DM355

DDR2 / mDDR Memory Controller DDR2 / mDDR (16-bit bus width)Asynchronous (8/16-bit bus width)Asynchronous EMIF (AEMIF)

RAM, Flash (NAND, OneNAND)Two MMC/SDFlash Card Interfaces

One SmartMedia/xD

64 independent DMA channelsEDMA

Eight EDMA channelsThree 64-Bit General Purpose (eachconfigurable as two separate 32-bitTimers

timers)Peripherals

One 64-Bit Watch DogNot all peripherals pins are

Three (one with RTS and CTS flowavailable at the same time

UART

control)(For more detail, see theDevice Configuration

Three (each supports two slaveSPIsection).

devices)I

C One (Master/Slave)Audio Serial Port [ASP] Two ASPGeneral-Purpose Input/Output Port Up to 104Pulse width modulator (PWM) Four outputsOne Input (VPFE)Configurable Video Ports

One Output (VPBE)High, Full Speed DeviceUSB 2.0

High, Full, Low Speed HostARMOn-Chip CPU Memory Organization 16-KB I-cache, 8-KB D-cache,32-KB RAM, 8-KB ROMJTAG BSDL_ID JTAGID register (address location: 0x01C4 0028) 0x0B73B01FCPU Frequency (Maximum) MHz ARM 216 MHz and 270 MHzCore (V) 1.3 VVoltage

I/O (V) 3.3 V, 1.8 VReference frequency options 24 MHz (typical), 36 MHzPLL Options

Configurable PLL controller PLL bypass, programmable PLLBGA Package 13 x 13 mm 337-Pin BGA (ZCE)Process Technology 90 nmProduct Preview (PP),Product Status

(1)

Advance Information (AI), PPor Production Data (PD)

(1) PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and otherspecifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

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2.2 Memory Map Summary

TMS320DM355Digital Media System-on-Chip (DMSoC)

SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007

Table 2-3 shows the memory map address ranges of the device. Table 2-3 depicts the expanded map ofthe Configuration Space (0x01C0 0000 through 0x01FF FFFF). The device has multiple on-chip memoriesassociated with its processor and various subsystems. To help simplify software development a unifiedmemory map is used where possible to maintain a consistent view of device resources across all busmasters. The bus masters are the ARM, EDMA, USB, and VPSS.

Table 2-2. DM355 Memory Map

Start Address End Address Size (Bytes) ARM EDMA USB VPSSMem Map Mem Map Mem Map Mem Map

0x0000 0000 0x0000 3FFF 16K ARM RAM0

(Instruction)0x0000 4000 0x0000 7FFF 16K ARM RAM1

Reserved Reserved(Instruction)0x0000 8000 0x0000 FFFF 32K ARM ROM(Instruction)

- only 8K used0x0001 0000 0x0001 3FFF 16K ARM RAM0 (Data) ARM RAM0 ARM RAM00x0001 4000 0x0001 7FFF 16K ARM RAM1 (Data) ARM RAM1 ARM RAM10x0001 8000 0x0001 FFFF 32K ARM ROM (Data) ARM ROM ARM ROM- only 8K used0x0002 0000 0x000F FFFF 896K Reserved0x0010 0000 0x01BB FFFF 26M0x01BC 0000 0x01BC 0FFF 4K ARM ETB Mem0x01BC 1000 0x01BC 17FF 2K ARM ETB Reg Reserved0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher Reserved0x01BC 1900 0x01BC FFFF 59136 Reserved0x01BD 0000 0x01BF FFFF 192K0x01C0 0000 0x01FF FFFF 4M CFG Bus CFG Bus

ReservedPeripherals Peripherals0x0200 0000 0x09FF FFFF 128M ASYNC EMIF (Data) ASYNC EMIF (Data)0x0A00 0000 0x11EF FFFF 127M - 16K0x11F0 0000 0x11F1 FFFF 128K Reserved Reserved0x11F2 0000 0x1FFF FFFF 141M-64K0x2000 0000 0x2000 7FFF 32K DDR EMIF Control DDR EMIF ControlRegs Regs0x2000 8000 0x41FF FFFF 544M-32K Reserved0x4200 0000 0x49FF FFFF 128M Reserved AEMIF - shadow0x4A00 0000 0x7FFF FFFF 864M Reserved0x8000 0000 0x8FFF FFFF 256M DDR EMIF DDR EMIF DDR EMIF DDR EMIF0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved Reserved Reserved

Table 2-3. DM355 ARM Configuration Bus Access to Peripherals

Address Accessibility

Region Start End Size ARM EDMA

EDMA CC 0x01C0 0000 0x01C0 FFFF 64K √ √EDMA TC0 0x01C1 0000 0x01C1 03FF 1K √ √EDMA TC1 0x01C1 0400 0x01C1 07FF 1K √ √Reserved 0x01C1 8800 0x01C1 9FFF 6K √ √Reserved 0x01C1 A000 0x01C1 FFFF 24K √ √UART0 0x01C2 0000 0x01C2 03FF 1K √ √

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PRODUCT PREVIEW

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007

Table 2-3. DM355 ARM Configuration Bus Access to Peripherals (continued)

Address Accessibility

UART1 0x01C2 0400 0x01C2 07FF 1K √ √Timer4/5 0x01C2 0800 0x01C2 0BFF 1K √ √Real-time out 0x01C2 0C00 0x01C2 0FFF 1K √ √I2C 0x01C2 1000 0x01C2 13FF 1K √ √Timer0/1 0x01C2 1400 0x01C2 17FF 1K √ √Timer2/3 0x01C2 1800 0x01C2 1BFF 1K √ √WatchDog Timer 0x01C2 1C00 0x01C2 1FFF 1K √ √PWM0 0x01C2 2000 0x01C2 23FF 1K √ √PWM1 0x01C2 2400 0x01C2 27FF 1K √ √PWM2 0x01C2 2800 0x01C2 2BFF 1K √ √PWM3 0x01C2 2C00 0x01C2 2FFF 1K √ √System Module 0x01C4 0000 0x01C4 07FF 2K √ √PLL Controller 0 0x01C4 0800 0x01C4 0BFF 1K √ √PLL Controller 1 0x01C4 0C00 0x01C4 0FFF 1K √ √Power/Sleep Controller 0x01C4 1000 0x01C4 1FFF 4K √ √ARM Interrupt Controller 0x01C4 8000 0x01C4 83FF 1K √ √USB OTG 2.0 Regs / RAM 0x01C6 4000 0x01C6 5FFF 8K √ √SPI0 0x01C6 6000 0x01C6 67FF 2K √ √SPI1 0x01C6 6800 0x01C6 6FFF 2K √ √GPIO 0x01C6 7000 0x01C6 77FF 2K √ √SPI2 0x01C6 7800 0x01C6 FFFF 2K √ √

VPSS Subsystem 0x01C7 0000 0x01C7 FFFF 64K √ √VPSS Clock Control 0x01C7 0000 0x01C7 007F 128 √ √Hardware 3A 0x01C7 0080 0x01C7 00FF 128 √ √Image Pipe (IPIPE) Interface 0x01C7 0100 0x01C7 01FF 256 √ √On Screen Display 0x01C7 0200 0x01C7 02FF 256 √ √High Speed Serial IF 0x01C7 0300 0x01C7 03FF 256 √ √Video Encoder 0x01C7 0400 0x01C7 05FF 512 √ √CCD Controller 0x01C7 0600 0x01C7 07FF 256 √ √VPSS Buffer Logic 0x01C7 0800 0x01C7 08FF 256 √ √Reserved 0x01C7 0900 0x01C7 09FF 256 √ √Image Pipe (IPIPE) 0x01C7 1000 0x01C7 3FFF 12K √ √Reserved 0x01CC 0000 0x01CD FFFF 128K √ √Multimedia / SD 1 0x01E0 0000 0x01E0 1FFF 8K √ √ASP0 0x01E0 2000 0x01E0 3FFF 8K √ √ASP1 0x01E0 4000 0x01E0 5FFF 8K √ √UART2 0x01E0 6000 0x01E0 63FF 1K √ √Reserved 0x01E0 6400 0x01E0 FFFF 39K √ √ASYNC EMIF Control 0x01E1 0000 0x01E1 0FFF 4K √ √Multimedia / SD 0 0x01E1 1000 0x01E1 FFFF 60K √ √Reserved 0x01E2 0000 0x01FF FFFF 1792K √ √ASYNC EMIF Data (CE0) 0x0200 0000 0x03FF FFFF 32M √ √ASYNC EMIF Data (CE1) 0x0400 0000 0x05FF FFFF 32M √ √Reserved 0x0A00 0000 0x0BFF FFFF 32M √ √Reserved 0x0C00 0000 0x0FFF FFFF 64M √ √

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PRODUCT PREVIEW

2.3 Pin Assignments

2.3.1 Pin Map (Bottom View)

VSSA_PLL2

VDDA33_USB

VDDA13_USB

VSS

CIN2

VREF

CIN3CIN0

VDDA_PLL2

VSS

LCD_OE

FIELDVCLK

VSS

CVDD

VSYNCEXTCLKVFB

VDD_VOUT

HSYNCCOUT0COUT1TVOUT

TDOEMU0EMU1

VSS_USB

USB_VBUS

COUT2COUT3IOUT

TDITMS

VSS_USB

USB_IDCOUT4

VSS

TRST

VSS_USB_REF

USB_R1

VDDD13_USB

USB_DRV

VBUS

CVDD

YOUT7COUT5

MXO1

VSS

VSS_USB

VDDA33_USB_

PLL

VSS

YOUT5YOUT4YOUT0

MXI1

VSS

USB_DPUSB_DM

VSS

YOUT6YOUT2

CVDD

VSS

IBIAS

VSS

COUT6

COUT7

YOUT3

YOUT1

RSV01

VDD

TMS320DM355Digital Media System-on-Chip (DMSoC)

SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions inthe smallest possible package. Pin multiplexing is controlled using a combination of hardwareconfiguration at device reset and software programmable register settings.

Figure 2-1 through Figure 2-4 show the pin assignments in four quadrants (A, B, C, and D). Note thatmicro-vias are not required. Contact your TI representative for routing recommendations.

Figure 2-1. Pin Map [Quadrant A]

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DDR_CLK

7654

DDR_A05

DDR_A02

VDDR_A07DDR_A04DDR_A00

UVSS

TPCLK

DDR_A11DDR_A09DDR_A08

VSS

DDR_CAS

DDR_BA[2]

DDR_A12DDR_A10DDR_A01

VSS

DDR_BA[0]DDR_BA[1]

DDR_A13DDR_A06

DDR_A03

VSS

DDR_ZNDDR_CSDDR_RAS

VSS

MXO2

VDD_DDR

CVDD

VSS

CAM_WEN_

FIELD

CAM_VDYIN3

VSS

MXI2

VDD_DDR

VDD_VIN

YIN0YIN2YIN4YIN1VSS_MX2

VSS

CVDD

CAM_HDCIN7

RSV05

VSS

VDD_DDR

VSS

YIN5YIN6CIN5

RSV06

RSV04

VSS

VSS_DAC

VDDA18V_DAC

VDD

YIN7CIN4CIN1

VSS

RSV03

VSS

VDD

CVDD

CIN6

VSS

RSV07RSV02

VDD_VIN

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007

Figure 2-2. Pin Map [Quadrant B]

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