Texas Instruments DAC8580 Bedienungsanleitung

User's Guide

SLAU173A–December 2005–Revised November 2009

DAC8580/81 Evaluation Module

This user guide describes the characteristics, operation, and the use of the DAC8580/81 Evaluation

Module. It covers all pertinent areas involved to properly use this EVM board along with the devices that it

supports. The physical printed circuit board (PCB) layout, schematic diagram and circuit descriptions are

included.

Contents

1 EVM Overview ............................................................................................................... 2

2 PCB Design and Performance ............................................................................................ 3

3 EVM Operation .............................................................................................................. 8

4 Using the DAC8581EVM with DXP ..................................................................................... 13

5 Bill of Materials ............................................................................................................. 17

List of Figures

1 DAC8580/81EVM Block Diagram......................................................................................... 3

2 Top Silkscreen............................................................................................................... 4

3 Layer 1 (Top Signal Plane) ................................................................................................ 5

4 Layer 2 (Ground Plane).................................................................................................... 5

5 Layer 3 (Power Plane) ..................................................................................................... 6

6 Layer 4 (Bottom Signal Plane) ............................................................................................ 6

7 Bottom Silkscreen........................................................................................................... 6

8 INL Characteristic Plot for the DAC8581 ................................................................................ 7

9 DNL Characteristic Plot for the DAC8581 ............................................................................... 7

10 DAC8580EVM Default Jumper Setting................................................................................... 9

11 DAC8581EVM Default Jumper Setting................................................................................... 9

12 DAC Output Waveform ................................................................................................... 11

13 MMB0 with DAC8581EVM Installed .................................................................................... 14

14 Loading a DAC8581EVM Configuration................................................................................ 15

15 DAC8581EVM: Frequency/Amplitude and Update Rate Adjustments ............................................. 16

16 DAC Output Update Options............................................................................................. 17

List of Tables

1 DAC8580/81EVM Factory Default Jumper Setting..................................................................... 8

2 Unity Gain Output Jumper Settings..................................................................................... 10

3 Gain of Two Output Jumper Settings................................................................................... 10

4 Jumper Settings for a Gain of Five With Inverted Output............................................................ 10

5 Jumper Setting Function.................................................................................................. 11

6 DAC8581EVM: GPIO Options........................................................................................... 16

7 Output Update Features.................................................................................................. 17

8 DAC8580/81EVM Bill of Materials ...................................................................................... 17

Microsoft, Windows are registered trademarks of Microsoft Corporation.

All other trademarks are the property of their respective owners.

SLAU173A–December 2005–Revised November 2009 DAC8580/81 Evaluation Module

EVM Overview

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1 EVM Overview

This section gives a general overview of the DAC8580/81 Evaluation Module (EVM) and instructions on

setting up and using this evaluation module. Throughout this document, the abbreviation EVM and the

phrase evaluation module are synonymous with the DAC8580/81EVM. Unless otherwise specified,

operation of the DAC8580EVM is identical to the operation of the DAC8581EVM; therefore, the

abbreviation DAC8580/81EVM is used throughout this document.

1.1 Features

This EVM features the DAC8580/81 digital-to-analog converter (DAC). It provides a quick and easy way to

evaluate the functionality and performance of the high-resolution, serial input DAC. The EVM provides the

serial interface header to easily attach to any host microprocessor or TI DSP-based system for

communication.

1.2 Power Requirements

The following sections describe the power requirements of this EVM.

1.2.1 Supply Voltage

The dc power supply for the digital section (DVDD) of the device under test (DUT) installed on this EVM is

selectable between +5 VD and +3.3 VD via the W1 jumper, although the digital pull-up resistors are

permanently tied to +5 VD. The +5-VD source can come from the J5-1 terminal (if installed) or the J6-10

terminal and is referenced to ground through the J5-2 and J6-5 terminals, respectively.

The dc power supply requirements for the analog section (AVDD and AVSS) of the DUT installed on this

EVM is provided by +5 VA that can come from the J5-3 terminal (if installed) or the J6-3 terminal, and -5

VA that can come from J6-4 terminal, respectively. The analog ground is referenced through the J1-2

terminal (if installed) or the J6-6 terminal. The high voltage supply via VCC and VSS is typically ±15 V but

can range from ±4.5 V minimum to ±18 V maximum and connect through the J1-1 and J1-3 terminals,

respectively (if installed), or through the J6-1 and J6-2 terminals. All of the analog power supplies are

referenced to analog ground through the J1-2 and J6-6 terminals.

The VCC supply sources the positive rail of the external output operational amplifier, U2, as well as the

REF02 reference source, U3, and the buffer operational amplifier, U8A. The negative rail of U2 is supplied

by VSS, although U2 also can be selected to be connected to AGND via W5 jumper. The external

operational amplifiers, U2 and U8B, are installed as an option to provide output signal conditioning and for

any other output configurations desired.

CAUTION

To avoid potential damage to the EVM board, ensure that the correct cables

are connected to their respective terminals as labeled on the EVM board.

Stresses above the maximum listed voltage ratings may cause permanent

damage to the device.

1.2.2 Reference Voltage

The externally-generated +5 VDC, via REF02, or +4.096 VDC, via REF3040, precision voltage reference is

jumper selectable via W4. The reference voltage for the DUT can be chosen between the installed

precision reference circuits or user-supplied reference via TP1. The REF02, U3, is the reference source

installed from the factory whereas the REF3040, U4, is optional. Because the REF3040 is pin compatible

with the REF31xx and REF32xx reference family, the user can choose between these wide varieties of

precision references. The REF02 is a 10 ppm/°C with excellent line regulation and stability. The chosen

reference source provides the DAC8580/81 voltage output range. An external reference source of up to

AVDD can be applied to the reference input via TP1 if other than the onboard reference source is desired.

2DAC8580/81 Evaluation Module SLAU173A–December 2005–Revised November 2009

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DAC Module

O utput

Buffe r

Module

VCC

VSS

+3 .3VD

VCC

+5 VD

GND

+5 VA

DAC Out

(J1 )

(J5 )

(J6 )

(P6)

External

Reference

Module

(J2)

(P2)

SCLK

FSYNC

TP 4

VSS

REFIN

+5VD

DIN

(J4)

(P4)

TP 3

W 15

W 5

VSS

AGND

OUT

TP 2

W 1

DAC Module features the DAC8580/81.

+3 .3VD

OSR 1

RSTB

MUTEB

OSR 2

BPB

1 CH

+5 VA

-5VA

TP 1

U 1

-5VA

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PCB Design and Performance

1.3 EVM Basic Functions

This EVM is designed primarily as a functional evaluation platform to test certain functional characteristics

of the DAC8580/81 digital-to-analog converter. Functional evaluation of the installed DAC device can be

accomplished with the use of any microprocessor, TI DSP, or some sort of a signal/waveform generator.

The headers J2 (top side) and P2 (bottom side) are pass-through connectors provided to allow the control

signals and data required to interface a host processor or waveform generator to the DAC8580/81EVM

using a custom-built cable.

The DAC output can be monitored through the J4 header connector. In addition, the DAC output can be

connected to the output operational amplifier, U2, by using a jumper across any of the pins 1-2, 3-4, 5-6,

or 7-8 of the J4 header terminal. The input signal going into the output operational amplifier, U2, must be

configured correctly on the J3 header to achieve the desired output waveform. The output operational

amplifier, U2, is configurable through J3, W5, and W15 for any desired waveform characteristic.

Figure 1 shows a block diagram of the DAC8580/81EVM.

Figure 1. DAC8580/81EVM Block Diagram

2 PCB Design and Performance

This section discusses the layout design of the PCB, describing the physical and mechanical

characteristics of the EVM. It shows the resulting performance of the EVM, which can be compared to the

device specification listed in the data sheet. The list of components used on the module is also included in

this section.

2.1 PCB Layout

The DAC8580/81EVM is designed to demonstrate the performance quality of the installed DAC device

under test (DUT), as specified in the data sheet. To take full advantage of the EVM capabilities, use care

during the schematic design phase to properly select the right components and to build the circuit

correctly. The circuit should include adequate bypassing, identifying and managing the analog and digital

signals, and understanding the component electrical and mechanical attributes.

The main design concern during the layout process is the optimal placement of components and the

proper routing of signals. Place the bypass capacitors as close as possible to the pins, and the analog and

digital signals should be properly separated from each other. In the layout process, carefully consider the

power and ground planes because of their importance. A solid plane is ideally preferred but because of its

greater cost, sometimes a split plane can be used satisfactorily. When considering a split plane design,

SLAU173A–December 2005–Revised November 2009 DAC8580/81 Evaluation Module

PCB Design and Performance

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analyze the component placement and carefully split the board into its analog and digital sections starting

from the device under test. The ground plane plays an important role in controlling the noise and other

effects that otherwise contribute to the error of the DAC output. To ensure that the return currents are

handled properly, route the appropriate signals only in their respective sections, meaning the analog

traces should only lay directly above or below the analog section and the digital traces in the digital

section. Minimize the length of the traces but use the biggest possible trace width allowable in the design.

These design practices can be seen in Figure 2 through Figure 7.

The DAC8580/81EVM board is constructed on a four-layer printed-circuit board (PCB) using a copper-clad

FR-4 laminate material. The PCB has a dimension of 43,1800 mm (1.7000 inch) × 82,5500 mm (3.2000

inch), and the board thickness is 1,5748 mm (0.0620 inch). Figure 2 through Figure 7 show the individual

artwork layers.

Figure 2. Top Silkscreen

Figure 3. Layer 1 (Top Signal Plane)

4DAC8580/81 Evaluation Module SLAU173A–December 2005–Revised November 2009

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PCB Design and Performance

Figure 4. Layer 2 (Ground Plane)

Figure 5. Layer 3 (Power Plane)

SLAU173A–December 2005–Revised November 2009 DAC8580/81 Evaluation Module

PCB Design and Performance

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Figure 6. Layer 4 (Bottom Signal Plane)

Figure 7. Bottom Silkscreen

2.2 EVM Performance Results

The EVM performance test was achieved using the DAC8580/81EVM piggy-backed onto the High

Interface Board (HIB) for DAC tester, and tested using the Teradyne A580 connected to a personal

computer. The EVM board is tested for all codes of the device under test (DUT) and is allowed to settle

before the measurement is recorded. This process is repeated for all codes to generate the

measurements for INL and DNL results.

6DAC8580/81 Evaluation Module SLAU173A–December 2005–Revised November 2009

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PCB Design and Performance

The results of the DAC8580/81EVM characterization test are shown in Figure 8 and Figure 9.

Figure 8. INL Characteristic Plot for the DAC8581

Figure 9. DNL Characteristic Plot for the DAC8581

SLAU173A–December 2005–Revised November 2009 DAC8580/81 Evaluation Module

EVM Operation

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3 EVM Operation

This section covers in detail the EVM operation to provide guidance to the user in evaluating the onboard

DAC and how to interface the EVM to a host processor.

See the specific DAC data sheet, as listed in the Related Documentation from Texas Instruments section

(Section 3.5) of this user guide for more information about the DAC serial interface and other related

topics.

The EVM board is factory-tested and configured to operate in the bipolar output mode.

3.1 Factory Default Setting

The EVM board is set to its default configuration from the factory as described in Table 1 to operate in

bipolar ±5-V output operation as measured from TP5. The default jumper settings below are shown in

Figure 10 and Figure 11 for each respective EVM.

Table 1. DAC8580/81EVM Factory Default Jumper Setting

DAC8580/81EVM Jumper Default Configuration

Reference Jumper Position Function

W1 2-3 DVDD is powered at +3.3 VD.

W4 1-2 DAC reference is sourced externally from U3.

W5 1-2 Negative supply rail of U2 operational amplifier is sourced by VSS.

W7 CLOSE OSR1 is tied low, configured for 2x oversampling rate. This is hardwired to DGND for the

DAC8580/81EVM.

W8 CLOSE OSR2 is tied low, configured for 2x oversampling rate. This is hardwired to DGND for the

DAC8580/81EVM.

W9 CLOSE RSTB is tied low so the DAC is configured for conventional operation. Digital filter is

disconnected. This is hardwired to DGND for the DAC8580/81EVM.

W10 CLOSE BPB is tied low so the DAC is configured for conventional operation. Digital filter is

disconnected. This is hardwired to DGND for the DAC8580/81EVM.

W14 1-2 The CS signal is routed to FSYNC to synchronize the data word.

W15 CLOSE Output operational amplifier is configured for a gain of 2.

W16 OPEN MUTEB/CLR is high so that the DAC8580/DAC8581 output is not set to midscale (~0V).

W17 CLOSE (For For the DAC8580EVM, this jumper must be connected to digital ground reference for proper

DAC8580EVM) operation.

OPEN (For For the DAC8581EVM, this jumper must be connected to DVDD for proper operation;

DAC8581EVM) therefore, the jumper is not installed.

J3 2-3 DAC output is tied to the noninverting input of the output operational amplifier.

J4 1-2 DAC VOUT is routed to the J3 jumper.

J6 5-6 AGND and DGND are tied together.

8DAC8580/81 Evaluation Module SLAU173A–December 2005–Revised November 2009

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Jumpers are

hardwired to DGND.

This jumper header is not installed.

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EVM Operation

Figure 10. DAC8580EVM Default Jumper Setting

Figure 11. DAC8581EVM Default Jumper Setting

3.2 Host Processor Interface

The host processor basically drives the DAC; therefore, the DAC proper operation depends on the

successful configuration between the host processor and the EVM board. In addition, a properly written

code is also required to operate the DAC.

A custom cable can be made specific to the host interface platform. The EVM allows interface to the host

processor through J2 and P2 pass-through header connector for the serial control signals and the serial

data input. The output can be monitored through the J4 header connector.

A TI Interface Board is also available for a specific TI DSP Starter Kit as well as an MSP430-based

microprocessor as mentioned in Section 1 of this manual. Using the interface board foregoes the task of

building customized cables and allows easy configuration of a simple evaluation system.

This DAC EVM interfaces with any host processor capable of handling serial communication protocols or

the popular TI DSP. For more information regarding the serial interface of the particular DAC installed, see

the specific DAC data sheet, as listed in the Related Documentation from Texas Instruments section of

this user guide.

SLAU173A–December 2005–Revised November 2009 DAC8580/81 Evaluation Module

EVM Operation

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3.3 The Output Operational Amplifier

The EVM includes an optional signal-conditioning circuit for the DAC output through an external

operational amplifier, U2. The output operational amplifier is set to unity gain configuration by default.

Nevertheless, the raw output of the DAC can be probed through the even pins of the output terminal, J4.

The inverting input of U2 can be tied to the gain resistor, R12 (via W15) or the DAC output (by shorting

pins 3 and 4 of the J3 header) or to any voltage source through J3-4.

The following sections describe the different configurations of the output amplifier, U2. This operational

amplifier can be used to serve as buffer to unload the DAC and also different signal conditioning and

amplification purposes desired.

This buffering circuit may present some slight distortion because of the feedback resistor and capacitor. If

this is the case, users can easily configure the feedback circuit to closely match the desired wave shape

by simply removing R6 and C12 and replacing it with the proper values. Additionally, C12 can be removed

altogether and R6 can be replaced with a 0-Ωresistor if desired.

3.3.1 Unity Gain Output

Table 2 shows the jumper setting for the unity gain configuration of the DAC output buffer in unipolar or

bipolar mode.

Table 2. Unity Gain Output Jumper Settings

Jumper Position

Reference Unipolar Bipolar Function

J3 2-3 2-3 Routes the DAC output to the noninverting terminal of the output operational amplifier, U2.

W15 OPEN OPEN Disconnect the inverting input of the operational amplifier, U2, from gain resistor, R12.

W5 2-3 1-2 Negative rail of operational amplifier is tied to AGND or powered by VSS.

3.3.2 Output Gain of Two

Table 3 shows the proper jumper settings of the EVM for the 2× gain output of the DAC.

Table 3. Gain of Two Output Jumper Settings

Jumper Position

Reference Unipolar Bipolar Function

J3 2-3 2-3 Routes the DAC output to the noninverting terminal of the operational amplifier, U2.

W15 CLOSED CLOSED Inverting input of the output operational amplifier, U2, is connected to gain resistor, R12, to

set for a gain of 2.

W5 2-3 1-2 Supplies power, VSS, to the negative rail of operational amplifier, U2, for bipolar supply mode

or ties it to AGND for unipolar supply mode.

3.3.3 Output Gain of Five With DAC VOUT Inverted

Table 4 shows the proper jumper settings of the EVM to achieve a gain of five with the output of the DAC

inverted.

Table 4. Jumper Settings for a Gain of Five With Inverted Output

Jumper Position

Reference Unipolar Bipolar Function

J3 1-2 & 3-4 1-2 & 3-4 Output of DAC is inverted with a gain of five. Watch for clipping due to operational amplifier

headroom issue.

W15 OPEN OPEN Disconnect the inverting input of operational amplifier, U2, from the gain resistor, R12.

W5 2-3 1-2 Supplies power, VSS, to the negative rail of operational amplifier, U2, for bipolar supply

mode, or ties it to AGND for unipolar supply mode.

10 DAC8580/81 Evaluation Module SLAU173A–December 2005–Revised November 2009

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