Texas Instruments TPSM846C24 Bedienungsanleitung

SNVU570A–December 2017–Revised June 2018

TPSM846C24 70-A Parallel Operation Evaluation Module

User's Guide

SNVU570A–December 2017–Revised June 2018

TPSM846C24 70-A Parallel Operation Evaluation Module

This user’s guide contains information for the TPSM846C24DEVM-007 evaluation module (BSR007). Also

included are the performance specifications, schematic, bill of materials (BOM), and layout of the EVM.

Contents

1 Description.................................................................................................................... 2

2 Getting Started............................................................................................................... 2

3 Test Point Descriptions ..................................................................................................... 3

4 Operation Notes.............................................................................................................. 4

5 Performance Data ........................................................................................................... 5

6 Schematic..................................................................................................................... 6

7 Bill of Material ................................................................................................................ 7

8 PCB Layout................................................................................................................... 8

List of Figures

1 EVM User Interface.......................................................................................................... 2

2 Efficiency...................................................................................................................... 5

3 Power Dissipation............................................................................................................ 5

4 Output Voltage Ripple....................................................................................................... 5

5 TPSM846C24DEVM-007 Schematic...................................................................................... 6

6 Top Components ............................................................................................................ 8

7 Topside Copper.............................................................................................................. 8

8 Layer 2 Copper .............................................................................................................. 8

9 Layer 3 Copper .............................................................................................................. 8

10 Layer 4 Copper .............................................................................................................. 8

11 Layer 5 Copper .............................................................................................................. 8

12 Bottom-Side Copper......................................................................................................... 9

13 Bottom Components (Bottom View)....................................................................................... 9

List of Tables

1 Test Points.................................................................................................................... 3

2 TPSM846C24DEVM-007 Bill of Material ................................................................................. 7

Trademarks

All trademarks are the property of their respective owners.

Description

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TPSM846C24 70-A Parallel Operation Evaluation Module

1 Description

The TPSM846C24 device is a synchronous buck power module designed to provide up to 35-A of output

current. The TPSM846C24 can be paralled with two devices to achieve output current up to 70 A. The

TPSM846C24 is a highly integrated, DC-DC power module that combines a 35-A DC/DC converter with

power MOSFETs, a shielded inductor, some input and output capacitors, and passives into a low profile

package. The input voltage range is from 4.5 V to 15 V. The output voltage range is from 0.5 V to 2 V.

This evaluation module is designed to demonstrate the ease-of-use and small printed-circuit-board area

that may be achieved when paralleling two TPSM846C24 power modules. Monitoring test points are

provided to allow measurement of efficiency, power dissipation, input ripple, output ripple, line and load

regulation, and transient response. Additionally, control test points are provided for use of the power good,

enable control, and undervoltage lock out (UVLO) features of the device. The EVM uses a recommended

PCB layout that maximizes thermal performance and minimizes output ripple and noise.

2 Getting Started

Figure 1 highlights the user interface items associated with the EVM. The polarized input power terminal

block (TB1) is used for connection to the host input supply. TB2 and TB3 allow 4 terminals for VOUT and

TB4 and TB5 allow 4 terminals for PGND for connection to the load. These terminal blocks can except up

to 12-AWG wire.

Figure 1. EVM User Interface

The VIN monitor (VIN and PGND) and VOUT monitor (VS+ and VS–) test points located near the input

terminal block and the output terminal blocks are intended to be used as voltage monitoring points where

voltmeters can be connected to measure the input and output voltages. Do not use these VIN and VOUT

monitoring test points as the input supply or output load connection points. The PCB traces connecting to

these test points are not designed to support high currents.

The VIN scope (J1) and VOUT scope (J2) test points can be used to monitor VIN and VOUT waveforms

with an oscilloscope. These test points are intended for use with un-hooded scope probes outfitted with a

low-inductance ground lead (ground spring) mounted to the scope barrel. The two sockets of each test

point are on 0.1 inch centers. Insert the scope probe tip into the socket labeled VIN or VOUT, and insert

the scope ground lead into the hole of the socket labeled PGND.

The test points located directly below the device are made available to test the features of the device. Any

external connections made to these test points should be referenced to one of the AGND test points

located along the bottom of the EVM. Refer to Test Point Descriptions for more information on the

individual control test points.

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Test Point Descriptions

SNVU570A–December 2017–Revised June 2018

TPSM846C24 70-A Parallel Operation Evaluation Module

The Vout Select jumper (P4) is used to set the output voltage. The default loading is the 1.0 V position.

The Comp Select jumper (P2) sets the proper frequency compensation for the total amount of output

capacitance present on the VOUT bus. The EVM is shipped with approximately 2000 µF of output

capacitance loaded on the board. Locations are provided on the board to add another 2000 µF of output

capacitance (C28–C31). The default jumper load is the 2000 µF position.

When two TPSM846C24 devices are paralleled, the SYNC pins of the Master and the Slave must be

supplied with a 50% duty cycle external clock signal at the desired switching frequency. A 500-kHz clock

is present on the EVM which supplies the required 50% duty cycle signal. The Master device (U1) locks to

the rising edge of the clock and the Slave device (U2) locks to the falling edge of the clock.

3 Test Point Descriptions

Wire-loop test points and scope probe test points are provided as convenient connection points for digital

voltmeters (DVM) or oscilloscope probes to aid in the evaluation of the device. Table 1 provides a

description of each test point:

Table 1. Test Points

Test Point Description

VIN Input voltage monitor. Connect DVM to this point for measuring efficiency.

VS+ Supply path output voltage monitor. Connect DVM positive lead to this point for line regulation and load

regulation.

VS– Return path output voltage monitor. Connect DVM negative lead to this point for measuring line regulation

and load regulation.

VOUT Output voltage monitor. Connect DVM to this point and PGND for measuring efficiency.

PGND Input and output voltage monitor grounds. Reference the VIN and VOUT DVMs to these ground points.

VIN MON (J1) Input voltage scope monitor. Connect an oscilloscope to this set of points to measure input ripple voltage.

VOUT MON (J2) Output voltage scope monitor. Connect an oscilloscope to this set of points to measure output ripple

voltage and transient response.

AGND Analog ground point. Use any of the AGND test points as the ground reference for the control signals.

EN EN pin. Pull to AGND to stop power conversion. Float or pull to 3.3 V to enable power conversion. An

internal 10-kΩpullup resistor to 3.3 V is present on the EVM.

EXT CLK External clock input. This is the input to a D flip-flop. Apply an external clock at a frequency that is twice the

required switching frequency. Remove R13 before applying the clock signal.

SYNC SYNC monitor pin. This pin is the output of a D flip-flop which supplies a clock to both devices.

PGOOD Monitors the power good signal of the device. This is an open-drain signal that has an onboard 10-kΩ

pullup resistor to 3.3 V.

DIFFO Output of remote sense differential amplifier.

Signal Signal injection point for Bode plot analyzer. Inject from Signal to CHB.

CHA Input signal monitoring point for Bode plot analyzer.

CHB Output signal monitoring point for Bode plot analyzer.

PH1 Switch node of the TPSM846C24 Master device (U1). Use an unshielded scope probe to monitor this point.

PH2 Switch node of the TPSM846C24 Slave device (U2). Use an unshielded scope probe to monitor this point.

NOTE: Refer to TPSM846C24 4.5-V to 15-V Input, 0.5-V to 2.0-V Output, 35-A Power Module for

absolute maximum ratings associated with features in Table 1.

Operation Notes

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TPSM846C24 70-A Parallel Operation Evaluation Module

4 Operation Notes

To operate the EVM, apply a valid input voltage from 4.5 V to 15 V. The output voltage can be set over

the range from 0.5 V to 2.0 V.

The Power Good (PGOOD) indicator of the EVM will assert high when the output voltage is within ±5% of

the programmed output voltage value. A 10-kΩpullup resistor (R18) is populated between the PGOOD pin

and the 3V3 pin.

The TPSM846C24DEVM-007 is set-up to operate at 500 kHz. A clock circuit is present on the bottom of

the EVM. The clock circuit produces a 500 kHz, 50% duty cycle clock that feeds both devices. If another

switching frequency is required, R20 must be removed from the clock circuit on the bottom of the EVM

and an external clock must be connected to the EXT CLK test point. The external clock applied to EXT

CLK test point must be 2 × the required frequency. The device can be synchronized to an external clock

over the frequency range of 300 kHz to 1 MHz. Refer to TPSM846C24 4.5-V to 15-V Input, 0.5-V to 2.0-V

Output, 35-A Power Module for further information on synchronization.

The TPSM846C24DEVM-007 includes both input and output capacitors. The EVM includes footprints for

adding additional input and output capacitors to the EVM. Adding additional capacitance will improve

transient response. The actual capacitance required will depend on the input and output voltage conditions

of the particular application, along with the desired transient response. Refer to the product data sheet for

further information on input and output capacitance and transient response.

CAUTION

Do not change jumper settings while the module is powered. Permanent

damage may occur.

Output Current (A)

Output Voltage Ripple (mV)

0 10 20 30 40 50 60 70

D003

1.8 V

1.2 V

0.8 V

Output Current (A)

Efficiency (%)

0 10 20 30 40 50 60 70

100

D001

1.8 V

1.2 V

0.8 V

Output Current (A)

Power Dissipation (W)

0 10 20 30 40 50 60 70

D002

1.8 V

1.2 V

0.8 V

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Performance Data

SNVU570A–December 2017–Revised June 2018

TPSM846C24 70-A Parallel Operation Evaluation Module

5 Performance Data

Figure 2 through Figure 4 provide the EVM performance data with the following conditions:

VIN = 12 V, Fsw = 500 kHz, COUT = 4 × 47-µF ceramic plus 4 × 470-µF polymer

Figure 2. Efficiency Figure 3. Power Dissipation

Figure 4. Output Voltage Ripple

VIN

PGND

VS+

VOUT

PGND

PVIN

0.01µF

TP9

10.0k

R18

330µF

470µF

C25

DNP

PGND

VOUT

VIN

AGND

4.7µF

C11

1µF

C15

PGND

49.9

330µF

0.01µF

47µF

C21

47µF

C22

470µF

C26

DNP 470µF

C27

470µF

C28

TP1

TP15 TP16 TP17

0.1µF

C12

0.01µF

C16

2.2µF

C17

10.0k

R17

PGND

2000uF

4000uF

10.0k

DNP

TP19

665

R13 1500pF

C33

499

R14 2200pF

C34

AGND

TP13

6V5M

VINBP

3V3M

VIN_RTN

RT_SEL

AGND

PGND

VSHARE

PGOOD

SYNC

Signal CHA CHB

VIN

VOUT

VS-

DIFFO

Comp Sel

Vout Gain

PGOOD

TP6TP5

VS+

VS-

1 2

3 4

TB1

TP8

Ishare

Sync

TP10

TP11

GND

PGND

TP4DNP

PH2

PH1

TP3DNP

4.7µF

C13 0.1µF

C14

PGND

1µF

C18

0.01µF

C19

2.2µF

C20

3V3S

VIN_RTN_S

PGND

0.01µF

1 2

3 4

5 6

7 8

9 10

Sync

Vshare

Ishare

AGND

PGND

AGND

10.0

R11

10.0

R12

3V3

PGND

0.01µF

C10

1.00k

R22

49.9

R10

5.11k

R21

PGND

ISHARE

VSHARE

RT 13

NC 15

RT_SEL 14

FB 7

DNC 21

COMP 9

SYNC

NC 1

VS- 5

BP_RTN

PGOOD

DNC

PH 22

PH 23

DNC 30

PH 24

PH 25

PH 26

PH 27

PH 28

PH 29

DNC 31

DNC 8

PGND 35

PGND 34

PGND 59

PGND 42

PGND 43

VOUT 37

VOUT 38

VOUT 39

VOUT 40

VOUT 41

VOUT 55

PGND 33

PGND 54

VIN

45 VIN

DNC

PGND 56

PGND 57

VIN

DIFFO 6

VS+ 4

PGND 36

VIN

AGND 10

BP6_RTN

PGND 32

PGND 58

BP3

BP6

VINBP

DNC

TPSM846C24MOL

ISHARE

VSHARE

RT 13

NC 15

RT_SEL 14

FB 7

DNC 21

COMP 9

SYNC

NC 1

VS- 5

BP_RTN

PGOOD

DNC

PH 22

PH 23

DNC 30

PH 24

PH 25

PH 26

PH 27

PH 28

PH 29

DNC 31

DNC 8

PGND 35

PGND 34

PGND 59

PGND 42

PGND 43

VOUT 37

VOUT 38

VOUT 39

VOUT 40

VOUT 41

VOUT 55

PGND 33

PGND 54

VIN

45 VIN

DNC

PGND 56

PGND 57

VIN

DIFFO 6

VS+ 4

PGND 36

VIN

AGND 10

BP6_RTN

PGND 32

PGND 58

BP3

BP6

VINBP

DNC

TPSM846C24MOL

PGND

3V3

VIN 3V3

0.01µF

C35

PGND

1µF

C36

CLK

VCC

GND 3

SN74LVC1G80DCKR

R15

3V3

PGND

SYNC

TP12

V+

1CLOCK 2

GND 3

MAX7375AXR105-T

PGND

49.9

R20

1MHz Oscillator

PGND

PH1 PH2

Vshare

VOUT

PGND

47µF

C23

47µF

C24

22µF

C3 6V5S

VINBPS

5.11k

R19 ISHARE

470µF

C29

DNP 470µF

C30

DNP 470µF

C31

470µF

C32

TP2

NT1

Net-Tie

NT2

Net-Tie

TP14

TP18 TP20

TP7

OUT 6

GND

U3A

TPS715A33DRVR

39.2k

R16

DNP

39.2k

DNP

AGND

3.83k

7.15k

8.25k

10.0k

16.5k

0.8V

1.0V

1.1V

1.2V

1.8V

Schematic

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TPSM846C24 70-A Parallel Operation Evaluation Module

6 Schematic

Figure 5 illustrates the TPSM846C24DEVM-007 schematic.

Figure 5. TPSM846C24DEVM-007 Schematic

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Bill of Material

SNVU570A–December 2017–Revised June 2018

TPSM846C24 70-A Parallel Operation Evaluation Module

7 Bill of Material

Table 2 lists the EVM BOM.

Table 2. TPSM846C24DEVM-007 Bill of Material

Designator QTY Description Part Number Manufacturer

PCB 1 Printed Circuit Board - Any

U1, U2 2 TPSM846C24 TPSM846C24MOL Texas Instruments

C1, C2 2 CAP, AL, 330 µF, 25 V, ±20%, 0.053 ohm, TH 25ZL330MEFC10X12.5 Rubycon

C3, C4, C7, C8 4 CAP, CERM, 22 µF, 25 V, ±10%, X5R, 1210 GRM32ER61E226KE15L Murata

C5, C6, C9, C10,

C16, C19, C35 7 CAP, CERM, 0.01 µF, 50 V, ±10%, X7R, 0603 GRM188R71H103KA01D Murata

C11, C13 2 CAP, CERM, 4.7 µF, 16 V, ±10%, X5R, 0805 GRM21BR61C475KA88L Murata

C12, C14 2 CAP, CERM, 0.1 µF, 16 V, ±10%, X7R, 0603 GRM188R71C104KA01D Murata

C15, C18 2 CAP, CERM, 1 µF, 25 V, ±10%, X7R, 0805 GRM21BR71E105KA99L Murata

C17, C20 2 CAP, CERM, 2.2 µF, 16 V, ±10%, X7R, 0805 GRM21BR71C225KA12L Murata

C21, C22, C23, C24 4 CAP, CERM, 47 µF, 6.3 V, ±20%, X5R, 1210 GRM32ER60J476ME20L Murata

C27, C28, C31, C32 4 CAP, Tantalum Polymer, 470 µF, 6.3 V, ±20%, 0.01 ohm, 7343-40

SMD 6TPF470MAH Panasonic

C33 1 CAP, CERM, 1000 pF, 16 V, ±10%, X7R, 0402 GRM155R71C102KA01D Murata

C34 1 CAP, CERM, 2200 pF, 50 V, ±10%, X7R, 0402 GCM155R71H222KA37D Murata

C36 1 CAP, CERM, 1 µF, 16 V, ±10%, X7R, 0603 GRM188R71C105KA12D Murata

C25, C26, C29, C30 0 CAP, Tantalum Polymer, 470 µF, 6.3 V, ±20%, 0.01 ohm, 7343-40

SMD 6TPF470MAH Panasonic

D1 1 LED, Green, SMD 150060GS75000 Wurth Elektronik

J1, J2 2 Socket Strip, 2x1, 100mil, Black, Tin, TH 310-43-102-41-001000 Mill-Max

P1 1 Header, 2.54mm, 5x2, Gold, TH AWHW-10G-0202-T Assman WSW

P2, P4 2 Header, 100mil, 2x2, Tin, TH PEC02DAAN Sullins Connector Solutions

R1, R3 2 RES, 0, 5%, 0.063 W, 0402 CRCW04020000Z0ED Vishay-Dale

R5, R6, R7 3 RES, 121 k, 1%, 0.063 W, 0402 CRCW0402121KFKED Vishay-Dale

R8 1 RES, 51.1 k, 1%, 0.063 W, 0402 CRCW040251K1FKED Vishay-Dale

R9, R10, R23 3 RES, 49.9, 1%, 0.1 W, 0603 CRCW060349R9FKEA Vishay-Dale

R11, R12 2 RES, 10.0, 1%, 0.1 W, 0603 CRCW060310R0FKEA Vishay-Dale

R13 1 RES, 665, 1%, 0.063 W, 0402 CRCW0402665RFKED Vishay-Dale

R14 1 RES, 499, 1%, 0.063 W, 0402 CRCW0402499RFKED Vishay-Dale

R15, R16, R18, R20 4 RES, 10.0 k, 1%, 0.063 W, 0402 CRCW040210K0FKED Vishay-Dale

R17 1 RES, 4.99 k, 1%, 0.063 W, 0402 CRCW04024K99FKED Vishay-Dale

R19, R21 2 RES, 5.11 k, 1%, 0.063 W, 0402 CRCW04025K11FKED Vishay-Dale

R22 1 RES, 1.00 k, 1%, 0.063 W, 0402 CRCW04021K00FKED Vishay-Dale

R2, R4 0 RES, 39.2 k, 1%, 0.063 W, 0402 CRCW040239K2FKED Vishay-Dale

TB1, TB2, TB3,

TB4, TB5 5 Terminal Block, 30A, 9.52mm (.375) Pitch, 2-Pos, TH OSTT7022150 On-Shore Technology

TP1, TP5, TP6,

TP7, TP8, TP9,

TP10, TP12, TP15,

TP16, TP17, TP19,

R24

13 Test Point, Multipurpose, White, TH 5012 Keystone

TP2, TP11, TP13,

TP18, TP20, TP21,

TP22, TP23 8 Test Point, Multipurpose, Black, TH 5011 Keystone

TP14 1 Test Point, Multipurpose, Red, TH 5010 Keystone

TP3, TP4 0 Test Point, Multipurpose, White, TH 5012 Keystone

U3 1 Single Output LDO, 80 mA, Fixed 3.3 V Output, 2.5 to 24 V Input,

6-pin SON (DRV) TPS715A33DRVR Texas Instruments

U4 1 1MHz CMOS Silicon Oscillator, SOT-323 MAX7375AXR105-T Maxim

U5 1 Single Positive-Edge-Triggered D-Type Flip-Flop, (SOT-5) SN74LVC1G80DCKR Texas Instruments

PCB Layout

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TPSM846C24 70-A Parallel Operation Evaluation Module

8 PCB Layout

Figure 6 through Figure 13 display the EVM PCB layout images.

Figure 6. Top Components Figure 7. Topside Copper

Figure 8. Layer 2 Copper Figure 9. Layer 3 Copper

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PCB Layout

SNVU570A–December 2017–Revised June 2018

TPSM846C24 70-A Parallel Operation Evaluation Module

Figure 10. Layer 4 Copper Figure 11. Layer 5 Copper

Figure 12. Bottom-Side Copper Figure 13. Bottom Components (Bottom View)

Revision History

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Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (December 2017) to A Revision ................................................................................................ Page

• Corrected resistor references R18 and R20........................................................................................... 4

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