Texas Instruments ADC368 EVM Series Bedienungsanleitung

User’s Guide

ADC368xEVM Evaluation Module

Abstract

This user’s guide describes the characteristics, operation, and use of the ADC368x evaluation module (EVM).

This user's guide discusses how to set up and configure the software and hardware, and reviews various

aspects of the program operation. Throughout this document, the terms evaluation board, evaluation module,

and EVM are synonymous with the ADC368xEVM. In the following sections of this document, the ADC368x

evaluation board is referred to as the EVM and the ADC368x devices are referred to as the ADC devices,

respectively. This document applies only to the ADC3683EVM and ADC3682EVM.

Table of Contents

Abstract...................................................................................................................................................................................... 1

1 Introduction.............................................................................................................................................................................2

2 Equipment............................................................................................................................................................................... 2

2.1 ADC368xEVM Functionality...............................................................................................................................................2

2.2 Evaluation Board Feature Identification Summary.............................................................................................................4

2.3 Required Equipment.......................................................................................................................................................... 5

3 Setup Procedure..................................................................................................................................................................... 6

3.1 Install High-Speed Data Converter (HSDC) Pro Software................................................................................................. 6

3.2 Install ADC35XXEVM GUI 1.0 Software............................................................................................................................ 6

3.3 Connect the ADC368xEVM and TSW1400EVM................................................................................................................6

3.4 Connect the Power Supply and Mini-USB Connections.................................................................................................... 7

3.5 Connect the Clocks and Analog Input................................................................................................................................7

4 ADC GUI Configuration.......................................................................................................................................................... 8

4.1 Bypass Mode..................................................................................................................................................................... 9

4.2 Real Decimation Mode.....................................................................................................................................................13

4.3 Complex Decimation Mode.............................................................................................................................................. 16

5 Onboard Clocking Hardware Setup.................................................................................................................................... 20

5.1 Hardware Modfications.................................................................................................................................................... 21

5.2 Onboard Clock: ADC35XX GUI Real Decimation Mode ................................................................................................. 23

6 FDA Configuration................................................................................................................................................................24

7 ADC36xxEVM Power Monitor.............................................................................................................................................. 26

8 Test Pattern........................................................................................................................................................................... 27

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ADC368xEVM Evaluation Module 1

1 Introduction

The ADC36xxEVM is an evaluation board used to evaluate the ADC368x analog-to-digital converters (ADC)

from Texas Instruments. The ADC368x uses a serial LVDS interface to output the digital data. The serialized

LVDS interface supports output rates to 1 Gbps. The ADC368x can be operated in 'oversampling + decimating'

mode using the internal decimation filter in order to improve the dynamic range and relax external anti-aliasing

filter.

The ADC368xEVM is equipped with the following features:

• Transformer and FDA coupled analog inputs

• CDCE6214 clocking solution for on-board clocking

• Transformer coupled or single-ended clock inputs

• INA226 current shunt monitors for evaluating power consumption

• Power over mini-USB

• FMC connector

By default, the EVM is configured to receive external inputs for the sampling clock and analog input via AC-

coupled, transformer (balun) inputs. These transformers perform single-ended to differential conversion, and

provide a low noise/distortion passive input.

To exercise the full performance capabilities of this high performance SAR ADC, it is recommended to evaluate

the ADC in the default configuration, and then evaluate in other configurations (like onboard clocking or FDA

input), as required.

2 Equipment

This hardware setup procedure is written with the intent to use external clocking (sample clock and DCLKIN) and

transformer coupled analog inputs. Using onboard clocking and FDA driven analog inputs is an option, and

instructions are provided toward the end of this document to make the required hardware/software modifications.

2.1 ADC368xEVM Functionality

The ADC368xEVM receives power from the USB 2.0, +5 V rail, and is then converted to +3.3 VDC and +1.8

VDC. The ADC receives +1.8 VDC from the TPS62231 DC-DC converter. The power consumption of the 1.8 V

rail can be monitored (using the INA226) in the ADC35xxEVM GUI. USB-to-SPI communication is established

using the FTDI (FT4234H). The ADC clocks can be supplied externally or from the onboard PLL/Distributor

CDCE6214 (high quality external clocks are used to acheive best AC performance). The analog input can be AC

coupled through the Balun (ADT1-6T+) input, or DC (or AC) coupled with the onboard FDA (THS4541). The

analog input is 3.2 Vpp, and is driven a -1 dBFS (~2.8 Vpp) in all examples in this user's guide.

The ADC368x family has a +1.6 V voltage reference (VREF), and can be supplied internally or externally. By

default, the EVM is configured to supply an external voltage reference using the REF3318 (divided down to

+1.6V) and the OPA837 high speed amplifier to drive the voltage reference. At any time, the VREF can be

changed to internal reference by SPI write.

The ADC368x family uses an unbuffered analog input, so a glitch filter is required to attenuate the ADC sampling

glitch from when the sampling capacitors switch (sample/hold). The glitch filter acts as a low pass filter with an

corner frequency (Fc) at 30 MHz (accepts DC to 30 MHz).

The ADC368xEVM LVDS output data is routed to an FMC connector, and then connected to the LVDS

Interposer card. This interposer card then maps to the TSW1400EVM's HSMC connector in order to capture the

ADC368xEVM SLVDS clock and data signals.

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Figure 2-1. ADC36xxEVM block diagram: Balun input

Figure 2-2. ADC36xxEVM block diagram: FDA input

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ADC368xEVM Evaluation Module 3

2.2 Evaluation Board Feature Identification Summary

Figure 2-3. ADC368xEVM Feature Identification

Ensure that jumper J16 is shunted in the 2-3 position. This allows 5 V to be supplied to the ADC368xEVM

through the mini-USB connector.

If an external 5-V supply is desired, J16 must be shunted in the 1-2 position, and the external 5 V can be

connected to the test point labeled "+5 EXT". The USB data connection will still be connected for SPI

communications.

J13 is tied to the REFBUF pin. It can be left floating, or can be tied to 1.8V (shunt pins 2-3) for normal operation.

J14 is tied to the PDN/SYNC pin. It can be left floating for tied to ground (shunt pins 1-2) for normal operation. To

power down the ADC, tied to 1.8V (shunt pins 2-3). The ADC may also be powered down via SPI.

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Figure 2-4. LVDS Interposer

2.3 Required Equipment

• The following equipment is included in the EVM evaluation kit:

– ADC368xEVM Evaluation board (EVM)

– LVDS FPGA Interposer Card

– Mini-USB cable

The following equipment is not included in the EVM evaluation kit, but is required for evaluation of this EVM:

• TSW1400EVM data capture board and related items

•HSDC Pro software

• PC running Microsoft® Windows® 7, or 10

• One low-noise signal generator for the analog input (If using onboard clock option, no additiona signal

generators are required).

• Two low-noise signal generators for the sample clock and DCLKIN. (These two signal generators must share

the same reference frequency).

TI recommends the following generators:

• Rohde & Schwarz SMA100A

• Rohde & Schwarz SMA100B

A bandpass filter is required for the analog input signal due to most signal generators addition of phase noise or

spurious components. A bandpass filter should also be used for the sample clock input. The DCLKIN input does

not require a bandpass filter. If bandpass filters are not used, then the true performance of the ADC may not be

seen clearly, and will be limited by the performance of the signal generators being used.

The following recommended bandpass filter will have:

• Bandpass filter, greater than or equal to 60-dB harmonic attenuation, less than or equal to 5% bandwidth,

greater than 18-dBm power, less than 5-dB insertion loss

• Signal-path cables, SMA

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ADC368xEVM Evaluation Module 5

3 Setup Procedure

This Setup Procedure will detail how to setup the ADC368xEVM hardware and software GUI required for

evaluation using external sample and DCLKIN clocks. The clock rates in the following steps apply specifically to

the ADC3683EVM, but example clock rates are provided for other EVM variants.

3.1 Install High-Speed Data Converter (HSDC) Pro Software

Download the most recent version of the HSDC Pro software. Launch the executable, and accept the default

installation options.

Download and install the HSDC Pro Patch. This patch copies all the INI files required to the HSDC pro directory.

3.2 Install ADC35XXEVM GUI 1.0 Software

Download the ADC35XXEVM GUI 1.0 software from the EVM tool folder at ADC3683EVM.

Extract and run the executable file, and accept the default installation options.

3.3 Connect the ADC368xEVM and TSW1400EVM

Connect the ADC368xEVM FMC connector to J4 of the LVDS Interposer Card.

Connect J5 of the LVDS Interposer Card to J1 of the TSW1400EVM.

Figure 3-1. ADC368xEVM Complete Setup (external clocks)

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3.4 Connect the Power Supply and Mini-USB Connections

Use the following steps to connect the power supply and mini-USB connections:

1. Connect the power cable to the TSW1400EVM at 5-V (minimum 3 A) power supply. Place the power switch

(SW7) to the "On" position.

2. Connect the mini-USB cable to the TSW1400EVM (J2).

3. Connect the mini-USB cable to the ADC368xEVM (J16).

3.5 Connect the Clocks and Analog Input

Use the following steps to connect the external ADC clocks and analog input. If onboard clocking is to be used,

follow the instructions in the section Onboard Clocking Hardware Setup.

The clock frequencies shown below are for the power on/default settings (bypass mode/non-decimation) for the

ADC3683EVM, but the physical connections and signal power levels will remain the same for all ADC modes.

• For the sample clock (ADC3683EVM), set a signal generator to 65 MHz at a power level of +10 dBm.

Connect to the SMA connector J4. A bandpass filter for the sample clock is recommended for best AC

performance of the ADC368xEVM.

• For the DCLKIN clock (ADC3683EVM), set a signal generator to 292.5 MHz at a power level of +10 dBm. A

bandpass filter is not required for the DCLKIN clock.

External ADC sampling clock source and DCLKIN source must be frequency locked. If this is not

performed, the captured data will appear scrambled. If using the onboard clocking option, the

sampling clock and DCLKIN are frequency locked.

• For the analog input, set a signal generator to 5 MHz at a power level of ~ +15 dBm. A bandpass filter is

required to reduce harmonic and phase noise effects of the signal generator.

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ADC368xEVM Evaluation Module 7

4 ADC GUI Configuration

A hardware reset should be performed before programming the ADC by toggling the push button switch S1.

Also, a software reset may be performed at any time to reset the ADC registers to their default state.

Figure 4-1. ADC35xx Software Reset

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4.1 Bypass Mode

The following steps show how to configure the ADC368xEVM in Bypass mode with external sample clock and

DCLKIN. These instructions show how to configure the ADC3683EVM, but apply to other EVM variants as well.

4.1.1 ADC35XXEVM GUI: Bypass Mode (2W) Configuration

The following steps for Bypass (No Decimation) mode also apply to ADC3682EVM, but requires modification to

the sample/DCLKIN clocks in accordance with the desired sample rate and bit resolution.

For different sampling rates and bit resolutions, please use the tables for calculating the correct DCLKIN

frequency for the desired sample rate and bit resolution.

Table 4-1. 18-bit, Bypass Mode, Sample rate and DCLKIN examples (ADC3683EVM, ADC3682EVM)

Interface Mode DCLKIN multiplier Example Sample Clock Required DCLKIN Frequency

2 Wire 4.5 45 MSPS 202.5 MHz

1 Wire 9 32 MSPS 288 MHz

1/2 Wire 18 10 MSPS 180 MHz

Table 4-2. 16-bit, Bypass Mode, Sample rate and DCLKIN examples (ADC3663EVM, ADC3662EVM).

Interface Mode DCLKIN multiplier Example Sample Clock Required DCLKIN Frequency

2 Wire 4 65 MSPS 260 MHz

1 Wire 8 32 MSPS 256 MHz

1/2 Wire 16 10 MSPS 160 MHz

For this example, ensure that the sampling clock (J9) and DCLKIN (J7) are connected before launching the

ADC35XX EVM GUI. In this example for the ADC3683EVM, the sampling clock is 65 MHz, and the DCLKIN is

292.5 MHz.

External ADC sampling clock source and DCLKIN source must be frequency locked. If this is not

performed, the captured data will appear scrambled. If using the onboard clocking option, the

sampling clock and DCLKIN are frequency locked.

After launching the ADC35xx GUI perform the following steps:

• Under Resolution, select "18 bit".

• Under Mode, select "2 Wire".

• Ensure that "CDC Enable" is red (disabled).

• To calculate the DCLKIN frequency, enter "65" in the Fs(MHz) field, and click calculate. This is informational

only.

• Click "Configure" button.

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ADC368xEVM Evaluation Module 9

Figure 4-2. ADC35xx EVM GUI settings for 2W Bypass Mode

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