Texas Instruments ADS8860EVM-PDK Bedienungsanleitung

User's Guide

SBAU213–September 2013

ADS8860EVM-PDK

This user's guide describes the operation and use of the ADS8860 evaluation module (EVM). The

ADS8860 is a 16-bit, pseudo-differential, unipolar, successive approximation register (SAR), analog-to-

digital converter (ADC) with a maximum throughput of 1 MSPS. The device is a very low-power ADC with

excellent noise and distortion performance for ac or dc signals. The performance demonstration kit (PDK)

eases EVM evaluation with additional hardware and software for computer connectivity through a

universal serial bus (USB). The ADS8860EVM-PDK includes the ADS8860EVM as a daughter card,

MMB0 motherboard, A-to-B USB cable, and 6-V wall-adapter power supply. This user's guide covers

circuit description, schematic diagram, and bill of materials for the ADS8860EVM daughter card.

ADS8860EVM-PDK

Contents

1 Related Documentation .................................................................................................... 2

2 ADS8860EVM-PDK Overview ............................................................................................. 3

3 EVM Analog Interface ...................................................................................................... 4

4 EVM Digital Interface ....................................................................................................... 6

5 EVM Power-Supply Inputs ................................................................................................. 7

6 EVM Digital Configuration ................................................................................................. 8

7 PDK Kit Setup ............................................................................................................... 9

8 PDK Kit Operation ......................................................................................................... 11

9 Bill of Materials, Schematics, and Layout .............................................................................. 14

ADCPro is a trademark of Texas Instruments.

Windows is a registered trademark of Microsoft Corporation.

I2C is a trademark of NXP Semiconductors.

Samtec is a trademark of Samtec, Inc.

All other trademarks are the property of their respective owners.

SBAU213–September 2013 ADS8860EVM-PDK

Related Documentation

www.ti.com

ADS8860EVM-PDK (continued)

List of Figures

1 Differential Input Example ................................................................................................. 4

2 Single-Ended Signal Example............................................................................................. 5

3 THS4281 Reference Driver with Complementary OPA333 for Drift and Offset Correction ...................... 5

4 Serial 3-Wire Configuration................................................................................................ 8

5 Serial 4-Wire Configuration................................................................................................ 8

6 Plug-In Installer.............................................................................................................. 9

7 MMB0 Motherboard Jumper Configuration ............................................................................ 10

8 ADS8860EVM Jumper Configuration................................................................................... 10

9 Loading EVM Plug-in ..................................................................................................... 11

10 ADS8860EVM Plug-in: Device Configuration Tab .................................................................... 12

11 ADCPro Test Plug-ins .................................................................................................... 13

12 ADS8860EVM PCB: Top Layer ......................................................................................... 15

13 ADS8860EVM PCB: Ground Layer..................................................................................... 15

14 ADS8860EVM PCB: Power Layer ...................................................................................... 16

15 ADS8860EVM PCB: Bottom Layer...................................................................................... 16

List of Tables

1 Related Documentation .................................................................................................... 2

2 Analog Inputs................................................................................................................ 4

3 J2: Serial Interface Header ................................................................................................ 6

4 J3: Power-Supply Interface Header ...................................................................................... 7

5 ADS8860EVM Bill of Materials .......................................................................................... 14

1 Related Documentation

Table 1 lists the related documents that are available for download from Texas Instruments at www.ti.com.

Table 1. Related Documentation

Device Literature Number

ADS8860 SBAS547

OPA333 SBOS351

OPA376 SBOS406

OPA836 SLOS712

REF5045 SBOS410

THS4281 SLOS432

TPS78833 SLVS382

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ADS8860EVM-PDK Overview

2 ADS8860EVM-PDK Overview

The ADS8860EVM is an evaluation module built to the TI Modular EVM system specifications. The EVM

by itself has no microprocessor and cannot run software. Thus, the EVM is available as part of the

ADS8860EVM-PDK kit that combines the ADS8860EVM as a daughter board with the digital signal

processor (DSP)-based MMB0 motherboard using ADCPro™ software as a graphical user interface (GUI).

ADCPro software collects, records, and analyzes data from ADC evaluation boards. ADCPro also runs

different plug-in programs to easily expand testing and data collection capabilities. In combination with the

ADS8860EVM plug-in program, ADCPro offers a comprehensive evaluation environment for the

ADS8860. For more details on ADCPro, see the ADCPro Analog-to-Digital Converter Evaluation Software

User's Guide (SBAU128), available for download from www.ti.com.

ADS8860EVM Daughter Board Features:

• Includes support circuitry as a design example to match ADC performance

• 3.3-V slave serial peripheral interface (SPI)

• Serial interface header for easy connection to TI DSP-based communication systems

• Compatible with the TI Modular EVM system

• Designed for 5-V analog supply

• Onboard 4.5-V voltage reference

• Bipolar (–2.15 V to 2.15 V) or unipolar (0.1 V to 4.4 V) input range

ADS8860EVM-PDK Kit Additional Features:

• USB port for computer interfacing

• Regulated 5-V and 3.3-V supplies for powering EVM daughter board

• Easy-to-use evaluation software for Windows®operating system

• Data collection to text files

• Built-in analysis tools including scope, FFT, and histogram displays

• Easily expandable with new analysis plug-in tools from Texas Instruments

SBAU213–September 2013 ADS8860EVM-PDK

AINP

AINN

10000pF

4.7

1k

OPA836

+1.125V

-2.15V

+2.15V

1k

0V 5V

A0(-)

JP4 (CLOSED)

Transfer Function:

AINP = 2.25V ±A0(-)

0.1V

4.4V

2.25V

EVM Analog Interface

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3 EVM Analog Interface

The ADS8860EVM is designed for easy interfacing to multiple analog sources. SMA connectors allow

the EVM to have input signals connected through coaxial cables. In addition, the Samtec™ connector

provides a convenient 10-pin, dual-row, header and socket combination at J1. Consult Samtec at

www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating connector options. The analog inputs

are buffered by an OPA836 high-speed operational amplifier in order to properly drive the ADS8860

ADC input.

Use appropriate caution when handling these pins. Table 2 summarizes the pinout for analog interface J1.

Table 2. Analog Inputs

Connector Number Signal Description

Samtec 10 x 2 J1.10 A0(-) CH0 inverted EVM input

SMA J4 A0(-) CH0 inverted EVM input

3.1 Unipolar Input Signal Configuration

With JP4 closed, the OPA836 positive input is biased with +1.125 V, created by diving the 4.5-V onboard

reference by four. This bias becomes a 2.25-V offset at the output of the OPA836 that allows input signals

with a 0-V common mode. To keep the OPA836 distortion as low as possible, the input signal swing is

limited from –2.15 V to +2.15 V, as shown in Figure 1.

Figure 1. Differential Input Example

4ADS8860EVM-PDK SBAU213–September 2013

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0.22

1k

1µF

OPA333

THS4281

10µF

1µF

20k

1k

1µF

Vref

4.5V from

REF5045

AINP

AINN

10000pF

4.7

1k

OPA836

+2.25V

0.1V

+4.4V 1k

2.25V 5V

A0(-)

JP4 (OPEN)

Transfer Function:

AINP = 4.5V ±A0(-)

0.1V

4.4V

2.25V

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EVM Analog Interface

3.2 Bipolar Input Signal Configuration

With JP4 open, the OPA836 positive input is biased with +2.25 V, created by diving the 4.5-V onboard

reference by two. This bias becomes a 4.5-V offset at the output of the OPA836 that allows input signals

with a 2.25-V common mode. To keep the OPA836 distortion as low as possible, the input signal swing is

limited from +0.1 V to +4.4 V, as shown in Figure 2.

Figure 2. Single-Ended Signal Example

3.3 Voltage Reference

Because the EVM is powered by a 5-V analog supply, the reference should be a value below 5 V. This

EVM uses 4.5 V, created by the onboard REF5045, as shown in Figure 3. Then, the EVM is filtered by an

RC filter with a 160-Hz cutoff frequency to minimize noise contribution. Finally, the EVM is buffered by the

THS4281, which can drive the 10 μF required at the ADC reference (with a 2-MHz effective bandwidth

and 22-μVrms total noise). The OPA333 and the additional feedback is optional, but does complement the

THS4281, minimizing offset and drift.

Figure 3. THS4281 Reference Driver with Complementary OPA333 for Drift and Offset Correction

SBAU213–September 2013 ADS8860EVM-PDK

EVM Digital Interface

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4 EVM Digital Interface

Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-L-DV-P provide a convenient 10-pin, dual-

row, header and socket combinations at P1. The header and socket provide access to the ADC digital

control pins. Consult Samtec at www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating

connector options.

Table 3 summarizes the pinouts for digital interface J2.

Table 3. J2: Serial Interface Header

Pin Number Signal Description

Chip-select input that can be used as a convert

J2.1 CS or CONVST start

J2.3 SCLK Serial clock input

Chip-select input that can be used as a convert

J2.7 CS or CONVST start meant for the MMB0 motherboard

J2:13 SDO or MISO SDO or MISO output

20-kΩpull-up resistor for detecting falling edges at

J2.15 INT the end of conversion

Direct connection to the convert start pin if JP3 is

J2.17 CONVST installed

J2.4, J2.10, and J2.18 GND Digital ground connections

I2C bus; used only to program the U4 EEPROM on

J2.16, J2.20 I2C™ bus the EVM board

J2.2, J2.5-6, J2.8-9,

J2.11-12, J2.14, and Unused Unused

J2:19

4.1 Serial Interface (SPI)

The ADS8860 ADC uses SPI serial communication in mode 1 (CPOL = 0, CPHA = 1) with high-speed

clocks higher than 30 MHz; for slower clocks, mode 0 is used (CPOL = 0, CPHA = 0). Because the serial

clock (SCLK) frequency can be as fast as 80 MHz, the ADS8860EVM offers 47-Ωresistors between the

SPI signals and J2 to aid with signal integrity. Typically, in high-speed SPI communication, fast signal

edges can cause overshoot; these 47-Ωresistors slow down the signal edges in order to minimize signal

overshoot.

4.2 I2C Bus for Onboard EEPROM

The ADS8860EVM has an I2C bus that records the board name and assembly date to communicate with

the onboard EEPROM. The bus is not used in any form by the ADS8860 converter.

6ADS8860EVM-PDK SBAU213–September 2013

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EVM Power-Supply Inputs

5 EVM Power-Supply Inputs

J3 is the power-supply input connector. Table 4 lists the configuration details for J3.

Table 4. J3: Power-Supply Interface Header

Pin Number Pin Name Function Required

J3.3 +5VA 5-V analog supply Yes

J3.5 GND Digital ground input Yes

J3.6 GND Analog ground input Yes

J3.7 1.8 VD 1.8-V digital supply Optional

J3.9 3.3 VD 3.3-V digital supply Yes

J3.10 5 VD 5-V digital supply No

P3.1-2, P3.4, and P3.7- Unused Unused No

5.1 Analog Power Options

The ADS8860EVM board is designed to function with a 5-V analog power supply connected to J3.3. The

ADS8860 is limited to 3.6 V for the analog supply, so the board regulates down the 5-V analog supply with

an onboard 3.3-V low dropout receiver (LDO), such as the TPS78833.

5.2 Digital Power Options

The ADS8860EVM connects the digital power supply of the ADS8860 to 3.3 VD (J3.10) with a 0-Ω

resistor. This setting matches the logic level of the MMB0 motherboard.

5.3 Analog and Digital Grounds

The EVM only has one ground plane for all analog and digital supplies, thus, pins J3.5 and J3.6 are tied

together to this ground plane. Therefore, both supply grounds should be connected to pins J3.5–6 so they

share the same ground.

SBAU213–September 2013 ADS8860EVM-PDK

SDI

SCLK

SDO

CONVST

JP2

JP3

(CLOSED)

DVDD

10k

/CS

CONVST

J2:1 or J2:7

J2:17

ADS8860 /CS

CONVST

SDI

SCLK

SDO

CONVST

JP2

JP3

(OPEN)

DVDD

10k

/CS

J2:1 or J2:7

J2:17

ADS8860

EVM Digital Configuration

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6 EVM Digital Configuration

The EVM offers two jumpers (JP2 and JP3) to configure the EVM in either 3-wire SPI mode or 4-wire SPI

mode. By default, the EVM jumper settings are 3-wire. JP1 only establishes the pin that carries the chip-

select signal from the J2 header.

6.1 SPI 3-Wire Mode (JP2:2–3 and JP3:OPEN)

The chip-select signal is used to bring the ADS8860 digital output out of 3-state and initializes

conversions. The rising edge of the chip-select signal starts a conversion, then after the conversion time,

the falling edge of the chip-select signal brings the digital output out of 3-state. Figure 4 shows the serial

configuration for this mode.

Figure 4. Serial 3-Wire Configuration

6.2 SPI 4-Wire Mode (JP2:1–2 and JP3:CLOSED)

The chip-select signal is used to bring the ADS8860 digital output out of 3-state. However, conversion is

initialized from J3:17 as an independent signal. The rising edge of J3:17 (CONVST) starts a conversion,

then after the conversion time, the falling edge of the chip-select signal brings the digital output out of 3-

state. Figure 5 shows the serial configuration for this mode.

Figure 5. Serial 4-Wire Configuration

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PDK Kit Setup

7 PDK Kit Setup

CAUTION

Do not connect the ADS8860EVM-PDK to a PC before completing Section 7.

Failure to observe this caution may cause Microsoft Windows to disregard the

ADS8860EVM-PDK as a connected device.

This section presents the steps required to setup the ADS8860EVM-PDK kit before operation. Section 8

explains how to operate the kit to acquire and analyze data.

The steps to setup the kit are as follows and must be completed before attempting to capture data:

Step 1. Download and install the ADCPro software (if not already installed) on a PC.

Step 2. Download and install the ADS8860EVM-PDK EVM plug-in software.

Step 3. Configure the ADS8860EVM-PDK hardware.

Step 4. Power-up the ADS8860EVM-PDK.

Each task is described in the subsequent sections of this document.

7.1 Installing the ADCPro Software

ADCPro is the primary program used to evaluate the ADS8860. ADCPro is available at

www.ti.com/tool/adcpro. Refer to the ADCPro User's Guide (SBAU128) for detailed installation

instructions.

7.2 Installing ADS8860EVM-PDK Plug-In Software

NOTE: ADCPro should be installed before attempting to install the ADS8860EVM-PDK plug-in

software.

The installation file link for the PDK plug-in can be found in the ADS8860EVM-PDK product folder at

www.ti.com/tool/ADS8860evm-pdk. In the software section, look for a link with a file named ads886x-

adcproplugin-<version #>.exe (<version #> refers to the installation file version number, and increments

with software version releases). Download and double-click the file to run it; then follow the instructions as

shown.

Figure 6 shows the initial and completed installer screen shots.

Figure 6. Plug-In Installer

SBAU213–September 2013 ADS8860EVM-PDK

PDK Kit Setup

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7.3 Configuring the ADS8860EVM-PDK Hardware

The ADS8860EVM-PDK contains both the ADS8860EVM and the MMB0 motherboard; however, the

devices may be shipped unconnected or configured incorrectly. Follow these steps to verify that the

ADS8860EVM-PDK kit is properly configured and connected:

Step 1. Unpack the ADS8860EVM-PDK kit.

Step 2. Set J12 to closed, J13A to open, and J13B to closed on the MMB0, as shown in Figure 7.

• J12 must be closed. This setting allows the wall supply to power-up the MMB0 and

ADS8860EVM through J2 (6-VDC input), and regulate down to 5 V, 3.3 V.

• J13B must be closed. This setting connects the 5-V analog power supply with the 5-V

digital power supply.

• J13A must be opened. This setting allows the 5-V analog power supply to be regulated

on board.

Figure 7. MMB0 Motherboard Jumper Configuration

Step 3. Set JP1:2–3, JP2:2–3, JP3:open, and JP4:closed on the ADS8860EVM, as shown in

Figure 8.

Figure 8. ADS8860EVM Jumper Configuration

10 ADS8860EVM-PDK SBAU213–September 2013

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