Texas Instruments Bq24165EVM-720 Bedienungsanleitung

User's Guide

SLUU669–January 2012

QFN-Packaged bq24165/166/167EVM-720 Evaluation

Modules

The bq24165/166/167EVM-720 evaluation module is a complete charger module for evaluating a

compact, flexible, high-efficiency, USB-friendly, switch-mode, charge-management solution for single-cell,

Li-ion and Li-polymer batteries used in a wide range of portable applications.

Contents

1 Introduction .................................................................................................................. 2

1.1 bq2416x IC Features .............................................................................................. 2

1.2 bq24165/166/167EVM Features ................................................................................. 2

1.3 Schematic ........................................................................................................... 3

1.4 I/O Description ...................................................................................................... 3

1.5 Test Points .......................................................................................................... 4

1.6 Control and Key Parameters Setting ............................................................................ 4

1.7 Recommended Operating Conditions ........................................................................... 5

2 Test Summary ............................................................................................................... 5

2.1 Definitions ........................................................................................................... 5

2.2 Recommended Test Equipment ................................................................................. 6

2.3 Recommended Test Equipment Setup .......................................................................... 6

2.4 Recommended Test Procedure .................................................................................. 7

3 Printed-Circuit Board Layout Guideline .................................................................................. 8

4 Bill of Materials and Board Layout ...................................................................................... 10

4.1 Bill of Materials .................................................................................................... 10

4.2 Board Layout ...................................................................................................... 12

List of Figures

1 bq24165/166/167EVM (HPA720A) Schematic.......................................................................... 3

2 BAT_Load (PR1010E4) Schematic....................................................................................... 6

3 Original Test Setup for bq24165/166/167EVM (HPA720)............................................................. 7

4 Top Assembly Layer ...................................................................................................... 12

5 Top Layer .................................................................................................................. 13

6 Bottom Layer............................................................................................................... 14

7 First Internal Layer ........................................................................................................ 15

8 Second Internal Layer .................................................................................................... 16

List of Tables

1 Bill of Materials - HPA720A ............................................................................................. 10

SLUU669–January 2012 QFN-Packaged bq24165/166/167EVM-720 Evaluation Modules

Introduction

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1 Introduction

1.1 bq2416x IC Features

The bq24165/166/167 integrates a synchronous PWM controller, power MOSFETs, input current sensing,

high-accuracy current and voltage regulation, charge termination and power path management into a

chipscale package. Key integrated circuit (IC) features include:

• High-efficiency, fully integrated, NMOS-NMOS, synchronous buck charger with 1.5-MHz frequency

• Integrated power FETs for up to 2.5-A charge rate

• Power path management between battery and system voltages

For details, see the bq24165/166/167 data sheet (SLUSAP4).

1.2 bq24165/166/167EVM Features

The bq24165/166/167 evaluation module (EVM) is a complete charger module for evaluating compact,

flexible, high-efficiency, USB-friendly, switch-mode battery charge and power path management solution

for single-cell, Li-ion and Li-polymer battery-powered systems used in a wide range of portable

applications. Key EVM features include:

• Programmable charge current, input current on, and VINDPM threshold using jumpers

• Input power connectors for both USB input and ac adapter

• Programmable charge current, input current on, and VINDPM threshold using jumpers

• IN operating range of 4.2 V – 10 V

• USB operating range of 4.2 V – 6 V

• LED indication for status signals

• Test points for key signals available for testing purposes. Easy probe hook-up

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Introduction

1.3 Schematic

Figure 1. bq24165/166/167EVM (HPA720A) Schematic

1.4 I/O Description

Header/Terminal Block Description

J1-IN Adapter positive header

J2-IN Adapter positive terminal

J2-GND Adapter negative terminal

J3-GND Adapter negative header

J4-USB USB positive header

J5-SYS System output positive header

J6-USB USB positive terminal

J6-GND USB negative terminal

J7-SYS System output positive terminal

J7-GND System output negative terminal

J8-GND USB negative header

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Introduction

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Header/Terminal Block Description

J9-GND System output negative header

J10–BAT+ Battery positive header

J11-BAT+ Battery positive terminal

J11-GND Battery negative terminal

J12-GND Battery negative header

J13-DRV DRV reference voltage positive header

J14-DRV DRV reference voltage positive terminal

J14-GND DRV reference voltage negative terminal

J15-GND DRV reference voltage negative header

J16–TS External thermistor positive terminal

J16–GND Ground connection for external thermistor

1.5 Test Points

Test Point Description

TP1 Kelvin to IN

TP2 Kelvin to USB

TP3 SW

TP4 Kelvin to SYS

TP5 GND

TP6 GND

TP7 IUSB3

TP8 Kelvin to BAT

TP9 IUSB1

TP10 IUSB2

TP11 ISET

TP12 ILIM

TP13 CE2 for bq24165 or TS for bq24166/167

TP14 CE1 for bq24165 or CE for bq24166/167

1.6 Control and Key Parameters Setting

Jump Default Factory

IC Description

er Setting

1-2: FET GATE = BGATE: External PFET's gate tied to BGATE pin and therefore

controlled by the integrated circuit (IC). 1-2 (FET GATE =

All JP1 2-3: FET GATE = SYS: External PFET's gate tied to SYS and therefore disabled. BGATE)

It is recommended that this jumper be changed only when the device is not enabled or in

Hi-Z mode so that the PFET's gate is never left open.

1-2: CE1 = HI: Active-low enable for reduced VBAT voltage (if CE2 = LO) or suspended

charging (if CE2 = HI)

bq24165 JP2 2-3 (CE1 = LO)

2-3: CE1 = LO: Active-low enable for full current charging (if CE2 = LO) or charging at

half current (if CE2 = HI)

bq24166 1-2: CE = HI: Active-low charge enable high to disable charge and enter Hi-Z mode

JP2 2-3 (CE = LO)

bq24167 2-3: CE = LO: Active-low charge enable low for normal operation

1-2: IUSB3 = HI

2-3: IUSB3 = LO

All JP3 2-3 (IUSB3 = LO)

See data sheet Table 1 for description of USB input current limit and VINDPM threshold

setting. Default setting is for 500-mA input current limit and 4.68-V threshold.

1-2: IUSB2 = HI

2-3: IUSB2 = LO

All JP4 2-3 (IUSB2 = LO)

See data sheet Table 1 for description of USB input current limit and VINDPM threshold

setting. Default setting is for 500-mA input current limit and 4.68-V threshold.

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Test Summary

Jump Default Factory

IC Description

er Setting

1-2: IUSB1 = HI

2-3: IUSB1 = LO

All JP5 1-2 (IUSB1 = HI)

See data sheet Table 1 for description of USB input current limit and VINDPM threshold

setting. Default setting is for 500-mA input current limit and 4.68-V threshold.

1-2 (CE2 = HI): Active-low enable for charging at half current (if CE1 = LO) or

suspended charging (if CE1 = HI)

bq24165 JP6 2-3 (CE2 = LO)

2-3 (CE2 = LO): Active-low enable for full current charging (if CE1 = LO) or reduced

VBAT voltage (if CE1 = HI)

1-2 (TS = EXT or TS floating): Connects the TS pin to an external thermistor. The

resistor divider formed by R1 and R3 has been sized to accommodate a 10-kΩ

bq24166 thermistor. If a different thermistor is used, R1 and R3 need to be resized.

JP6 2-3 (TS = INT)

bq24167 2-3 (TS = NT): Connects a potentiometer to the TS so the potentiometer can emulate a

thermistor. The potentiometer has been preset to approximately 3.4 kΩso that the TS

voltage is 0.5 x V(DRV).

1.7 Recommended Operating Conditions

Min Typ Max Unit

Supply voltage, VIN Operating input voltage from ac adapter 4.2 10 V

USB voltage, VUSB Operating input voltage from USB or equivalent supply 4.2 6 V

Battery voltage, VBAT Voltage applied at VBAT terminal (depends on status of CE1 4.02 4.2 4.24 V

and CE2)

System voltage, VSYS Voltage output at SYS terminal (depends on VBAT voltage 3.4 4.37 V

and status of VINDPM)

Supply current, IIN(MAX) Maximum input current limit for ac adapter input (set by 1.5 2.5 A

user-selectable resistor)

Supply current, IUSB(MAX) Maximum input current limit for USB input (set by USBx 0.1 0.5 1.5 A

input pins)

Charge current, Ichrg Battery charge current 0.550 2.5 A

Operating junction temperature range, TJ0 125 °C

2 Test Summary

This procedure describes one test configuration of the HPA720 evaluation board for bench evaluation. An

electronic load is used to simulate a battery.

2.1 Definitions

The following naming conventions are followed.

VXXX : External voltage supply name (VADP, VBT, VSBT)

LOADW: External load name (LOADR, LOADI)

V(TPyyy): Voltage at internal test point TPyyy. For example, V(TP12) means the voltage at

TP12.

V(Jxx): Voltage at header Jxx

V(TP(XXX)): Voltage at test point XXX. For example, V(ACDET) means the voltage at the test

point which is marked as ACDET.

V(XXX, YYY): Voltage across point XXX and YYY.

I(JXX(YYY)): Current going out from the YYY terminal of header XX.

Jxx(BBB): Terminal or pin BBB of header xx

JPx ON : Internal jumper Jxx terminals are shorted.

JPx OFF: Internal jumper Jxx terminals are open.

JPx (-YY-) ON: Internal jumper Jxx adjacent terminals marked as YY are shorted.

SLUU669–January 2012 QFN-Packaged bq24165/166/167EVM-720 Evaluation Modules

Test Summary

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Measure: →A,B Check specified parameters A, B. If measured values are not within specified limits,

the unit under test has failed.

Observe →A,B Observe if A, B occur. If they do not occur, the unit under test has failed.

Assembly drawings have location for jumpers, test points, and individual components.

2.2 Recommended Test Equipment

2.2.1 Power Supplies

1. Power Supply #1 (PS#1) capable of supplying 6 V at 3 A is required.

2. If not using a battery as the load, then power supply #2 (PS#2) capable of supplying up to 5 V at 5 A is

required to power the circuit shown in Figure 2.

2.2.2 Load #1 between BAT and GND

Testing with an actual battery is the best way to verify operation in the system. If a battery is unavailable,

then a circuit similar to the one shown in Figure 2 can simulate a battery when connected to a second

power supply.

Figure 2. BAT_Load (PR1010E4) Schematic

2.2.3 Load #2 Between SYS and GND

Although not required, a resistive load capable of sinking up to 3 A can be used.

2.2.4 Meters

Four equivalent voltage meters (VM#) and two equivalent current meters (CM#). The current meters must

be able to measure a 3-A current.

2.3 Recommended Test Equipment Setup

1. For all power connections, use short, twisted-pair wires of appropriate gauge wire for the amount of the

current.

2. Set Power Supply #1 for 6 V ± 100 mVdc, 3 A ± 100-mA current limit, and then turn off supply.

3. If BAT_Load (PR1010) as shown in Figure 2 is used, connect Power Supply #2 (PS#2) set to

approximately 2.5 V to the input side (PS#2+/-) of BAT_Load (PR1010), and then turn off PS#2.

4. Connect the output side of the battery or BAT_Load (PR1010) in series with current meter (multimeter)

#2 (CM#2) to J11 (BAT, GND). Ensure that a voltage meter is connected across J10 or TP8 and J12

or TP6 (BAT, GND).

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PR1010

VM#2CM#2

ICHRG

PS#1

VM#3

CM#1

IIN

+ -

VM#1

VM#4

V+

PS#2

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Test Summary

5. Connect VM#3 across J5 or TP4 and J9 (SYS, GND).

6. Connect VM#4 across J13 and J15 (DRV, GND).

7. Ensure jumpers are at the default factory settings per Section 1.6

8. After the preceding steps, the test setup for HPA720 is as shown in Figure 3

Figure 3. Original Test Setup for bq24165/166/167EVM (HPA720)

2.4 Recommended Test Procedure

The following test procedure is useful for evaluating the charger IC outside of a real system, if no battery

is available to connect to the output and a simulated battery is needed.

2.4.1 Charge Voltage and Current Regulation of IN

1. Ensure that the Section 2.3 steps are followed.

2. Move JP2 (CE1 or CE) = HI and JP6 = HI.

3. Connect the output of Power Supply #1 (PS#1) in series with current meter #1 (CM#1) to J2 (IN,

GND).

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Printed-Circuit Board Layout Guideline

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4. Connect voltage meter #1 (VM#1) across J1 or TP1 and J3 or TP6 (IN, GND).

5. With PS#2 disabled, turn on PS#1.

6. Move JP2 (CE1 or CE) = LO and JP6 = LO.

7. Enable PS#2 and slowly increase the PS#2 voltage, so that the voltage measured on VM#2, across

BAT and GND, rises from 2.5V, until

Measure on CM#2→ICHRG = 2500 mA ± 150 mA

Observe →D1 and D2 are on.

8. Adjust the power supply so that VM#1 still reads 6 V ± 100 mV, if necessary, until

Measure on CM#1 →IIN < 2100 mA.

9. Turn off PS#1 and PS#2.

2.4.2 Charge Voltage and Current Regulation of USB

1. Ensure that the Section 2.3 steps are followed.

2. Move JP2 (CE1 or CE) = HI and JP6 = HI.

3. Connect the output of Power Supply #1 (PS#1) in series with current meter (multimeter) #1 (CM#1) to

J4 and J8 or J6 (USB, GND).

4. Connect voltage meter 1 (VM#1) across J4 or TP2 and J8 or TP5 (USB, GND).

5. With PS#2 disabled, turn on PS#1.

6. Move JP2 (CE1 or CE) = LO and JP6 = LO while keeping the default settings for JP3 (USB3), JP4

(USB2), and JP5 (USB1).

7. Enable PS#2 and adjust PS#2 so that the voltage measured by VM#2, across BAT and GND,

measures > 3.2 V but < 4.2 V.

8. Adjust PS#1 so that VM#1 still reads 6 V ± 100 mV, if necessary.

9. Measure and Observe:

Measure on CM#2→ICHRG > 650 mA

Measure on CM#1 →IIN = 475 mA ± 30 mA

Observe →D1 and D2 are on.

10. Turn off PS#1 and PS#2.

2.4.3 Helpful hints

1. To observe the taper current as the battery voltage approaches the set regulation voltage, allow the

battery to charge or, if using BAT_Load (PR1010), slowly increase the PS#2 voltage powering

BAT_Load (PR1010). Use VM#2 across BAT and GND to measure the battery voltage sensed by the

IC.

2. To observe the VINDPM function, lower the current limit on PS#1.

3. To observe battery supplement mode, apply a resistive load across SYS and GND that is higher than

the maximum charge current.

3 Printed-Circuit Board Layout Guideline

1. To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND,

must be placed as close as possible to the bq2416x.

2. Place 4.7-µF input capacitor as close to PMID pin and PGND pin as possible to make the high-

frequency, current-loop area as small as possible. Place 1-µF input capacitor GNDs as close to the

respective PMID capacitor GND and PGND pins as possible to minimize the ground difference

between the input and PMID_.

3. The local bypass capacitor from SYS to GND must be connected between the SYS pin and PGND of

the IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and

back to the PGND pin.

4. Place all decoupling capacitors close to their respective IC pins and as close as possible to PGND (do

not place components such that routing interrupts power stage currents). All small control signals must

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Printed-Circuit Board Layout Guideline

be routed away from the high-current paths.

5. The printed-circuit board (PCB) must have a ground plane (return) connected directly to the return of

all components through vias (two vias per capacitor for power-stage capacitors, one via per capacitor

for small-signal components). It is also recommended to put vias inside the PGND pads for the IC, if

possible. A star ground design approach is typically used to keep circuit block currents isolated (high-

power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single

ground plane for this design gives good results. With this small layout and a single ground plane, no

ground-bounce issue occurs, and having the components segregated minimizes coupling between

signals.

6. The high-current charge paths into IN, USB, BAT, SYS, and from the SW pins must be sized

appropriately for the maximum charge current in order to avoid voltage drops in these traces. The

PGND pins must be connected to the ground plane to return current through the internal low-side FET.

7. For high-current applications, the balls for the power paths must be connected to as much copper in

the board as possible. This allows better thermal performance because the board conducts heat away

from the IC.

SLUU669–January 2012 QFN-Packaged bq24165/166/167EVM-720 Evaluation Modules

Bill of Materials and Board Layout

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4 Bill of Materials and Board Layout

4.1 Bill of Materials

Table 1. Bill of Materials - HPA720A

Count RefDes Value Description Size Part Number MFR

-001 -002 -003

0 0 0 C1, C6 Open Capacitor, Ceramic 805 Std Std

2 2 2 C2, C7 1.0uF Capacitor, Ceramic, 25V, X5R, 10% 603 Std Std

2 2 2 C3, C8 4.7uF Capacitor, Ceramic, 25V, X5R, 10% 805 Std Std

1 1 1 C4 10uF Capacitor, Ceramic, 10V, X5R, 20% 603 Std Std

0 0 0 C5 47uF Capacitor, Ceramic 805 Std Std

1 1 1 C9 0.01uF Capacitor, Ceramic, 16V, X7R, 10% 603 Std Std

0 0 0 C10 47uF Capacitor, Ceramic 1206 Std Std

2 2 2 C11, C12 1.0uF Capacitor, Ceramic, 6.3V, X5R, 10% 402 Std Std

2 2 2 D1, D2 LTST-C190GKT Diode, LED, Green, 2.1-V, 20-mA, 6-mcd 603 LTST-C190GKT Liteon

1 1 1 D3 BAT54C Diode, Dual Schottky, 200-mA, 30-V SOT23 BAT54C Fairchild

10 10 10 J1, J3, J4, J5, J8, J9, J10, PEC02SAAN Header, Male 2-pin, 100mil spacing, 0.100 inch x 2 PEC02SAAN Sullins

J12, J13, J15

5 5 5 J2, J6, J7, J11, J14 ED555/2DS Terminal Block, 2-pin, 6-A, 3.5mm 0.27 x 0.25 ED555/2DS OST

0 1 1 J16 ED555/2DS Terminal Block, 2-pin, 6-A, 3.5mm 0.27 x 0.25 ED555/2DS OST

6 6 6 JP1, JP2, JP3, JP4, JP5, PEC03SAAN Header, Male 3-pin, 100mil spacing, 0.100 inch x 3 PEC03SAAN Sullins

JP6

1 1 1 L1 1.5uH Inductor, SMT, 3.5A, 70 mΩ4.1x4.4 mm SPM4012T-1R5M TDK Alternate: Toko

Alternate: FDSD0415-

H-1R5M

1 1 1 Q1 CSD25401Q3 MOSFET, PChan, -20V, 60A, 8.7 mΩQFN3.3X3.3mm CSD25401Q3 TI

1 1 1 R1 300kΩResistor, Chip, 1/16W, 1% 603 Std Std

1 1 1 R2 100ΩResistor, Chip, 1/16W, 1% 402 Std Std

1 1 1 R3 100kΩResistor, Chip, 1/16W, 1% 603 Std Std

0 1 1 R4 1870ΩResistor, Chip, 1/16W, 1% 603 Std Std

0 1 1 R5 4120ΩResistor, Chip, 1/16W, 1% 603 Std Std

1 1 1 R6 196ΩResistor, Chip, 1/16W, 1% 402 Std Std

2 2 2 R7, R8 1.50kΩResistor, Chip, 1/16W, 1% 603 Std Std

0 1 1 R9 50.0kΩPotentiometer, 3/8 Cermet, 12-Turn 0.25x0.17 inch 3266W-1-503LF Bourns

2 0 0 R10, R11 0 Resistor, Chip, 1/16W 603 Std Std

14 14 14 TP1, TP2, TP3, TP4, TP7, 5002 Test Point, White, Thru Hole Color Keyed 0.100 x 0.100 inch 5002 Keystone

TP8, TP9, TP10, TP11,

TP12, TP13, TP14, TP15,

TP16

2 2 2 TP5, TP6 5001 Test Point, Black, Thru Hole Color Keyed 0.100 x 0.100 inch 5001 Keystone

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