Texas Instruments SPRU938B Bedienungsanleitung

TMS320DM643x DMPVLYNQ Port

User's Guide

Literature Number: SPRU938BSeptember 2007

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Contents

Preface ............................................................................................................................... 71 Introduction ................................................................................................................ 81.1 Purpose of the Peripheral ....................................................................................... 81.2 Features ........................................................................................................... 81.3 Functional Block Diagram ....................................................................................... 91.4 Industry Standard(s) Compliance Statement ................................................................. 92 Peripheral Architecture .............................................................................................. 102.1 Clock Control .................................................................................................... 102.2 Signal Descriptions ............................................................................................. 112.3 Pin Multiplexing ................................................................................................. 112.4 Protocol Description ............................................................................................ 112.5 VLYNQ Functional Description ............................................................................... 122.6 Initialization ...................................................................................................... 152.7 Auto-Negotiation ................................................................................................ 152.8 Address Translation ............................................................................................ 162.9 Flow Control ..................................................................................................... 192.10 Reset Considerations .......................................................................................... 202.11 Interrupt Support ................................................................................................ 202.12 EDMA Event Support .......................................................................................... 222.13 Power Management ............................................................................................ 232.14 Endianness Considerations ................................................................................... 232.15 Emulation Considerations ..................................................................................... 233 VLYNQ Port Registers ................................................................................................ 243.1 Revision Register (REVID) .................................................................................... 253.2 Control Register (CTRL) ....................................................................................... 263.3 Status Register (STAT) ........................................................................................ 283.4 Interrupt Priority Vector Status/Clear Register (INTPRI) .................................................. 303.5 Interrupt Status/Clear Register (INTSTATCLR) ............................................................ 303.6 Interrupt Pending/Set Register (INTPENDSET) ............................................................ 313.7 Interrupt Pointer Register (INTPTR) ......................................................................... 313.8 Transmit Address Map Register (XAM)...................................................................... 323.9 Receive Address Map Size 1 Register (RAMS1) .......................................................... 333.10 Receive Address Map Offset 1 Register (RAMO1) ........................................................ 333.11 Receive Address Map Size 2 Register (RAMS2) .......................................................... 343.12 Receive Address Map Offset 2 Register (RAMO2) ........................................................ 343.13 Receive Address Map Size 3 Register (RAMS3) .......................................................... 353.14 Receive Address Map Offset 3 Register (RAMO3) ........................................................ 353.15 Receive Address Map Size 4 Register (RAMS4) .......................................................... 363.16 Receive Address Map Offset 4 Register (RAMO4) ........................................................ 363.17 Chip Version Register (CHIPVER) ........................................................................... 373.18 Auto Negotiation Register (AUTNGO) ....................................................................... 374 Remote Configuration Registers ................................................................................. 38Appendix A VLYNQ Protocol Specifications ........................................................................ 39A.1 Introduction ...................................................................................................... 39

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A.2 Special 8b/10b Code Groups ................................................................................. 39A.3 Supported Ordered Sets ....................................................................................... 39A.4 VLYNQ 2.0 Packet Format .................................................................................... 40A.5 VLYNQ 2.X Packets ............................................................................................ 42Appendix B Write/Read Performance .................................................................................. 44B.1 Introduction ...................................................................................................... 44B.2 Write Performance.............................................................................................. 44B.3 Read Performance ............................................................................................. 46Appendix C Revision History ............................................................................................. 47

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List of Figures

1 VLYNQ Port Functional Block Diagram ................................................................................... 92 External Clock Block Diagram ............................................................................................ 103 Internal Clock Block Diagram ............................................................................................. 104 VLYNQ Module Structure ................................................................................................. 125 Write Operations ........................................................................................................... 136 Read Operations ........................................................................................................... 147 Example Address Memory Map .......................................................................................... 178 Interrupt Generation Mechanism Block Diagram ....................................................................... 219 Revision Register (REVID) ................................................................................................ 2510 Control Register (CTRL) ................................................................................................... 2611 Status Register (STAT) .................................................................................................... 2812 Interrupt Priority Vector Status/Clear Register (INTPRI) .............................................................. 3013 Interrupt Status/Clear Register (INTSTATCLR) ........................................................................ 3014 Interrupt Pending/Set Register (INTPENDSET) ........................................................................ 3115 Interrupt Pointer Register (INTPTR) ..................................................................................... 3116 Transmit Address Map Register (XAM) ................................................................................. 3217 Receive Address Map Size 1 Register (RAMS1) ...................................................................... 3318 Receive Address Map Offset 1 Register (RAMO1) .................................................................... 3319 Receive Address Map Size 2 Register (RAMS2) ...................................................................... 3420 Receive Address Map Offset 2 Register (RAMO2) .................................................................... 3421 Receive Address Map Size 3 Register (RAMS3) ...................................................................... 3522 Receive Address Map Offset 3 Register (RAMO3) .................................................................... 3523 Receive Address Map Size 4 Register (RAMS4) ...................................................................... 3624 Receive Address Map Offset 4 Register (RAMO4) .................................................................... 3625 Chip Version Register (CHIPVER) ....................................................................................... 3726 Auto Negotiation Register (AUTNGO) ................................................................................... 37A-1 Packet Format (10-bit Symbol Representation) ........................................................................ 40

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List of Tables

1 VLYNQ Signal Descriptions ............................................................................................... 112 Address Translation Example (Single Mapped Region) .............................................................. 173 Address Translation Example (Single Mapped Region) .............................................................. 184 VLYNQ Register Address Space ......................................................................................... 245 VLYNQ Port Controller Registers ........................................................................................ 246 Revision Register (REVID) Field Descriptions ......................................................................... 257 Control Register (CTRL) Field Descriptions ............................................................................ 268 Status Register (STAT) Field Descriptions ............................................................................. 289 Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions ........................................ 3010 Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions .................................................. 3011 Interrupt Pending/Set Register (INTPENDSET) Field Descriptions ................................................. 3112 Interrupt Pointer Register (INTPTR) Field Descriptions ............................................................... 3113 Address Map Register (XAM) Field Descriptions ...................................................................... 3214 Receive Address Map Size 1 Register (RAMS1) Field Descriptions ................................................ 3315 Receive Address Map Offset 1 Register (RAMO1) Field Descriptions .............................................. 3316 Receive Address Map Size 2 Register (RAMS2) Field Descriptions ................................................ 3417 Receive Address Map Offset 2 Register (RAMO2) Field Descriptions .............................................. 3418 Receive Address Map Size 3 Register (RAMS3) Field Descriptions ................................................ 3519 Receive Address Map Offset 3 Register (RAMO3) Field Descriptions .............................................. 3520 Receive Address Map Size 4 Register (RAMS4) Field Descriptions ................................................ 3621 Receive Address Map Offset 4 Register (RAMO4) Field Descriptions .............................................. 3622 Chip Version Register (CHIPVER) Field Descriptions................................................................. 3723 Auto Negotiation Register (AUTNGO) Field Descriptions ............................................................ 3724 VLYNQ Port Remote Controller Registers .............................................................................. 38A-1 Special 8b/10b Code Groups ............................................................................................. 39A-2 Supported Ordered Sets .................................................................................................. 39A-3 Packet Format (10-bit Symbol Representation) Description .......................................................... 41B-1 Scaling Factors ............................................................................................................. 45B-2 Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ) .................................... 45B-3 Relative Performance with Various Latencies .......................................................................... 46C-1 Document Revision History ............................................................................................... 47

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PrefaceSPRU938B – September 2007

Read This First

About This Manual

This document describes the VLYNQ port in the TMS320DM643x Digital Media Processor (DMP).

Notational Conventions

This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM643x Digital Media Processor (DMP). Copies of thesedocuments are available on the Internet at www.ti.com .Tip: Enter the literature number in the search boxprovided at www.ti.com.

The current documentation that describes the DM643x DMP, related peripherals, and other technicalcollateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .

SPRU978 —TMS320DM643x DMP DSP Subsystem Reference Guide. Describes the digital signalprocessor (DSP) subsystem in the TMS320DM643x Digital Media Processor (DMP).

SPRU983 —TMS320DM643x DMP Peripherals Overview Reference Guide. Provides an overview andbriefly describes the peripherals available on the TMS320DM643x Digital Media Processor (DMP).

SPRAA84 —TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from theTexas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. Theobjective of this document is to indicate differences between the two cores. Functionality in thedevices that is identical is not included.

SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.

SPRU871 —TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digitalsignal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.Trademarks

VLYNQ is a trademark of Texas Instruments.

SPRU938B – September 2007 Preface 7Submit Documentation Feedback

1 Introduction

1.1 Purpose of the Peripheral

1.2 Features

User's GuideSPRU938B – September 2007

VLYNQ Port

The VLYNQ™ communications interface port is a low pin count, high-speed, point-to-point serial interfacein the TMS320DM643x Digital Media Processor (DMP) used for connecting to host processors and otherVLYNQ compatible devices. The VLYNQ port is a full-duplex serial bus where transmit and receiveoperations occur separately and simultaneously without interference.

VLYNQ enables the extension of an internal bus segment to one or more external physical devices. Theexternal devices are mapped to local physical address space and appear as if they are on the internal busof the DM643x DMP. The external devices must also have a VLYNQ interface.

VLYNQ uses a simple block code (8b/10b) packet format and supports in-band flow control so that noextra terminals are needed to indicate that overflow conditions might occur.

The VLYNQ module on the DM643x DMP serializes a write transaction to the remote/external device andtransfers the write via the VLYNQ port (TX pins). The remote VLYNQ module deserializes the transactionon the other side.

The read transactions to the remote/external device follow the same process, but the remote device'sVLYNQ module serializes the read return data and transfers it to the VLYNQ port (RX pins). The readreturn data is finally deserialized and released to the device internal bus.

The external device can also initiate read and write transactions.

The general features of the VLYNQ port are:•Low pin count (10 pin interface, scalable to as low as 3 pins)•No tri-state signals– All signals are dedicated and driven by only one device– Necessary to allow support for high-speed PHYs•Simple packet-based transfer protocol for memory-mapped access– Write request/data packet– Read request packet– Read response data packet– Interrupt request packet•Auto width negotiation

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1.3 Functional Block Diagram

Slave

config

bus

Interface

Master

config

Interface

bus

VLYNQ module

VLYNQ register

access

CPU/EDMA initiated

transfers to

remote device

Off chip

(remote)

device access

System

CPU/EDMA

memory

System

VLYNQ_SCRUN

VLYNQ_CLOCK

VLYNQ_RXD[3:0]

VLYNQ_TXD[3:0]

INT55

interrupt controller

VLQINT

1.4 Industry Standard(s) Compliance Statement

Introduction

•Symmetric Operations– Transmit (TX) pins on the first device connect to the receive (RX) pins on the second device andvice-versa.

– Data pin widths are automatically detected after reset– Re-request packets, response packets, and flow control information are all multiplexed and sentacross the same physical pins.– Supports both host/peripheral and peer-to-peer communication models•Simple block code packet formatting (8b/10b)•Supports in-band and flow control– No extra pins are needed– Allows the receiver to momentarily throttle the transmitter back when overflow is about to occur– Uses the special built-in block code capability to interleave flow control information seamlessly withuser data•Automatic packet formatting optimizations•Internal loopback modes are provided•Connects to legacy VLYNQ devices

Figure 1 shows a functional block diagram of the VLYNQ port.

Figure 1. VLYNQ Port Functional Block Diagram

VLYNQ is an interface defined by Texas Instruments and does not conform to any other industry standard.

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2 Peripheral Architecture

2.1 Clock Control

VLYNQ

CLKDIR=0

DMxxx device

VLYNQ_CLK

VLYNQ

CLKDIR=0

VLYNQ device

VLYNQ CLKDIR=1

DMxxx device

VLYNQ_CLK

VLYNQ

CLKDIR=1

VLYNQ device

VLYNQ

internal

sys clk Don’t

care

Peripheral Architecture

This section discusses the architecture and basic functions of the VLYNQ peripheral.

The module's serial clock direction and frequency are software configurable through the CLKDIR andCLKDIV bits in the VLYNQ control register (CTRL). The VLYNQ serial clock can be sourced from theinternal system clock (CLKDIR = 1) or by an external clock source (CLKDIR = 0) for its serial operations.

The CLKDIV bit can divide the serial clock (1/1 - 1/8) down when the internal clock is selected as thesource. The serial clock is not affected by the CLKDIV bit values, if the serial clock is externally sourced.

The reset value of the CLKDIR bit is 0 (external clock source).

The external clock source is shown in Figure 2 . The internal clock source is shown in Figure 3 .

Figure 2. External Clock Block Diagram

Figure 3. Internal Clock Block Diagram

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