Xilinx Virtex-4 QV FPGA Bedienungsanleitung

Virtex-4 QV

FPGA Ceramic

Packaging and

[Guide Subtitle]

[optional]

UG496 (v1.1) June 8, 2012 [optional]

Virtex-4 QV FPGA

Ceramic Packaging and

Pinout Specifications

UG496 (v1.1) June 8, 2012

Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012

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Revision History

The following table shows the revision history for this document.

Date Version Revision

04/02/08 1.0 Initial Xilinx release.

06/08/12 1.1 Added Chapter 6, “Guidelines for Xilinx CF Package Handling and Assembly.”

Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com 3

UG496 (v1.1) June 8, 2012

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 1: Device Packaging Overview

Device/Package Combinations and Available I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 2: Pinout Tables

CF1140 (SX55) Ceramic Flip-Chip Column Grid Package . . . . . . . . . . . . . . . . . . . . . 15

CF1144 (FX60) Ceramic Flip-Chip Column Grid Package . . . . . . . . . . . . . . . . . . . . . 47

CF1509 (FX140) Ceramic Flip-Chip Column Grid Package . . . . . . . . . . . . . . . . . . . . 79

CF1509 (LX200) Ceramic Flip-Chip Column Grid Package . . . . . . . . . . . . . . . . . . . 120

Chapter 3: Pinout Diagrams

CF1140 Package Pinout Diagram (SX55). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

CF1140 Color-Coded SelectIO Interface and Bank Information . . . . . . . . . . . . . . 163

CF1144 Package Pinout Diagram (FX60). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

CF1144 Color-Coded SelectIO Interface and Bank Information . . . . . . . . . . . . . . 165

CF1509 Package Pinout Diagram (LX200) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

CF1509 Color-Coded SelectIO Interface and Bank Information . . . . . . . . . . . . . . 167

CF1509 Package Pinout Diagram (FX140). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

CF1509 Color-Coded SelectIO Interface and Bank Information . . . . . . . . . . . . . . 169

Chapter 4: Mechanical Drawings

CF1140 Ceramic Flip-Chip Column Grid Package Specifications . . . . . . . . . . . . 172

CF1144 Ceramic Flip-Chip Column Grid Package Specifications . . . . . . . . . . . . 173

CF1509 Ceramic Flip-Chip Column Grid Package Specifications . . . . . . . . . . . . 174

Chapter 5: Thermal Specifications

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

CF Package Construction and Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Thermal Resistance and Package Mass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table of Contents

4www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging

UG496 (v1.1) June 8, 2012

Chapter 6: Guidelines for Xilinx CF Package Handling and Assembly

Product Unpacking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Product Handling and Inspection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Board Level Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com 5

UG496 (v1.1) June 8, 2012

Preface

About This Guide

This guide provides complete packing information for Virtex®-4 QPro™-V (QV)

Radiation-Hardened FPGAs in 1.00-mm pitch ceramic flip-chip column grid array (CF)

packages. Virtex-4 QV Radiation Hardened FPGAs are offered exclusively in ceramic flip-

chip column grid array (CF) packages that are optimally designed for improved thermal

cycle reliability.

Guide Contents

This manual contains the following chapters:

•Chapter 1, “Device Packaging Overview,” provides an introduction to the Virtex-4 QV

family with a summary of maximum I/Os available in each device/package

combination. Also includes table of pin definitions.

•Chapter 2, “Pinout Tables,” provides pinout information for all Virtex-4 QV

Radiation-Hardened FPGAs.

•Chapter 3, “Pinout Diagrams,” provides pinout diagrams for all Virtex-4 QV

Radiation-Hardened package/device combinations.

•Chapter 4, “Mechanical Drawings,” provides mechanical drawings of all Virtex-4 QV

Radiation-Hardened FPGAs.

•Chapter 5, “Thermal Specifications,” provides thermal data associated with Virtex-4

QV Radiation-Hardened FPGA packaging. Discusses Virtex-4 QV FPGA power

management strategy and thermal management options.

Additional Resources

To find additional documentation, see the Xilinx website at:

http://www.xilinx.com/literature.

To search the Answer Database of silicon, software, and IP questions and answers, or to

create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support.

6www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging

UG496 (v1.1) June 8, 2012

Preface: About This Guide

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

Convention Meaning or Use Example

Courier font

Messages, prompts, and

program files that the system

displays

speed grade: - 100

Courier bold Literal commands that you enter

in a syntactical statement ngdbuild design_name

Helvetica bold

Commands that you select from

a menu File ∅Open

Keyboard shortcuts Ctrl+C

Italic font

Variables in a syntax statement

for which you must supply

values

ngdbuild design_name

References to other manuals

See the Development System

Reference Guide for more

information.

Emphasis in text

If a wire is drawn so that it

overlaps the pin of a symbol, the

two nets are not connected.

Square brackets [ ]

An optional entry or parameter.

However, in bus specifications,

such as bus[7:0], they are

required.

ngdbuild [option_name]

design_name

Braces { } A list of items from which you

must choose one or more lowpwr ={on|off}

Vertical bar | Separates items in a list of

choices lowpwr ={on|off}

Vertical ellipsis

Repetitive material that has

been omitted

IOB #1: Name = QOUT’

IOB #2: Name = CLKIN’

Horizontal ellipsis . . . Repetitive material that has

been omitted

allow block block_name loc1

loc2 ... locn;

Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com 7

UG496 (v1.1) June 8, 2012

Conventions

Online Document

The following conventions are used in this document:

Convention Meaning or Use Example

Blue text Cross-reference link to a location

in the current document

See the section “Additional

Resources” for details.

Refer to “Title Formats” in

Chapter 1 for details.

Red text Cross-reference link to a location

in another document

See Figure 2-5 in the Virtex-II

Platform FPGA User Guide.

Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com

for the latest speed files.

8www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging

UG496 (v1.1) June 8, 2012

Preface: About This Guide

Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com 9

UG496 (v1.1) June 8, 2012

Chapter 1

Device Packaging Overview

This section describes the pinouts for Virtex-4 QV Radiation Hardened FPGAs in 1.00-mm

pitch ceramic flip-chip column grid array (CF) packages. Virtex-4 QV Radiation Hardened

FPGAs are offered exclusively in ceramic flip-chip column grid array (CF) packages that are

optimally designed for improved thermal cycle reliability. All of these packages are pinout

compatible with a commercial grade equivalent BGA (Table 1-1).

Each device I/O ring is split into eight or more I/O banks to allow for flexibility in the

choice of I/O standards (see UG070,Virtex-4 User Guide). Global pins, including JTAG,

configuration, and power/ground pins, are listed at the end of each table. Table 1-3

provides the definitions for all pin types.

Note: Check www.xilinx.com for the latest pinout information.

Device/Package Combinations and Available I/Os

Table 1-1 lists the available CF packages and their pin compatible flip-chip packages.

Table 1-2 lists the number of available I/Os and differential I/O pairs for each Virtex-4 QV

FPGA. The number of I/Os per package includes all user I/Os except the fifteen control

pins (CCLK, DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO, TMS,

HSWAPEN, DXN, DXP, AND RSVD).

Table 1-1: Ceramic Flip-Chip Packages and Compatible BGA

Ceramic Package CF1140 CF1144 CF1509

Pitch 1.00 mm 1.00 mm 1.00 mm

Size 35 mm ×35 mm 35 mm ×35 mm 40 mm ×40 mm

Compatible BGA

XQR4VSX55 FF1148

XQR4VFX60 FF1152

XQR4VFX140 FF1517

XQR4VLX200 FF1513

10 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging

UG496 (v1.1) June 8, 2012

Chapter 1: Device Packaging Overview

Pin Definitions

Table 1-3 provides a description of each pin type listed in Virtex-4 QV FPGA pinout tables.

The "_#" suffix appended to some pin descriptions indicates the bank in which that pin

resides. Pins without this suffix appended are not associated with any particular bank.

Note: RocketIO™transceivers are not supported for Virtex-4 QV FPGAs.

Table 1-2: Virtex-4 QV FPGA Available I/Os per Device/Package Combination

Virtex-4 QV

Device User and Differential

I/Os Virtex-4 QV CF Package

CF1140 CF1144 CF1509

XQR4VSX55 Available User I/Os 640

Differential I/O Pairs 320

XQR4VFX60 Available User I/Os 576

Differential I/O Pairs 288

XQR4VFX140 Available User I/Os 768

Differential I/O Pairs 384

XQR4VLX200 Available User I/Os 960

Differential I/O Pairs 480

Table 1-3: Virtex-4 QPro FPGA Pin Definitions

Pin Name Direction Description

User I/O Pins

IO_LXXY_# Input/Output

All user I/O pins are capable of differential signalling and can implement

LVDS, LVDSEXT, ULVDS, BLVDS, LVPECL, or LDT pairs. Each user I/O is

labeled “IO_LXXY_#”, where:

IO indicates a user I/O pin.

LXXY indicates a differential pair, with XX a unique pair in the bank and Y

= [P|N] for the positive/negative sides of the differential pair.

Multi-Function Pins

IO_LXXY_ZZZ_# Multi-function pins are labelled “IO_LXXY_ZZZ_#”, where ZZZ represents

one or more of the functions described below.

For a given multi-function pin, ZZZ is one or more of the following:

ADCn Input/Output ADC1 through ADC7 input pins are reserved for future use but can be

used for I/O or other designated functions.

Dn Input/Output In SelectMAP mode, D0 through D31 are configuration data pins. These pins

become user I/Os after configuration, unless the SelectMAP port is retained.

CC(2) Input/Output

These lower capacitance clock pins connect to Clock Capable I/Os. These

pins do not support LVDS outputs, and they become regular user I/Os

when not needed for clocks.

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