BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY
BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)(not used)(not used)(not used)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved) (reserved)
(reserved)
(reserved)
(reserved)(reserved)
(reserved)(reserved)
(reserved) (reserved) (reserved) (reserved)
(reserved) (reserved)
SPICON
F8h 04h
F0h 00h
I2CCON
E8h 00h
ACC
E0h 00h
ADCCON2
D8h 00h
PSW
D0h 00h
T2CON
C8h 00h
WDCON
C0h 10h
IP
B8h 00h
P3
B0h FFh
IE
A8h 00h
P2
A0h FFh
SCON
98h 00h
P1
90h FFh
TCON
88h 00h
P0
80h FFh
DAC0L
F9h 00h
ADCOFSL
F1h *00h
ADCDATAL
D9h 00h
ECON
B9h 00h
IEIP2
A9h A0h
S UF
99h 00h
TMOD
89h 00h
SP
81h 07h
DAC0H
FAh 00h
ADCOFSH
F2h *20h
ADCDATAH
DAh 00h
DMAL
D2h 00h
RCAP2L
CAh 00h
TL0
8Ah 00h
DPL
82h 00h
DAC1L
FBh 00h
ADCGAINL
F3h *00h
DMAH
D3h 00h
RCAP2H
CBh 00h
TL1
8Bh 00h
DPH
83h 00h
DAC1H
FCh 00h
ADCGAINH
F4h *00h
DMAP
D4h 00h
TL2
CCh 00h
EDATA1
BCh 00h
TH0
8Ch 00h
DPP
84h 00h
DACCON
FDh 04h
ADCCON3
F5h 00h
TH2
CDh 00h
EDATA2
BDh 00h
TH1
8Dh 00h
EADRL
C6h 00h
EDATA3
BEh 00h
SPIDAT
F7h 00h
ADCCON1
EFh 00h
PSMCON
DFh DEh
EDATA4
BFh 00h
PCON
87h 00h
SPR0
F8h 0
F0h 0
I2CI
E8h 0
E0h 0
CS0
D8h 0
P
D0h 0
CAP2
C8h 0
WDWR
C0h 0
PX0
B8h 0
RXD
B0h 1
EX0
A8h 0
A0h 1
RI
98h 0
T2
90h 1
IT0
88h 0
80h 1
SPR1
F9h 0
F1h 0
I2CTX
E9h 0
E1h 0
CS1
D9h 0
F1
D1h 0
CNT2
C9h 0
WDE
C1h 0
PT0
B9h 0
TXD
B1h 1
ET0
A9h 0
A1h 1
TI
99h 0
T2EX
91h 1
IE0
89h 0
81h 1
CPHA
FAh 1
F2h 0
I2CRS
EAh 0
E2h 0
CS2
DAh 0
OV
D2h 0
TR2
CAh 0
WDS
C2h 0
PX1
BAh 0
INT0
B2h 1
EX1
AAh 0
A2h 1
R 8
9Ah 0
92h 1
IT1
8Ah 0
82h 1
CPOL
FBh 0
F3h 0
I2CM
EBh 0
E3h 0
CS3
DBh 0
RS0
D3h 0
EXEN2
CBh 0
WDIR
C3h 0
PT1
BBh 0
INT1
B3h 1
ET1
ABh 0
A3h 1
T 8
9Bh 0
93h 1
IE1
8Bh 0
83h 1
SPIM
FCh 0
F4h 0
MDI
ECh 0
E4h 0
SCONV
DCh 0
RS1
D4h 0
TCLK
CCh 0
C4h 1
PS
BCh 0
T0
B4h 1
ES
ACh 0
A4h 1
REN
9Ch 0
94h 1
TR0
8Ch 0
84h 1
SPE
FDh 0
F5h 0
MCO
EDh 0
E5h 0
CCONV
DDh 0
F0
D5h 0
RCLK
CDh 0
PRE1
C5h 0
PT2
BDh 0
T1
B5h 1
ET2
ADh 0
A5h 1
SM2
9Dh 0
95h 1
TF0
8Dh 0
85h 1
WCOL
FEh 0
F6h 0
MDE
EEh 0
E6h 0
DMA
DEh 0
AC
D6h 0
EXF2
CEh 0
PRE2
C6h 0
PADC
BEh 0
WR
B6h 1
EADC
AEh 0
A6h 1
SM1
9Eh 0
96h 1
TR1
8Eh 0
86h 1
ISPI
FFh 0
F7h 0
MDO
EFh 0
E7h 0
ADCI
DFh 0
CY
D7h 0
TF2
CFh 0
PRE3
C7h 0
PSI
BFh 0
RD
B7h 1
EA
AFh 0
A7h 1
SM0
9Fh 0
97h 1
TF1
8Fh 0
87h 1
SPR0
F8h 0
SPICON
F8h 04h
SPR1
F9h 0
mnemonic
reset value
address
mnemonic
address
reset value
these bits this byte
are contained in
* calibration coefficients are preconfigured at power-up to factory calibrated values
7Fh
...
30h
2Fh
2Eh
2Dh
2Ch
2Bh
2Ah
29h
28h
27h
26h
25h
24h
23h
22h
21h
20h
1Fh R7
1Eh R6
1Dh R5
1Ch R4
1Bh R3
1Ah R2
19h R1
18h R0
17h R7
16h R6
15h R5
14h R4
13h R3
12h R2
11h R1
10h R0
0Fh R7
0Eh R6
0Dh R5
0Ch R4
0Bh R3
0Ah R2
09h R1
08h R0
07h R7
06h R6
05h R5
04h R4
03h R3
02h R2
01h R1
00h R0
General Purpose
Area
it Addressable
Area
Register ank 3
7Fh 7Eh 7Dh 7Ch 7Bh 7Ah 79h 78h
77h 76h 75h 74h 73h 72h 71h 70h
6Fh 6Eh 6Dh 6Ch 6Bh 6Ah 69h 68h
67h 66h 65h 64h 63h 62h 61h 60h
5Fh 5Eh 5Dh 5Ch 5Bh 5Ah 59h 58h
57h 56h 55h 54h 53h 52h 51h 50h
4Fh 4Eh 4Dh 4Ch 4Bh 4Ah 49h 48h
47h 46h 45h 44h 43h 42h 41h 40h
3Fh 3Eh 3Dh 3Ch 3Bh 3Ah 39h 38h
37h 36h 35h 34h 33h 32h 31h 30h
2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h
27h 26h 25h 24h 23h 22g 21h 20h
1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h
17h 16h 15h 14h 13h 12h 11g 10h
0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h
07h 06h 05h 04h 03h 02h 01h 00h
127
...
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
decimal
address
HEX
address
(bit addresses)
4K bytes
(1K pages)
data
Flash/EE
(accessible
through
SFRs)
CFG832.0=0
external
data
memory
(16M bytes
addressable)
MSB
address
LSB
address
3FFh
000h ( page 0 )
( page 1023 )
Register ank 2 Register ank 1 Register ank 0
CFG832.0=1
internal
data
memory
2K bytes
000h
FFFFFFh
7FFh
PLLCON
D7h 53h
CHIPID
C2h 2Xh
EADRH
C7h 00h
PWM0L
B1h 00h
PWM0H
B2h 00h
PWM1L
B3h 00h
PWM1H
B4h 00h
SPH
B7h 00h
CFG832
AFh 00h
PWMCON
AEh 00h
TIMECON
A1h 00h
HTHSEC
A2h 00h
SEC
A3h 00h
MIN
A4h 00h
HOUR
A5h 00h
INTVAL
A6h 00h
DPCON
A7h 00h
T3FD
9Dh 00h
T3CON
9Eh 00h
PRE0
I2CDAT
9Ah 00h
I2CADD
9Bh 55h
SFR MAP & RESET VALUES
SFR DESCRIPTIONS
DATA MEMORY: RAM, SFRs, user Flash/EE (all read/write)
MAP KEY
DATA MEMORY SPACE
(read/write area)
LOWER RAM
SFR details
DACCON.7 ModeSelect (0=12bit, 1=8bit)
DACCON.6 DAC1 RangeSelect (0=V
REF
, 1=V
DD
)
DACCON.5 DAC0 RangeSelect (0=V
REF
, 1=V
DD
)
DACCON.4 Clear DAC1 (0=0V, 1=normal operation)
DACCON.3 Clear DAC0 (0=0V, 1=normal operation)
DACCON.2 SynchronousUpdate (1=asynchronous)
DACCON.1 PowerDown DAC1 (0=off, 1=on)
DACCON.0 PowerDown DAC0 (0=off, 1=on)
ADCCON3.7 busy indicator flag (0=ADC not active)
ADCCON3.6 gain calibration disable (0=gain cal enabled)
ADCCON3.5 number of averages selection bits:
ADCCON3.4 [15,1,31,63]
ADCCON3.3 cal clock divide select (0=ADCclk, 1=ADCclk/2)
ADCCON3.2 cal mode select (0=device, 1=system)
ADCCON3.1 cal type select (0=offset, 1=gain)
ADCCON3.0 start calibration bit, cleared by hardware
DACCON
DAC Control register
DAC1H,DAC1L
DAC1 data registers
ADCCON3
ADC Control register #3
ADCGAINH
ADC Gain
calibration coefficients
ADCGAINL
ADCOFSH
ADCOFSL
ADC Offset
calibration coefficients
auxiliary math register
ACC
Accumulator
PSMCON
Power Supply Monitor control register
PSMCON.6 PSM status bit (1=normal / 0=fault)
PSMCON.5 PSM interrupt bit
PSMCON.4 trip point select bits
PSMCON.3 [4.37V, 3.08V, 2.93V, 2.63V]
PSMCON.2 (this bit must contain zero)
PSMCON.1 (reserved)
PSMCON.0 PSM powerdown control (1=on / 0=off)
ADCDATAH
ADC Data registers
ADCDATAL
DMAP,DMAH,DMAL
DMA address pointer
CY carry flag
AC auxiliary carry flag
F0 general purpose flag 0
RS1 register bank select control bits
RS0 active register bank = [0,1,2,3]
OV overflow flag
F1 general purpose flag 1
P parity of ACC
DAC0H,DAC0L
DAC0 data registers
PSW
Program Status Word
TH2,TL2
Timer2 register
RCAP2H,RCAP2L
Timer2 Reload/Capture
TF2 overflow flag
EXF2 external flag
RCLK receive clock enable (0=Timer1 used for RxD clk)
TCLK transmit clock enable (0=Timer1 used for TxD clk)
EXEN2 external enable (0=ignore T2EX, 1=cap/rld on T2EX)
TR2 run control (0=stop, 1=run)
CNT2 timer/counter select (0=timer, 1=counter)
CAP2 capture/reload select (0=reload, 1=capture)
T2CON
Timer2 Control register
PS priority of SP / 2C (serial interface interrupt)
PAD C priority of ADC (ADC interrupt)
PT2 priority of TF2/EXF2 (Timer2 overflow interrupt)
PS priority of R /T (serial port interrupt)
PT1 priority of TF1 (Timer1 overflow interrupt)
PX1 priority of E1 (external interrupt 1)
PT0 priority of TF0 (Timer0 overflow interrupt)
PX0 priority of E0 (external interrupt 0)
IP
nterrupt Priority register
RD external data memory read strobe
WR external data memory write strobe
T1 timer/counter 1 external input
T0 timer/counter 0 external input
NT1 external interrupt 1
NT0 external interrupt 0
TxD serial port transmit data line
RxD serial port receive data line
P3
Port3 register
EA enable inturrupts (0=all inturrupts disabled)
EADC enable ADC (ADC interrupt)
ET2 enable TF2/EXF2 (Timer2 overflow interrupt)
ES enable R /T (serial port interrupt)
ET1 enable TF1 (Timer1 overflow interrupt)
EX1 enable E1 (external interrupt 1)
ET0 enable TF0 (Timer0 overflow interrupt)
EX0 enable E0 (external interrupt 0)
IE
nterrupt Enable register #1
P2
Port2 register
(also A8-A15 & A16-A23)
S UF
Serial port Buffer register
SM0 UART mode control bits baud rate:
SM1 00 - 8bit shift register - F
OSC
/12
01 - 8bit UART - variable
10 - 9bit UART - F
OSC
/64(x2)
11 - 9bit UART - variable
SM2 in modes 2&3, enables multiprocessor communication
REN receive enable control bit
TB8 in modes 2&3, 9th bit transmitted
RB8 in modes 2&3, 9th bit received
T transmit interrupt flag
R receive interrupt flag
SCON
Serial communications Control register
T2EX timer/counter 2 capture/reload trigger
T2 timer/counter 2 external input
P1
Port1 register (analog & digital inputs)
TH0,TL0
Timer0 registers
TH1,TL1
Timer1 registers
TMOD.3/.7 gate control bit (0=ignore NTx)
TMOD.2/.6 counter/timer select bit (0=timer)
TMOD.1/.5 timer mode selecton bits
TMOD.0/.4 [13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]
(upper nibble = Timer1, lower nibble = Timer0)
TMOD
Timer Mode register
TF1 Timer1 overflow flag (auto cleared on vector to SR)
TR1 Timer1 run control (0=off, 1=run)
TF0 Timer0 overflow flag (auto cleared on vector to SR)
TR0 Timer0 run control (0=off, 1=run)
E1 external NT1 flag (auto cleared on vector to SR)
T1 E1 type (0=level trig, 1=edge trig)
E0 external NT0 flag (auto cleared on vector to SR)
T0 E0 type (0=level trig, 1=edge trig)
TCON
Timer Control register
PCON.7 double baud rate control
PCON.4 ALE disable (0=normal, 1=forces ALE high)
PCON.3 general purpose flag
PCON.2 general purpose flag
PCON.1 power-down control bit (recoverable with hard reset)
PCON.0 idle-mode control (recoverable with enabled interrupt)
PCON
Power Control register
DPP
Data Pointer Page
DPH,DPL (DPTR)
Data Pointer
SP
Stack Pointer
P0
Port0 register
(also A0-A7 & D0-D7)
ADCCON1.7 ADC mode (0=off, 1=on)
ADCCON1.6 external Vref select bit (0=on-chip Vref)
ADCCON1.5 conversion time = 16 / ADCclk
ADCCON1.4 ADCclk = 16,777,216Hz / [8,4,16,32]
ADCCON1.3 acquisition time select bits
ADCCON1.2 acq time = [1,2,3,4] / ADCclk
ADCCON1.1 Timer2 convert enable
ADCCON1.0 external CONVST enable
ADCCON1
ADC Control register #1
ADCCON2
ADC Control register #2
ADC ADC interrupt flag
DMA DMA mode enable
CCONV continuous conversion enable bit
SCONV single conversion start bit
CS3 input channel select bits:
CS2 0 - 7 = ADC0 - ADC7
CS1 8 = temperature sensor
CS0 9=DAC0, A=DAC1, B=AGND
PLLCON.7 oscillator powerdown control bit (0=XTAL on)
PLLCON.6 PLL lock indicator flag (0=out of lock)
PLLCON.5 (this bit must contain zero)
PLLCON.4 (this bit must contain zero)
PLLCON.3 fast interrupt control bit (0=normal)
PLLCON.2 3-bit clock divider value, CD (default=3):
PLLCON.1
PLLCON.0
PLLCON
PLL Control register
f
CORE
= 16,777,216Hz / 2
CD
T MECON.6 (this bit must contain 1)
T MECON.5 NTVAL timebase select bits
T MECON.4 [128th sec, seconds, minutes, hours]
T MECON.3 single time interval control bit (0=reload&restart)
T MECON.2 time interval interrupt bit, T
T MECON.1 time interval enable bit (0=disable&clear)
T MECON.0 time clock enable bit (0=disable)
TIMECON
Time nterval Counter Control Register
HTHSEC
T C Elapsed 128th Second Register
SEC
T C Elapsed Seconds Register
MIN
T C Elapsed Minutes Register
HOUR
T C Elapsed Hours Register
INTVAL
T C nterval Register
CFG832
ADuC832 Configuration Register
CFG832.7 extended stack-pointer enable (0=disable)
CFG832.6 PWM pins select (0=P2.6/P2.7,1=P3.4/P3.3)
CFG832.5 DAC output buffer bypass (0=buffer enabled)
CFG832.4 external clock select (0=internal clock)
CFG832.3 (this bit must contain 0)
CFG832.2 (this bit must contain 0)
CFG832.1 (this bit must contain 0)
CFG832.0 internal XRAM select (0=external XRAM)
EADRH,EADRL
Data Flash/EE address registers
EDATA1,EDATA2,EDATA3,EDATA4
Data Flash/EE data registers
01h READ page
02h PROGRAM page
04h VER FY page
05h ERASE page
06h ERASE ALL
ECON
Data Flash/EE comand register
82h PROGRAM byte
0Fh EX T ULOAD mode
F0h ENTER ULOAD mode
(all others reserved)
SP SP inturrupt (set at end of SP transfer)
WCOL write collision error flag
SPE SP enable (0= 2C enable, 1=SP enable)
SP M master mode select (0=slave)
CPOL clock polarity select (0=SCLK idles low)
CPHA clock phase select (0=leading edge latch)
SPR1 SP bitrate select bits
SPR0 bitrate = Fcore / [2,4,8,16] (slave: SPR0=SS)
SPICON
SP Control register
SPIDAT
SP Data register
PRE3 watchdog timeout selection bits
PRE2 0-7=[15.6,31.2,62.5,125,250,500,1000,2000]ms
PRE1 8=0ms (immediate reset)
PRE0 >8=reserved
WD R watchdog interrupt response bit
WDS watchdog status flag (1 indicates watchdog timeout)
WDE watchdog enable control (0=disabled)
WDWR watchdog write enable bit (set to enable write)
WDCON
Watchdog Timer control register
E P2.6 priority of T interrupt (time interval)
E P2.5 priority of PSM interrupt (power supply monitor)
E P2.4 priority of SP interrupt (serial interface)
E P2.3 (this bit must contain zero)
E P2.2 enable T interrupt (time interval)
E P2.1 enable PSM (power supply monitor interrupt)
E P2.0 enable SP interrupt (serial interface)
IEIP2
nterrupt Enable/Priority register #2
CHIPID
Chip D Register
(2X hex = ADuC832)
SPH
Stack Pointer High byte
PWMCON
PWM Control register
PWMCON.6 PWM mode bits [0=disabled, 1=single/var.res.,
PWMCON.5 2=twin/8bit, 3=twin/16bit, 4=dual/16bitNRZ,
PWMCON.4 5=dual/8bit, 6=dual/16bitRZ, 7=(reserved)]
PWMCON.3 PWM clock divide bits
PWMCON.2 PWM counter = clock / [1,4,16,64]
PWMCON.1 PWM clock source bits [1=F
XTAL
/15, 2=F
XTAL
,
PWMCON.0 3=T0 ext.int.rate, 4=F
VCO
(16.777MHz)]
PWM0H,PWM0L
PWM0 data registers
PWM1H,PWM1L
PWM1 data registers
DPCON
Data Pointer Control register
DPCON.6 data pointer auto-toggle enable (0=disable)
DPCON.5 shadow data pointer mode control bits
DPCON.4 [1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
DPCON.3 main data pointer mode control bits
DPCON.2 [1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
DPCON.1 (not implemented to allow NC DPCON toggling)
DPCON.0 data pointer select [0=main, 1=shadow]
T3CON
Timer 3 Control register
T3CON.7 Timer 3 baud rate enable (0=disable)
T3CON.2 binary divide factor (D V)
T3CON.1 D V = log[F
CORE
/(32·baudrate)] / log2
T3CON.0 (rounded down)
T3FD
Timer 3 Fractional Divider register
T3FD = (2·F
CORE
) / (baudrate·2
D V
) - 64
MDO master mode SDATA output bit
MDE master mode SDATA output enable (0=disable)
MCO master mode SCLK output bit
MD master mode SDATA input bit
2CM master mode select bit (0=slave mode)
2CRS serial port reset
2CTX transmission direction status (0=RX,1=TX)
2C serial interface interrupt
I2CCON
2C Control register
I2CADD
2C Address register
I2CDAT
2C Data register
lower RAM
details
SFRs
(direct
addressing
only)
128 bytes
upper RAM
(indirect
addressing
only)
128 bytes
lower RAM
(direct or
indirect
addressing)
00h
FFh
