Atmel AVR AT90S2333 Bedienungsanleitung

Pin Configurations

TQFP Top View PDIP

(INT1) PD3

(T0) PD4

VCC

GND

XTAL1

XTAL2

PC1 (ADC1)

PC0 (ADC0)

AGND

AREF

AVCC

PB5 (SCK)

(T1) PD5

(AIN0) PD6

(AIN1) PD7

(ICP) PB0

(OC1) PB1

(SS) PB2

(MOS1) PB3

(MOS0) PB4

PD2 (INT0)

PD1 (TXD)

PD0 (RDX)

RESET

PC5 (ADC5)

PC4 (ADC4)

PC3 (ADC3)

PC2 (ADC2)

RESET

(RXD) PD0

(TXD) PD1

(INT0) PD2

(INT1) PD3

(T0) PD4

VCC

GND

XTAL1

XTAL2

(T1) PD5

(AIN0) PD6

(AIN1) PD7

(ICP) PB0

PC5 (ADC5)

PC4 (ADC4)

PC3 (ADC3)

PC2 (ADC2)

PC1 (ADC1)

PC0 (ADC0)

AGND

AREF

AVCC

PB5 (SCK)

PB4 (MISO)

PB3 (MOSI)

PB2 (SS)

PB1 (OC1)

Features

•High-performance and Low-power AVR®8-bit RISC Architecture

– 118 Powerful Instructions - Most Single Cycle Execution

– 32 x 8 General Purpose Working Registers

– Up to 8 MIPS Throughput at 8 MHz

•Data and Nonvolatile Program Memory

– 2K/4K Bytes of In-System Programmable Flash

Endurance 1,000 Write/Erase Cycles

– 128 Bytes of SRAM

– 128/256 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

•Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler

– Expanded 16-bit Timer/Counter with Separate Prescaler,

Compare, Capture Modes and 8-, 9- or 10-bit PWM

– On-chip Analog Comparator

– Programmable Watchdog Timer with Separate On-chip Oscillator

– Programmable UART

– 6-channel, 10-bit ADC

– Master/Slave SPI Serial Interface

•Special Microcontroller Features

– Brown-Out Reset Circuit

– Enhanced Power-on Reset Circuit

– Low-Power Idle and Power Down Modes

– External and Internal Interrupt Sources

•Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

•Power Consumption at 4 MHz, 3V, 25°C

– Active: 3.4 mA

– Idle Mode: 1.4 mA

– Power Down Mode: <1 µA

•I/O and Packages

– 20 Programmable I/O Lines

– 28-pin PDIP and 32-pin TQFP

•Operating Voltage

– 2.7V - 6.0V (AT90LS2333 and AT90LS4433)

– 4.0V - 6.0V (AT90S2333 and AT90S4433)

•Speed Grades

– 0 - 4 MHz (AT90LS2333 and AT90LS4433)

– 0 - 8 MHz (AT90S2333 and AT90S4433)

Rev. 1042D–04/99

8-bit

Microcontroller

with 2K/4K bytes

In-System

Programmable

Flash

AT90S2333

AT90LS2333

AT90S4433

AT90LS4433

Preliminary

AT90S/LS2333 and AT90S/LS4433

Description

The AT90S2333/4433 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing pow-

erful instructions in a single clock cycle, the AT90S2333/4433 achieves throughputs approaching 1 MIPS per MHz allowing

the system designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly

connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction

executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times

faster than conventional CISC microcontrollers.

The AT90S2333/4433 provides the following features: 2K/4K bytes of In-System Programmable Flash, 128/256 bytes

EEPROM, 128 bytes SRAM, 20 general purpose I/O lines, 32 general purpose working registers, two flexible

timer/counters with compare modes, internal and external interrupts, a programmable serial UART, 6-channel, 10-bit ADC,

programmable Watchdog Timer with internal oscillator, an SPI serial port and two software selectable power saving modes.

The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue function-

ing. The Power Down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the

next interrupt or hardware reset.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The on-chip Flash program mem-

ory can be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer.

By combining a RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S2333/4433 is a

powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The AT90S2333/4433 AVR is supported with a full suite of program and system development tools including: C compilers,

macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

Table 1. Comparison Table

Device Flash EEPROM SRAM Voltage Range Frequency

AT90S2333 2K 128B 128B 4.0V - 6.0V 0 - 8 MHz

AT90LS2333 2K 128B 128B 2.7V - 6.0V 0 - 4 MHz

AT90S4433 4K 256B 128B 4.0V - 6.0V 0 - 8 MHz

AT90LS4433 4K 256B 128B 2.7V - 6.0V 0 - 4 MHz

AT90S/LS2333 and AT90S/LS4433

Block Diagram

Figure 1. The AT90S2333/4433 Block Diagram

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH MCU CONTROL

SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTC

DATA REGISTER

PORTB

DATA REGISTER

PORTC

ANALOG MUX ADC

DATA REGISTER

PORTD

PROGRAMMING

LOGIC

TIMING AND

CONTROL

OSCILLATOR

INTERRUPT

UNIT

EEPROM

SPI UART

STATUS

ALU

PORTB DRIVERS

PORTC DRIVERS

PORTD DRIVERS

PB0 - PB5

PC0 - PC5

RESET

VCC

AVCC

AGND

AREF

GND

XTAL2

XTAL1

CONTROL

LINES

ANALOG

COMPARATOR

PD0 - PD7

8-BIT DATA BUS

DATA DIR.

REG. PORTD

AT90S/LS2333 and AT90S/LS4433

Pin Descriptions

VCC

Supply voltage

GND

Ground

Port B (PB5..PB0)

Port B is a 6-bit bi-directional I/O port with internal pullup resistors. The Port B output buffers can sink 20 mA. As inputs,

Port B pins that are externally pulled low will source current if the pull-up resistors are activated.

Port B also serves the functions of various special features of the AT90S2333/4433 as listed on page 60.

The port B pins are tristated when a reset condition becomes active, even if the clock is not running.

Port C (PC5..PC0)

Port C is a 6-bit bi-directional I/O port with internal pullup resistors. The Port C output buffers can sink 20 mA. As inputs,

Port C pins that are externally pulled low will source current if the pull-up resistors are activated. Port C also serves as the

analog inputs to the A/D Converter.

The port C pins are tristated when a reset condition becomes active, even if the clock is not running.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs,

Port D pins that are externally pulled low will source current if the pull-up resistors are activated.

Port D also serves the functions of various special features of the AT90S2333/4433 as listed on page 67.

The port D pins are tristated when a reset condition becomes active, even if the clock is not running.

RESET

Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate

a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier

AVCC

This is the supply voltage pin for the A/D Converter. It should be externally connected to VCC via a low-pass filter. See

page 52 for details on operation of the ADC.

AREF

This is the analog reference input for the A/D Converter. For ADC operations, a voltage in the range 2.7V to AVCC must be

applied to this pin.

AGND

If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to

GND.

AT90S/LS2333 and AT90S/LS4433

Clock Options

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-

chip oscillator, as shown in Figure 2 and Figure 3. Either a quartz crystal or a ceramic resonator may be used.

External Clock

If the oscillator is to be used as a clock for an external device, the clock signal from XTAL2 may be routed to one HC buffer,

while reducing the load capacitor by 5 pF, as shown in Figure 3. To drive the device from an external clock source, XTAL2

should be left unconnected while XTAL1 is driven as shown in Figure 4.

Figure 2. Oscillator Connections

Figure 3. Using MCU Oscillator as a Clock for an External Device

Figure 4. External Clock Drive Configuration

XTAL1

REDUCE BY 5PF

MAX 1 HC BUFFER

XTAL2

AT90S/LS2333 and AT90S/LS4433

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access

time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands

are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock

cycle.

Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling

efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table

look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register

operations are also executed in the ALU. Figure 5 shows the AT90S2333/4433 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.

This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing

them to be accessed as though they were ordinary memory locations.

Figure 5. The AT90S2333/4433 AVR RISC Architecture

1K/2K X 16

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control Interrupt

Unit

SPI

Unit

8-bit

Timer/Counter

Watchdog

Timer

Analog to Digital

Converter

Analog

Comparator

I/O Lines

128/256 x 8

EEPROM

Data Bus 8-bit

AVR

AT90S2333/4433 Architecture

Serial

UART

16-bit

Timer/Counter

with PWM

128 x 8

Data

SRAM

Direct Addressing

Indirect Addressing

AT90S/LS2333 and AT90S/LS4433

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-

converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following

those of the register file, $20 - $5F.

The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program

memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched

from the program memory. This concept enables instructions to be executed in every clock cycle.

The program memory is In-System Programmable Flash memory.

With the relative jump and call instructions, the whole 1K/2K word address space is directly accessed. Most AVR instruc-

tions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effec-

tively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the

usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are exe-

cuted). The 8-bit stack pointer SP is read/write accessible in the I/O space.

The 128 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR

architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

Figure 6. AT90S2333/4433 Memory Maps

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status

register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro-

gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the

interrupt vector address, the higher the priority.

32 Gen. Purpose

Working Registers

64 I/O Registers

Internal SRAM

(128 x 8)

$0000

$001F

$005F

$0060

$00DF

$0020

$000

$3FF/ $7FF

Data MemoryProgram Memory

Program Flash

(1K/2K x 16)

AT90S/LS2333 and AT90S/LS4433

General Purpose Register File

Figure 7 shows the structure of the 32 general purpose working registers in the CPU.

Figure 7. AVR CPU General Purpose Working Registers

All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only

exceptions are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and

a register, and the LDI instruction for load immediate constant data. These instructions apply to the second half of the reg-

isters in the register file - R16..R31. The general SBC, SUB, CP, AND, and OR, and all other operations between two

registers or on a single register apply to the entire register file.

As shown in Figure 7, each register is also assigned a data memory address, mapping them directly into the first 32 loca-

tions of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization

provides great flexibility in access of the registers, as the X, Y and Z registers can be set to index any register in the file.

X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers

for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as:

Figure 8. X, Y and Z Registers

In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and

decrement (see the descriptions for the different instructions).

70Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register low byte

R27 $1B X-register high byte

R28 $1C Y-register low byte

R29 $1D Y-register high byte

R30 $1E Z-register low byte

R31 $1F Z-register high byte

15 0

X - register 7 0 7 0

R27 ($1B) R26 ($1A)

15 0

Y - register 7 0 7 0

R29 ($1D) R28 ($1C)

15 0

Z - register 7 0 7 0

R31 ($1F) R30 ($1E)

AT90S/LS2333 and AT90S/LS4433

ALU - Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a

single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into

three main categories - arithmetic, logical, and bit-functions.

In-System Programmable Flash Program Memory

The AT90S2333/4433 contains 2K/4K bytes on-chip In-System Programmable Flash memory for program storage. Since

all instructions are 16-or 32-bit words, the Flash is organized as 1K/2K x 16. The Flash memory has an endurance of at

least 1000 write/erase cycles. The AT90S2333/4433 Program Counter (PC) is 10/11 bits wide, thus addressing the

1024/2048 program memory addresses. See page 78 for a detailed description on Flash data downloading. See page 10

for the different program memory addressing modes.

Figure 9. SRAM Organization

SRAM Data Memory

The figure above shows how the AT90S2333/4433 SRAM Memory is organized.

The lower 224 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. The first 96

locations address the Register File and I/O Memory, and the next 128 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with

Pre-Decrement, and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the indirect addressing

pointer registers.

The direct addressing reaches the entire data space. The Indirect with Displacement mode features a 63 address locations

reach from the base address given by the Y or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,

Y and Z are decremented and incremented.

R0 $0000

R1 $0001

R2 $0002

……

R29 $001D

R30 $001E

R31 $001F

I/O Registers

$00 $0020

$01 $0021

$02 $0022

……

$3D $005D

$3E $005E

$3F $005F

Internal SRAM

$0060

$0061

…

$00DE

$00DF

AT90S/LS2333 and AT90S/LS4433

The 32 general purpose working registers, 64 I/O registers and the 128 bytes of internal data SRAM in the

AT90S2333/4433 are all accessible through all these addressing modes.

See the next section for a detailed description of the different addressing modes.

Program and Data Addressing Modes

The AT90S2333/4433 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the Flash

program memory, SRAM, Register File, and I/O data memory. This section describes the different addressing modes sup-

ported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all

figures show the exact location of the addressing bits.

Figure 10. Direct Single Register Addressing

The operand is contained in register d (Rd).

Figure 11. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

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